sys/arm/nvidia/tegra124/tegra124_car.c

275

DIV(0, "hclk_div", "sclk", CLK_SYSTEM_RATE, 4, 2, 0),

sys/arm/nvidia/tegra124/tegra124_car.c

276

DIV(0, "pclk_div", "hclk", CLK_SYSTEM_RATE, 0, 2, 0),

sys/arm64/freescale/imx/imx8mp_ccm.c

424

DIV(IMX8MP_CLK_CLKOUT1_DIV, "clkout1_div", "clkout1_sel", 0x128, 0, 4),

sys/arm64/freescale/imx/imx8mp_ccm.c

428

DIV(IMX8MP_CLK_CLKOUT2_DIV, "clkout2_div", "clkout2_sel", 0x128, 16, 4),

sys/arm64/freescale/imx/imx8mp_ccm.c

463

DIV(IMX8MP_CLK_IPG_ROOT, "ipg_root", "ahb_root", 0x9080, 0, 1),

sys/arm64/freescale/imx/imx8mq_ccm.c

146

DIV(IMX8MQ_ARM_PLL_REF_DIV, "arm_pll_ref_div", "arm_pll_ref_sel", 0x28, 5, 6),

sys/arm64/freescale/imx/imx8mq_ccm.c

147

DIV(IMX8MQ_GPU_PLL_REF_DIV, "gpu_pll_ref_div", "gpu_pll_ref_sel", 0x18, 5, 6),

sys/arm64/freescale/imx/imx8mq_ccm.c

148

DIV(IMX8MQ_VPU_PLL_REF_DIV, "vpu_pll_ref_div", "vpu_pll_ref_sel", 0x20, 5, 6),

sys/arm64/freescale/imx/imx8mq_ccm.c

149

DIV(IMX8MQ_AUDIO_PLL1_REF_DIV, "audio_pll1_ref_div", "audio_pll1_ref_sel", 0x0, 5, 6),

sys/arm64/freescale/imx/imx8mq_ccm.c

150

DIV(IMX8MQ_AUDIO_PLL2_REF_DIV, "audio_pll2_ref_div", "audio_pll2_ref_sel", 0x8, 5, 6),

sys/arm64/freescale/imx/imx8mq_ccm.c

151

DIV(IMX8MQ_VIDEO_PLL1_REF_DIV, "video_pll1_ref_div", "video_pll1_ref_sel", 0x10, 5, 6),

sys/arm64/freescale/imx/imx8mq_ccm.c

216

DIV(IMX8MQ_CLK_IPG_ROOT, "ipg_root", "ahb", 0x9080, 0, 1),

sys/arm64/nvidia/tegra210/tegra210_car.c

256

DIV(0, "hclk_div", "sclk", CLK_SYSTEM_RATE, 4, 2, 0),

sys/arm64/nvidia/tegra210/tegra210_car.c

257

DIV(0, "pclk_div", "hclk", CLK_SYSTEM_RATE, 0, 2, 0),

sys/riscv/sifive/sifive_prci.c

137

#define DIV_END DIV(0, NULL, NULL, 0, 0)

sys/riscv/sifive/sifive_prci.c

235

DIV(FU740_PRCI_PCLK, "pclk", "hfpclk", FU740_PRCI_HFPCLK_DIV, 2),