rq_cfg
sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG];
rq_cfg[i].rq_id = 0xffff;
rq_cfg[i].r_ctl_mask = (uint8_t) hw->config.filter_def[i];
rq_cfg[i].r_ctl_match = (uint8_t) (hw->config.filter_def[i] >> 8);
rq_cfg[i].type_mask = (uint8_t) (hw->config.filter_def[i] >> 16);
rq_cfg[i].type_match = (uint8_t) (hw->config.filter_def[i] >> 24);
if (i >= ARRAY_SIZE(rq_cfg)) {
rq_cfg[i].rq_id = hw->hw_rq[i]->hdr->id;
rq_cfg, domain->vlan_id)) {
sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG];
rq_cfg[i].rq_id = 0xffff;
rq_cfg[i].r_ctl_mask = (uint8_t) hw->config.filter_def[i];
rq_cfg[i].r_ctl_match = (uint8_t) (hw->config.filter_def[i] >> 8);
rq_cfg[i].type_mask = (uint8_t) (hw->config.filter_def[i] >> 16);
rq_cfg[i].type_match = (uint8_t) (hw->config.filter_def[i] >> 24);
rq_cfg[j].rq_id = rq->hdr->id;
if (sli_cmd_reg_fcfi(&hw->sli, buf, SLI4_BMBX_SIZE, 0, rq_cfg, 0)) {
mrq.rq_cfg[mrq.num_pairs].len = len;
mrq.rq_cfg[mrq.num_pairs].ulp = hw->ulp_start + qt->ulp;
mrq.rq_cfg[mrq.num_pairs].filter_mask = qt->filter_mask;
mrq.rq_cfg[mrq.num_pairs].eq = eq;
if ((i != j) && (mrq.rq_cfg[i].filter_mask == mrq.rq_cfg[j].filter_mask)) {
if (rqset_filter_mask && (rqset_filter_mask != mrq.rq_cfg[i].filter_mask)) {
rqset_filter_mask = mrq.rq_cfg[i].filter_mask;
rqset_len = mrq.rq_cfg[i].len;
rqset_ulp = mrq.rq_cfg[i].ulp;
eqs[rqset_count] = mrq.rq_cfg[i].eq;
cq = hw_new_cq(mrq.rq_cfg[i].eq, default_lengths[QTOP_CQ]);
rq = hw_new_rq(cq, mrq.rq_cfg[i].len, mrq.rq_cfg[i].ulp);
rq->filter_mask = mrq.rq_cfg[i].filter_mask;
} rq_cfg[16];
sli_cmd_reg_fcfi(sli4_t *sli4, void *buf, size_t size, uint16_t index, sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG], uint16_t vlan_id)
case 0: reg_fcfi->rq_id_0 = rq_cfg[0].rq_id; break;
case 1: reg_fcfi->rq_id_1 = rq_cfg[1].rq_id; break;
case 2: reg_fcfi->rq_id_2 = rq_cfg[2].rq_id; break;
case 3: reg_fcfi->rq_id_3 = rq_cfg[3].rq_id; break;
reg_fcfi->rq_cfg[i].r_ctl_mask = rq_cfg[i].r_ctl_mask;
reg_fcfi->rq_cfg[i].r_ctl_match = rq_cfg[i].r_ctl_match;
reg_fcfi->rq_cfg[i].type_mask = rq_cfg[i].type_mask;
reg_fcfi->rq_cfg[i].type_match = rq_cfg[i].type_match;
sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG])
reg_fcfi_mrq->rq_cfg[i].r_ctl_mask = rq_cfg[i].r_ctl_mask;
reg_fcfi_mrq->rq_cfg[i].r_ctl_match = rq_cfg[i].r_ctl_match;
reg_fcfi_mrq->rq_cfg[i].type_mask = rq_cfg[i].type_mask;
reg_fcfi_mrq->rq_cfg[i].type_match = rq_cfg[i].type_match;
case 3: reg_fcfi_mrq->rq_id_3 = rq_cfg[i].rq_id; break;
case 2: reg_fcfi_mrq->rq_id_2 = rq_cfg[i].rq_id; break;
case 1: reg_fcfi_mrq->rq_id_1 = rq_cfg[i].rq_id; break;
case 0: reg_fcfi_mrq->rq_id_0 = rq_cfg[i].rq_id; break;
} rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG];
} rq_cfg[SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG];
sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG], uint16_t);
extern int32_t sli_cmd_reg_fcfi_mrq(sli4_t *, void *, size_t, uint8_t, uint16_t, uint16_t, uint8_t, uint8_t , uint16_t, sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG]);
struct rq_cfg rq_cfg;
rq_cfg.ena = 1;
rq_cfg.tcp_ena = 0;
*(uint64_t *)&rq_cfg);