sys/arm64/include/vmm.h

133

reg_write_t reg_write;

sys/arm64/include/vmm_instruction_emul.h

83

reg_read_t reg_read, reg_write_t reg_write, void *arg);

sys/arm64/vmm/vmm.c

465

.reg_write = (_write), \

sys/arm64/vmm/vmm.c

477

.reg_write = vmm_reg_wi, \

sys/arm64/vmm/vmm.c

500

.reg_write = vmm_reg_wi,

sys/arm64/vmm/vmm.c

523

reg_read_t reg_read, reg_write_t reg_write, void *arg)

sys/arm64/vmm/vmm.c

533

vm->special_reg[i].reg_write = reg_write;

sys/arm64/vmm/vmm.c

581

vm->special_reg[i].reg_write,

sys/arm64/vmm/vmm.c

594

vmm_special_regs[i].reg_write,

sys/dev/ichiic/ig4_iic.c

1002

reg_write(sc, IG4_REG_SS_SCL_HCNT, sc->cfg.ss_scl_hcnt);

sys/dev/ichiic/ig4_iic.c

1003

reg_write(sc, IG4_REG_SS_SCL_LCNT, sc->cfg.ss_scl_lcnt);

sys/dev/ichiic/ig4_iic.c

1004

reg_write(sc, IG4_REG_FS_SCL_HCNT, sc->cfg.fs_scl_hcnt);

sys/dev/ichiic/ig4_iic.c

1005

reg_write(sc, IG4_REG_FS_SCL_LCNT, sc->cfg.fs_scl_lcnt);

sys/dev/ichiic/ig4_iic.c

1006

reg_write(sc, IG4_REG_SDA_HOLD,

sys/dev/ichiic/ig4_iic.c

1010

reg_write(sc, IG4_REG_RX_TL, 0);

sys/dev/ichiic/ig4_iic.c

1011

reg_write(sc, IG4_REG_TX_TL, 0);

sys/dev/ichiic/ig4_iic.c

1013

reg_write(sc, IG4_REG_CTL,

sys/dev/ichiic/ig4_iic.c

1037

reg_write(sc, IG4_REG_TX_TL, v | IG4_FIFO_MASK);

sys/dev/ichiic/ig4_iic.c

1040

reg_write(sc, IG4_REG_TX_TL, v);

sys/dev/ichiic/ig4_iic.c

1044

reg_write(sc, IG4_REG_RX_TL, v | IG4_FIFO_MASK);

sys/dev/ichiic/ig4_iic.c

1047

reg_write(sc, IG4_REG_RX_TL, v);

sys/dev/ichiic/ig4_iic.c

1118

reg_write(sc, IG4_REG_INTR_MASK, 0);

sys/dev/ichiic/ig4_iic.c

1143

reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE);

sys/dev/ichiic/ig4_iic.c

1149

reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);

sys/dev/ichiic/ig4_iic.c

180

reg_write(sc, IG4_REG_INTR_MASK, val);

sys/dev/ichiic/ig4_iic.c

253

reg_write(sc, IG4_REG_I2C_EN, ctl);

sys/dev/ichiic/ig4_iic.c

353

reg_write(sc, IG4_REG_TX_TL, 0);

sys/dev/ichiic/ig4_iic.c

366

reg_write(sc, IG4_REG_CTL, ctl);

sys/dev/ichiic/ig4_iic.c

367

reg_write(sc, IG4_REG_TAR_ADD, tar);

sys/dev/ichiic/ig4_iic.c

445

reg_write(sc, IG4_REG_TX_TL, IG4_FIFO_LOWAT);

sys/dev/ichiic/ig4_iic.c

462

reg_write(sc, IG4_REG_DATA_CMD, cmd);

sys/dev/ichiic/ig4_iic.c

478

reg_write(sc, IG4_REG_RX_TL,

sys/dev/ichiic/ig4_iic.c

512

reg_write(sc, IG4_REG_DATA_CMD, cmd);

sys/dev/ichiic/ig4_iic.c

520

reg_write(sc, IG4_REG_TX_TL, lowat);

sys/dev/ichiic/ig4_iic.c

930

reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED);

sys/dev/ichiic/ig4_iic.c

931

reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0);

sys/dev/ichiic/ig4_iic.c

937

reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);

sys/dev/ichiic/ig4_iic.c

938

reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);

sys/dev/ichiic/ig4_iic.c

940

reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);

sys/dev/ichiic/ig4_iic.c

941

reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);

sys/dev/ichiic/ig4_iic.c

974

reg_write(sc, IG4_REG_GENERAL, v);

sys/dev/ichiic/ig4_iic.c

999

reg_write(sc, IG4_REG_INTR_MASK, 0);

sys/riscv/include/vmm_instruction_emul.h

83

reg_read_t reg_read, reg_write_t reg_write, void *arg);