reg_wr
rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr);
err = build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr),
err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr),
struct irdma_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
irdma_get_mr_access(reg_wr(ib_wr)->access,
stag_info.stag_key = reg_wr(ib_wr)->key & 0xff;
stag_info.stag_idx = reg_wr(ib_wr)->key >> 8;
stag_info.page_size = reg_wr(ib_wr)->mr->page_size;
set_reg_seg(wqe, reg_wr(wr));
ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
rc = qlnxr_prepare_reg(qp, fwqe1, reg_wr(wr));
struct ib_reg_wr reg_wr;