reg_read - FreeBSD

sys/arm64/include/vmm.h

132

reg_read_t reg_read;

sys/arm64/include/vmm_instruction_emul.h

83

reg_read_t reg_read, reg_write_t reg_write, void *arg);

sys/arm64/vmm/vmm.c

464

.reg_read = (_read), \

sys/arm64/vmm/vmm.c

476

.reg_read = vmm_reg_read_arg, \

sys/arm64/vmm/vmm.c

499

.reg_read = vmm_reg_raz,

sys/arm64/vmm/vmm.c

523

reg_read_t reg_read, reg_write_t reg_write, void *arg)

sys/arm64/vmm/vmm.c

532

vm->special_reg[i].reg_read = reg_read;

sys/arm64/vmm/vmm.c

580

vm->special_reg[i].reg_read,

sys/arm64/vmm/vmm.c

593

vmm_special_regs[i].reg_read,

sys/dev/ichiic/ig4_iic.c

1036

v = reg_read(sc, IG4_REG_TX_TL);

sys/dev/ichiic/ig4_iic.c

1039

(reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1;

sys/dev/ichiic/ig4_iic.c

1043

v = reg_read(sc, IG4_REG_RX_TL);

sys/dev/ichiic/ig4_iic.c

1046

(reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1;

sys/dev/ichiic/ig4_iic.c

1193

if (sc->intr_mask != 0 && reg_read(sc, IG4_REG_INTR_STAT) != 0) {

sys/dev/ichiic/ig4_iic.c

1205

device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg))

sys/dev/ichiic/ig4_iic.c

191

reg_read(sc, IG4_REG_CLR_RX_UNDER);

sys/dev/ichiic/ig4_iic.c

193

reg_read(sc, IG4_REG_CLR_RX_OVER);

sys/dev/ichiic/ig4_iic.c

195

reg_read(sc, IG4_REG_CLR_TX_OVER);

sys/dev/ichiic/ig4_iic.c

198

src = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);

sys/dev/ichiic/ig4_iic.c

199

reg_read(sc, IG4_REG_CLR_TX_ABORT);

sys/dev/ichiic/ig4_iic.c

251

reg_read(sc, IG4_REG_CLR_INTR);

sys/dev/ichiic/ig4_iic.c

257

v = reg_read(sc, IG4_REG_ENABLE_STATUS);

sys/dev/ichiic/ig4_iic.c

283

v = reg_read(sc, IG4_REG_RAW_INTR_STAT);

sys/dev/ichiic/ig4_iic.c

294

v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;

sys/dev/ichiic/ig4_iic.c

357

ctl = reg_read(sc, IG4_REG_CTL);

sys/dev/ichiic/ig4_iic.c

386

reg_read(sc, IG4_REG_CLR_INTR);

sys/dev/ichiic/ig4_iic.c

399

return ((reg_read(sc, IG4_REG_RAW_INTR_STAT) &

sys/dev/ichiic/ig4_iic.c

443

(reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);

sys/dev/ichiic/ig4_iic.c

450

(reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);

sys/dev/ichiic/ig4_iic.c

472

reg_read(sc, IG4_REG_RXFLR) & IG4_FIFOLVL_MASK);

sys/dev/ichiic/ig4_iic.c

476

reg_read(sc, IG4_REG_DATA_CMD);

sys/dev/ichiic/ig4_iic.c

504

(reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);

sys/dev/ichiic/ig4_iic.c

619

reg_read(sc, IG4_REG_CLR_TX_ABORT);

sys/dev/ichiic/ig4_iic.c

651

reg_read(sc, IG4_REG_CLR_INTR);

sys/dev/ichiic/ig4_iic.c

666

while (reg_read(sc, IG4_REG_I2C_STA) &

sys/dev/ichiic/ig4_iic.c

668

reg_read(sc, IG4_REG_DATA_CMD);

sys/dev/ichiic/ig4_iic.c

669

reg_read(sc, IG4_REG_TX_ABRT_SOURCE);

sys/dev/ichiic/ig4_iic.c

670

reg_read(sc, IG4_REG_CLR_INTR);

sys/dev/ichiic/ig4_iic.c

835

sc->cfg.version = reg_read(sc, IG4_REG_COMP_VER);

sys/dev/ichiic/ig4_iic.c

836

sc->cfg.bus_speed = reg_read(sc, IG4_REG_CTL) & IG4_CTL_SPEED_MASK;

sys/dev/ichiic/ig4_iic.c

838

reg_read(sc, IG4_REG_SS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;

sys/dev/ichiic/ig4_iic.c

840

reg_read(sc, IG4_REG_SS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;

sys/dev/ichiic/ig4_iic.c

842

reg_read(sc, IG4_REG_FS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;

sys/dev/ichiic/ig4_iic.c

844

reg_read(sc, IG4_REG_FS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;

sys/dev/ichiic/ig4_iic.c

846

reg_read(sc, IG4_REG_SDA_HOLD) & IG4_SDA_TX_HOLD_MASK;

sys/dev/ichiic/ig4_iic.c

853

v = reg_read(sc, IG4_REG_COMP_PARAM1);

sys/dev/ichiic/ig4_iic.c

927

v = reg_read(sc, IG4_REG_DEVIDLE_CTRL);

sys/dev/ichiic/ig4_iic.c

949

if (reg_read(sc, IG4_REG_COMP_TYPE) == IG4_COMP_TYPE)

sys/dev/ichiic/ig4_iic.c

957

reg_read(sc, IG4_REG_COMP_TYPE));

sys/dev/ichiic/ig4_iic.c

962

v = reg_read(sc, IG4_REG_COMP_TYPE);

sys/dev/ichiic/ig4_iic.c

965

v = reg_read(sc, IG4_REG_COMP_PARAM1);

sys/dev/ichiic/ig4_iic.c

966

v = reg_read(sc, IG4_REG_GENERAL);

sys/dev/ichiic/ig4_iic.c

975

v = reg_read(sc, IG4_REG_GENERAL);

sys/dev/ichiic/ig4_iic.c

980

v = reg_read(sc, IG4_REG_SW_LTR_VALUE);

sys/dev/ichiic/ig4_iic.c

981

v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);

sys/dev/ichiic/ig4_iic.c

983

v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE);

sys/dev/ichiic/ig4_iic.c

984

v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE);

sys/dev/ichiic/ig4_iic.c

988

v = reg_read(sc, IG4_REG_COMP_VER);

sys/dev/ichiic/ig4_iic.c

998

reg_read(sc, IG4_REG_CLR_INTR);

sys/riscv/include/vmm_instruction_emul.h

83

reg_read_t reg_read, reg_write_t reg_write, void *arg);