sys/arm64/vmm/io/vgic_v3.c

1311

vgic_register_read(struct hypctx *hypctx, struct vgic_register *reg_list,

sys/arm64/vmm/io/vgic_v3.c

1317

if (reg_list[i].start <= reg && reg_list[i].end >= reg + size) {

sys/arm64/vmm/io/vgic_v3.c

1318

offset = reg & (reg_list[i].size - 1);

sys/arm64/vmm/io/vgic_v3.c

1320

if ((reg_list[i].flags & size) != 0) {

sys/arm64/vmm/io/vgic_v3.c

1321

reg_list[i].read(hypctx, reg, rval, NULL);

sys/arm64/vmm/io/vgic_v3.c

1346

vgic_register_write(struct hypctx *hypctx, struct vgic_register *reg_list,

sys/arm64/vmm/io/vgic_v3.c

1352

if (reg_list[i].start <= reg && reg_list[i].end >= reg + size) {

sys/arm64/vmm/io/vgic_v3.c

1353

offset = reg & (reg_list[i].size - 1);

sys/arm64/vmm/io/vgic_v3.c

1355

if ((reg_list[i].flags & size) != 0) {

sys/arm64/vmm/io/vgic_v3.c

1356

reg_list[i].write(hypctx, reg, offset,

sys/dev/iicbus/pmic/rockchip/rk8xx.h

108

TAILQ_HEAD(, reg_list) regs;

sys/dev/iicbus/pmic/rockchip/rk8xx.h

68

TAILQ_ENTRY(reg_list) next;

sys/dev/iicbus/pmic/rockchip/rk8xx_regulators.c

318

struct reg_list *regp;

sys/dev/iicbus/pmic/rockchip/rk8xx_regulators.c

355

struct reg_list *regp;

sys/dev/liquidio/base/cn23xx_pf_device.c

865

oct->reg_list.pci_win_wr_addr = LIO_CN23XX_SLI_WIN_WR_ADDR64;

sys/dev/liquidio/base/cn23xx_pf_device.c

867

oct->reg_list.pci_win_rd_addr_hi = LIO_CN23XX_SLI_WIN_RD_ADDR_HI;

sys/dev/liquidio/base/cn23xx_pf_device.c

868

oct->reg_list.pci_win_rd_addr_lo = LIO_CN23XX_SLI_WIN_RD_ADDR64;

sys/dev/liquidio/base/cn23xx_pf_device.c

869

oct->reg_list.pci_win_rd_addr = LIO_CN23XX_SLI_WIN_RD_ADDR64;

sys/dev/liquidio/base/cn23xx_pf_device.c

871

oct->reg_list.pci_win_wr_data_hi = LIO_CN23XX_SLI_WIN_WR_DATA_HI;

sys/dev/liquidio/base/cn23xx_pf_device.c

872

oct->reg_list.pci_win_wr_data_lo = LIO_CN23XX_SLI_WIN_WR_DATA_LO;

sys/dev/liquidio/base/cn23xx_pf_device.c

873

oct->reg_list.pci_win_wr_data = LIO_CN23XX_SLI_WIN_WR_DATA64;

sys/dev/liquidio/base/cn23xx_pf_device.c

875

oct->reg_list.pci_win_rd_data = LIO_CN23XX_SLI_WIN_RD_DATA64;

sys/dev/liquidio/base/lio_device.c

918

lio_write_csr32(oct, oct->reg_list.pci_win_rd_addr_hi, addrhi);

sys/dev/liquidio/base/lio_device.c

921

(void)lio_read_csr32(oct, oct->reg_list.pci_win_rd_addr_hi);

sys/dev/liquidio/base/lio_device.c

923

lio_write_csr32(oct, oct->reg_list.pci_win_rd_addr_lo,

sys/dev/liquidio/base/lio_device.c

925

(void)lio_read_csr32(oct, oct->reg_list.pci_win_rd_addr_lo);

sys/dev/liquidio/base/lio_device.c

927

val64 = lio_read_csr64(oct, oct->reg_list.pci_win_rd_data);

sys/dev/liquidio/base/lio_device.c

940

lio_write_csr64(oct, oct->reg_list.pci_win_wr_addr, addr);

sys/dev/liquidio/base/lio_device.c

943

lio_write_csr32(oct, oct->reg_list.pci_win_wr_data_hi, val >> 32);

sys/dev/liquidio/base/lio_device.c

945

(void)lio_read_csr32(oct, oct->reg_list.pci_win_wr_data_hi);

sys/dev/liquidio/base/lio_device.c

947

lio_write_csr32(oct, oct->reg_list.pci_win_wr_data_lo,

sys/dev/liquidio/base/lio_device.h

413

struct lio_reg_list reg_list;