sys/amd64/acpica/acpi_wakeup.c

224

WAKECODE_FIXUP(wakeup_efer, uint64_t, rdmsr(MSR_EFER) &

sys/amd64/amd64/initcpu.c

104

wrmsr(MSR_DE_CFG, rdmsr(MSR_DE_CFG) |

sys/amd64/amd64/initcpu.c

116

msr = rdmsr(MSR_NB_CFG1);

sys/amd64/amd64/initcpu.c

130

msr = rdmsr(0xc001102a);

sys/amd64/amd64/initcpu.c

144

msr = rdmsr(MSR_LS_CFG);

sys/amd64/amd64/initcpu.c

154

msr = rdmsr(MSR_DE_CFG);

sys/amd64/amd64/initcpu.c

159

msr = rdmsr(MSR_LS_CFG);

sys/amd64/amd64/initcpu.c

164

msr = rdmsr(0xc0011028);

sys/amd64/amd64/initcpu.c

169

msr = rdmsr(MSR_LS_CFG);

sys/amd64/amd64/initcpu.c

224

wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);

sys/amd64/amd64/initcpu.c

237

wrmsr(0x1107, rdmsr(0x1107) | (1 << 28));

sys/amd64/amd64/initcpu.c

337

msr = rdmsr(MSR_EFER) | EFER_NXE;

sys/amd64/amd64/initcpu.c

342

msr = rdmsr(MSR_EFER) | EFER_TCE;

sys/amd64/amd64/machdep.c

1194

msr = rdmsr(MSR_EFER) | EFER_SCE;

sys/amd64/amd64/machdep.c

1841

pcb->pcb_gsbase = rdmsr(MSR_KGSBASE);

sys/amd64/amd64/machdep.c

575

db_printf("EFER\t0x%016lx\n", rdmsr(MSR_EFER));

sys/amd64/amd64/machdep.c

578

rdmsr(MSR_IA32_FEATURE_CONTROL));

sys/amd64/amd64/machdep.c

579

db_printf("DEBUG_CTL\t0x%016lx\n", rdmsr(MSR_DEBUGCTLMSR));

sys/amd64/amd64/machdep.c

580

db_printf("PAT\t0x%016lx\n", rdmsr(MSR_PAT));

sys/amd64/amd64/machdep.c

581

db_printf("GSBASE\t0x%016lx\n", rdmsr(MSR_GSBASE));

sys/amd64/amd64/trap.c

1084

rdmsr(MSR_FSBASE), rdmsr(MSR_GSBASE), rdmsr(MSR_KGSBASE));

sys/amd64/amd64/trap.c

201

gsbase = rdmsr(MSR_KGSBASE);

sys/amd64/pt/pt.c

195

reg = rdmsr(MSR_IA32_RTIT_OUTPUT_MASK_PTRS);

sys/amd64/pt/pt.c

232

xss = rdmsr(MSR_IA32_XSS);

sys/amd64/pt/pt.c

236

KASSERT((rdmsr(MSR_IA32_RTIT_CTL) & RTIT_CTL_TRACEEN) != 0,

sys/amd64/pt/pt.c

240

KASSERT((rdmsr(MSR_IA32_RTIT_CTL) & RTIT_CTL_TRACEEN) == 0,

sys/amd64/pt/pt.c

774

reg = rdmsr(MSR_IA_GLOBAL_STATUS_RESET);

sys/amd64/pt/pt.c

796

reg = rdmsr(MSR_IA_GLOBAL_STATUS);

sys/amd64/vmm/amd/svm.c

157

efer = rdmsr(MSR_EFER);

sys/amd64/vmm/amd/svm.c

2073

gctx->host_debugctl = rdmsr(MSR_DEBUGCTLMSR);

sys/amd64/vmm/amd/svm.c

217

efer = rdmsr(MSR_EFER);

sys/amd64/vmm/amd/svm.c

238

msr = rdmsr(MSR_VM_CR);

sys/amd64/vmm/amd/svm_msr.c

66

host_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR);

sys/amd64/vmm/amd/svm_msr.c

67

host_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR);

sys/amd64/vmm/amd/svm_msr.c

68

host_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR);

sys/amd64/vmm/amd/svm_msr.c

69

host_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK);

sys/amd64/vmm/intel/ept.c

81

cap = rdmsr(MSR_VMX_EPT_VPID_CAP);

sys/amd64/vmm/intel/vmx.c

243

SDT_PROBE_DEFINE4(vmm, vmx, exit, rdmsr,

sys/amd64/vmm/intel/vmx.c

2540

SDT_PROBE4(vmm, vmx, exit, rdmsr, vmx, vcpuid, vmexit, ecx);

sys/amd64/vmm/intel/vmx.c

2952

vmxctx->host_debugctl = rdmsr(MSR_DEBUGCTLMSR);

sys/amd64/vmm/intel/vmx.c

637

feature_control = rdmsr(MSR_IA32_FEATURE_CONTROL);

sys/amd64/vmm/intel/vmx.c

687

feature_control = rdmsr(MSR_IA32_FEATURE_CONTROL);

sys/amd64/vmm/intel/vmx.c

698

basic = rdmsr(MSR_VMX_BASIC);

sys/amd64/vmm/intel/vmx.c

962

fixed0 = rdmsr(MSR_VMX_CR0_FIXED0);

sys/amd64/vmm/intel/vmx.c

963

fixed1 = rdmsr(MSR_VMX_CR0_FIXED1);

sys/amd64/vmm/intel/vmx.c

979

fixed0 = rdmsr(MSR_VMX_CR4_FIXED0);

sys/amd64/vmm/intel/vmx.c

980

fixed1 = rdmsr(MSR_VMX_CR4_FIXED1);

sys/amd64/vmm/intel/vmx_msr.c

252

host_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR);

sys/amd64/vmm/intel/vmx_msr.c

253

host_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR);

sys/amd64/vmm/intel/vmx_msr.c

254

host_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR);

sys/amd64/vmm/intel/vmx_msr.c

255

host_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK);

sys/amd64/vmm/intel/vmx_msr.c

260

misc_enable = rdmsr(MSR_IA32_MISC_ENABLE);

sys/amd64/vmm/intel/vmx_msr.c

369

vcpu->guest_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR);

sys/amd64/vmm/intel/vmx_msr.c

370

vcpu->guest_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR);

sys/amd64/vmm/intel/vmx_msr.c

371

vcpu->guest_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR);

sys/amd64/vmm/intel/vmx_msr.c

372

vcpu->guest_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK);

sys/amd64/vmm/intel/vmx_msr.c

373

vcpu->guest_msrs[IDX_MSR_KGSBASE] = rdmsr(MSR_KGSBASE);

sys/amd64/vmm/intel/vmx_msr.c

62

return (rdmsr(MSR_VMX_BASIC) & 0xffffffff);

sys/amd64/vmm/intel/vmx_msr.c

88

true_ctls_avail = (rdmsr(MSR_VMX_BASIC) & (1UL << 55)) != 0;

sys/amd64/vmm/intel/vmx_msr.c

90

val = rdmsr(ctl_reg);

sys/amd64/vmm/intel/vmx_msr.c

92

trueval = rdmsr(true_ctl_reg); /* step c */

sys/amd64/vmm/vmm_host.c

47

vmm_host_efer = rdmsr(MSR_EFER);

sys/amd64/vmm/vmm_host.c

48

vmm_host_pat = rdmsr(MSR_PAT);

sys/compat/linuxkpi/common/include/asm/msr.h

32

#define rdmsrl(msr, val) ((val) = rdmsr(msr))

sys/dev/agp/agp_nvidia.c

389

base = rdmsr(IORR_BASE0 + 2 * iorr_addr);

sys/dev/agp/agp_nvidia.c

390

mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);

sys/dev/agp/agp_nvidia.c

410

sys = rdmsr(SYSCFG);

sys/dev/coretemp/coretemp.c

190

msr = rdmsr(MSR_BIOS_SIGN);

sys/dev/coretemp/coretemp.c

213

msr = rdmsr(MSR_IA32_EXT_CONFIG);

sys/dev/glxiic/glxiic.c

347

irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH);

sys/dev/glxiic/glxiic.c

996

irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH);

sys/dev/glxsb/glxsb.c

261

msr = rdmsr(SB_GLD_MSR_CAP);

sys/dev/glxsb/glxsb.c

288

msr = rdmsr(SB_GLD_MSR_CTRL);

sys/dev/hwpmc/hwpmc_amd.c

265

tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */

sys/dev/hwpmc/hwpmc_amd.c

581

if (rdmsr(pd->pm_perfctr) & (1 << (pd->pm_descr.pd_width - 1)))

sys/dev/hwpmc/hwpmc_amd.c

655

config = rdmsr(evsel);

sys/dev/hwpmc/hwpmc_amd.h

177

#define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0)

sys/dev/hwpmc/hwpmc_core.c

1078

intrstatus = rdmsr(IA_GLOBAL_STATUS);

sys/dev/hwpmc/hwpmc_core.c

1171

cpu, (uintmax_t) rdmsr(IAF_CTRL),

sys/dev/hwpmc/hwpmc_core.c

1172

(uintmax_t) rdmsr(IA_GLOBAL_CTRL),

sys/dev/hwpmc/hwpmc_core.c

1173

(uintmax_t) rdmsr(IA_GLOBAL_STATUS));

sys/dev/hwpmc/hwpmc_core.c

1203

if (rdmsr(IA32_PERF_CAPABILITIES) & PERFCAP_FW_WRITE) {

sys/dev/hwpmc/hwpmc_core.c

153

wrmsr(MSR_DEBUGCTLMSR, rdmsr(MSR_DEBUGCTLMSR) | 0x1000);

sys/dev/hwpmc/hwpmc_core.c

436

cc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),

sys/dev/hwpmc/hwpmc_core.c

437

cc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));

sys/dev/hwpmc/hwpmc_core.c

462

cc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),

sys/dev/hwpmc/hwpmc_core.c

463

cc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));

sys/dev/hwpmc/hwpmc_core.c

493

(uintmax_t) rdmsr(IAF_CTRL),

sys/dev/hwpmc/hwpmc_ibs.c

281

*v = IBS_FETCH_CTL_TO_COUNT(rdmsr(IBS_FETCH_CTL));

sys/dev/hwpmc/hwpmc_ibs.c

284

*v = IBS_OP_CTL_TO_COUNT(rdmsr(IBS_OP_CTL));

sys/dev/hwpmc/hwpmc_ibs.c

309

m = rdmsr(IBS_FETCH_CTL) & ~IBS_FETCH_CTL_CURCNTMASK;

sys/dev/hwpmc/hwpmc_ibs.c

316

m = rdmsr(IBS_OP_CTL) & ~IBS_OP_CTL_CURCNTMASK;

sys/dev/hwpmc/hwpmc_ibs.c

625

mpd.pl_mpdata[PMC_MPIDX_FETCH_EXTCTL] = rdmsr(IBS_FETCH_EXTCTL);

sys/dev/hwpmc/hwpmc_ibs.c

627

mpd.pl_mpdata[PMC_MPIDX_FETCH_LINADDR] = rdmsr(IBS_FETCH_LINADDR);

sys/dev/hwpmc/hwpmc_ibs.c

630

rdmsr(IBS_FETCH_PHYSADDR);

sys/dev/hwpmc/hwpmc_ibs.c

633

mpd.pl_mpdata[PMC_MPIDX_FETCH_CTL2] = rdmsr(IBS_FETCH_CTL2);

sys/dev/hwpmc/hwpmc_ibs.c

657

mpd.pl_mpdata[PMC_MPIDX_OP_RIP] = rdmsr(IBS_OP_RIP);

sys/dev/hwpmc/hwpmc_ibs.c

658

mpd.pl_mpdata[PMC_MPIDX_OP_DATA] = rdmsr(IBS_OP_DATA);

sys/dev/hwpmc/hwpmc_ibs.c

659

mpd.pl_mpdata[PMC_MPIDX_OP_DATA2] = rdmsr(IBS_OP_DATA2);

sys/dev/hwpmc/hwpmc_ibs.c

660

mpd.pl_mpdata[PMC_MPIDX_OP_DATA3] = rdmsr(IBS_OP_DATA3);

sys/dev/hwpmc/hwpmc_ibs.c

661

mpd.pl_mpdata[PMC_MPIDX_OP_DC_LINADDR] = rdmsr(IBS_OP_DC_LINADDR);

sys/dev/hwpmc/hwpmc_ibs.c

662

mpd.pl_mpdata[PMC_MPIDX_OP_DC_PHYSADDR] = rdmsr(IBS_OP_DC_PHYSADDR);

sys/dev/hwpmc/hwpmc_ibs.c

664

mpd.pl_mpdata[PMC_MPIDX_OP_TGT_RIP] = rdmsr(IBS_OP_TGT_RIP);

sys/dev/hwpmc/hwpmc_ibs.c

667

mpd.pl_mpdata[PMC_MPIDX_OP_DATA4] = rdmsr(IBS_OP_DATA4);

sys/dev/hwpmc/hwpmc_ibs.c

670

mpd.pl_mpdata[PMC_MPIDX_OP_CTL2] = rdmsr(IBS_OP_CTL2);

sys/dev/hwpmc/hwpmc_ibs.c

705

config = rdmsr(IBS_FETCH_CTL);

sys/dev/hwpmc/hwpmc_ibs.c

714

config = rdmsr(IBS_OP_CTL);

sys/dev/hwpmc/hwpmc_rapl.c

535

unit_val = rdmsr(unit_msr);

sys/dev/hwpmc/hwpmc_uncore.c

272

tmp = rdmsr(UCF_CTR0 + ri);

sys/dev/hwpmc/hwpmc_uncore.c

321

ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL),

sys/dev/hwpmc/hwpmc_uncore.c

322

ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL));

sys/dev/hwpmc/hwpmc_uncore.c

352

ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL),

sys/dev/hwpmc/hwpmc_uncore.c

353

ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL));

sys/dev/hwpmc/hwpmc_uncore.c

378

cpu, ri, v, (uintmax_t) rdmsr(UCF_CTRL));

sys/dev/hwpmc/hwpmc_uncore.c

581

tmp = rdmsr(UCP_PMC0 + ri);

sys/dev/hyperv/vmbus/amd64/hyperv_machdep.c

165

return (rdmsr(MSR_HV_TIME_REF_COUNT)); \

sys/dev/hyperv/vmbus/amd64/hyperv_machdep.c

217

orig = rdmsr(MSR_HV_REFERENCE_TSC);

sys/dev/hyperv/vmbus/vmbus_et.c

165

val = rdmsr(MSR_HV_STIMER0_CONFIG);

sys/dev/hyperv/vmbus/x86/hyperv_machdep.h

36

#define RDMSR(msr) rdmsr(msr)

sys/dev/hyperv/vmbus/x86/hyperv_x86.c

117

hc_orig = rdmsr(MSR_HV_HYPERCALL);

sys/dev/hyperv/vmbus/x86/hyperv_x86.c

131

hc = rdmsr(MSR_HV_HYPERCALL);

sys/dev/hyperv/vmbus/x86/hyperv_x86.c

146

hc = rdmsr(MSR_HV_HYPERCALL);

sys/dev/hyperv/vmbus/x86/hyperv_x86.c

84

return rdmsr(MSR_HV_TIME_REF_COUNT);

sys/dev/hyperv/vmbus/x86/hyperv_x86.c

91

return (rdmsr(MSR_HV_TIME_REF_COUNT));

sys/i386/acpica/acpi_wakeup.c

225

WAKECODE_FIXUP(wakeup_efer, uint64_t, rdmsr(MSR_EFER));

sys/i386/i386/geode.c

128

a = rdmsr(0x5140000c);

sys/i386/i386/geode.c

214

a = rdmsr(0x5140000d);

sys/i386/i386/geode.c

227

m = rdmsr(0x51400029);

sys/i386/i386/geode.c

350

printf("MFGPT bar: %jx\n", rdmsr(0x5140000d));

sys/i386/i386/initcpu.c

401

fcr = rdmsr(0x0107);

sys/i386/i386/initcpu.c

497

apicbase = rdmsr(MSR_APICBASE);

sys/i386/i386/initcpu.c

514

apicbase = rdmsr(MSR_APICBASE);

sys/i386/i386/initcpu.c

537

bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);

sys/i386/i386/initcpu.c

594

wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);

sys/i386/i386/initcpu.c

609

wrmsr(0x1107, rdmsr(0x1107) | fcr);

sys/i386/i386/initcpu.c

621

wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL);

sys/i386/i386/initcpu.c

691

wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);

sys/i386/i386/initcpu.c

735

wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);

sys/i386/i386/initcpu.c

766

msr = rdmsr(MSR_EFER) | EFER_NXE;

sys/i386/i386/initcpu.c

823

msr = rdmsr(0x83); /* HWCR */

sys/i386/i386/initcpu.c

845

msr=rdmsr(0x83);

sys/i386/i386/initcpu.c

884

whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);

sys/i386/i386/initcpu.c

934

whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);

sys/i386/i386/k6_mem.c

112

reg = rdmsr(UWCCR);

sys/i386/i386/k6_mem.c

165

reg = rdmsr(UWCCR);

sys/i386/i386/longrun.c

142

msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);

sys/i386/i386/longrun.c

150

msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);

sys/i386/i386/longrun.c

94

msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);

sys/i386/i386/longrun.c

97

flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;

sys/i386/i386/machdep.c

689

db_printf("EFER\t0x%016llx\n", rdmsr(MSR_EFER));

sys/i386/i386/machdep.c

692

rdmsr(MSR_IA32_FEATURE_CONTROL));

sys/i386/i386/machdep.c

696

db_printf("DEBUG_CTL\t0x%016llx\n", rdmsr(MSR_DEBUGCTLMSR));

sys/i386/i386/machdep.c

698

db_printf("PAT\t0x%016llx\n", rdmsr(MSR_PAT));

sys/x86/cpufreq/est.c

1041

msr = rdmsr(MSR_PERF_STATUS);

sys/x86/cpufreq/est.c

1246

*id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff;

sys/x86/cpufreq/est.c

1257

msr = rdmsr(MSR_PERF_CTL);

sys/x86/cpufreq/est.c

973

msr = rdmsr(MSR_MISC_ENABLE);

sys/x86/cpufreq/est.c

980

msr = rdmsr(MSR_MISC_ENABLE);

sys/x86/cpufreq/p4tcc.c

282

msr = rdmsr(MSR_THERM_CONTROL);

sys/x86/cpufreq/p4tcc.c

324

msr = rdmsr(MSR_THERM_CONTROL);

sys/x86/cpufreq/powernow.c

277

status = rdmsr(MSR_AMDK7_FIDVID_STATUS);

sys/x86/cpufreq/powernow.c

285

ctl = rdmsr(MSR_AMDK7_FIDVID_CTL) & PN7_CTR_FIDCHRATIO;

sys/x86/cpufreq/powernow.c

316

*status = rdmsr(MSR_AMDK7_FIDVID_STATUS);

sys/x86/cpufreq/powernow.c

486

status = rdmsr(MSR_AMDK7_FIDVID_STATUS);

sys/x86/cpufreq/powernow.c

652

status = rdmsr(MSR_AMDK7_FIDVID_STATUS);

sys/x86/cpufreq/powernow.c

822

status = rdmsr(MSR_AMDK7_FIDVID_STATUS);

sys/x86/cpufreq/powernow.c

891

status = rdmsr(MSR_AMDK7_FIDVID_STATUS);

sys/x86/x86/cpu_machdep.c

183

v = rdmsr(a->msr);

sys/x86/x86/cpu_machdep.c

190

v = rdmsr(a->msr);

sys/x86/x86/cpu_machdep.c

200

v = rdmsr(a->msr);

sys/x86/x86/cpu_machdep.c

396

v = rdmsr(MSR_IA32_SPEC_CTRL);

sys/x86/x86/cpu_machdep.c

456

mcnt_start = rdmsr(MSR_MPERF);

sys/x86/x86/cpu_machdep.c

457

acnt_start = rdmsr(MSR_APERF);

sys/x86/x86/cpu_machdep.c

460

mcnt_end = rdmsr(MSR_MPERF);

sys/x86/x86/cpu_machdep.c

461

acnt_end = rdmsr(MSR_APERF);

sys/x86/x86/cpu_machdep.c

794

msr = rdmsr(MSR_AMDK8_IPM);

sys/x86/x86/identcpu.c

1299

rdmsr(0x1002); /* Cyrix CPU generates fault. */

sys/x86/x86/identcpu.c

1536

msr = rdmsr(MSR_IA32_MISC_ENABLE);

sys/x86/x86/identcpu.c

1553

msr = rdmsr(MSR_EXTFEATURES);

sys/x86/x86/identcpu.c

1614

cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);

sys/x86/x86/identcpu.c

1922

amd_whcr = rdmsr(0xc0000082);

sys/x86/x86/identcpu.c

1934

amd_whcr = rdmsr(0xc0000082);

sys/x86/x86/identcpu.c

2360

msr = rdmsr(MSR_VM_CR);

sys/x86/x86/identcpu.c

2487

val = rdmsr(true_msr);

sys/x86/x86/identcpu.c

2489

val = rdmsr(msr);

sys/x86/x86/identcpu.c

2503

msr = rdmsr(MSR_IA32_FEATURE_CONTROL);

sys/x86/x86/identcpu.c

2506

basic = rdmsr(MSR_VMX_BASIC);

sys/x86/x86/identcpu.c

2647

msr = rdmsr(MSR_VMX_EPT_VPID_CAP);

sys/x86/x86/local_apic.c

457

apic_base = rdmsr(MSR_APICBASE);

sys/x86/x86/local_apic.c

467

apic_base = rdmsr(MSR_APICBASE);

sys/x86/x86/mca.c

1013

ctl = rdmsr(MSR_MC_CTL2(bank));

sys/x86/x86/mca.c

1038

misc = rdmsr(mca_msr_ops.misc(bank));

sys/x86/x86/mca.c

1071

mcg_cap = rdmsr(MSR_MCG_CAP);

sys/x86/x86/mca.c

1402

ctl = rdmsr(MSR_MC_CTL2(i));

sys/x86/x86/mca.c

1411

ctl = rdmsr(MSR_MC_CTL2(i));

sys/x86/x86/mca.c

1422

ctl = rdmsr(MSR_MC_CTL2(i));

sys/x86/x86/mca.c

1456

ctl = rdmsr(MSR_MC_CTL2(i));

sys/x86/x86/mca.c

1472

misc = rdmsr(mca_msr_ops.misc(bank));

sys/x86/x86/mca.c

1505

misc = rdmsr(mca_msr_ops.misc(i));

sys/x86/x86/mca.c

1588

mcg_cap = rdmsr(MSR_MCG_CAP);

sys/x86/x86/mca.c

1604

mask = rdmsr(MSR_MC0_CTL_MASK);

sys/x86/x86/mca.c

1618

(rdmsr(MSR_IA32_FEATURE_CONTROL) &

sys/x86/x86/mca.c

1620

wrmsr(MSR_MCG_EXT_CTL, rdmsr(MSR_MCG_EXT_CTL) | 1);

sys/x86/x86/mca.c

1725

(uintmax_t)rdmsr(MSR_P5_MC_TYPE),

sys/x86/x86/mca.c

1726

(uintmax_t)rdmsr(MSR_P5_MC_ADDR));

sys/x86/x86/mca.c

1731

mcg_status = rdmsr(MSR_MCG_STATUS);

sys/x86/x86/mca.c

817

status = rdmsr(mca_msr_ops.status(bank));

sys/x86/x86/mca.c

848

rec->mr_addr = rdmsr(mca_msr_ops.addr(bank));

sys/x86/x86/mca.c

851

rec->mr_misc = rdmsr(mca_msr_ops.misc(bank));

sys/x86/x86/mca.c

854

rec->mr_mcg_cap = rdmsr(MSR_MCG_CAP);

sys/x86/x86/mca.c

855

rec->mr_mcg_status = rdmsr(MSR_MCG_STATUS);

sys/x86/x86/mp_x86.c

347

v = rdmsr(0xc001100c);

sys/x86/x86/tsc.c

354

(rdmsr(0x1203) & 0x100000000ULL) == 0)

sys/x86/x86/tsc.c

449

mperf = rdmsr(MSR_MPERF);

sys/x86/x86/tsc.c

450

aperf = rdmsr(MSR_APERF);

sys/x86/x86/tsc.c

452

if (rdmsr(MSR_MPERF) != mperf && rdmsr(MSR_APERF) != aperf)

sys/x86/x86/ucode.c

124

orev = rdmsr(MSR_BIOS_SIGN) >> 32;

sys/x86/x86/ucode.c

158

nrev = rdmsr(MSR_BIOS_SIGN) >> 32;

sys/x86/x86/ucode.c

211

platformid = rdmsr(MSR_IA32_PLATFORM_ID);

sys/x86/x86/ucode.c

277

orev = rdmsr(MSR_BIOS_SIGN);

sys/x86/x86/ucode.c

305

nrev = rdmsr(MSR_BIOS_SIGN);

sys/x86/x86/ucode.c

324

revision = rdmsr(MSR_BIOS_SIGN);

sys/x86/x86/x86_mem.c

210

msrv = rdmsr(msr);

sys/x86/x86/x86_mem.c

222

msrv = rdmsr(msr);

sys/x86/x86/x86_mem.c

234

msrv = rdmsr(msr);

sys/x86/x86/x86_mem.c

249

msrv = rdmsr(msr);

sys/x86/x86/x86_mem.c

253

msrv = rdmsr(msr + 1);

sys/x86/x86/x86_mem.c

343

wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE);

sys/x86/x86/x86_mem.c

350

omsrv = rdmsr(msr);

sys/x86/x86/x86_mem.c

362

omsrv = rdmsr(msr);

sys/x86/x86/x86_mem.c

374

omsrv = rdmsr(msr);

sys/x86/x86/x86_mem.c

389

omsrv = rdmsr(msr);

sys/x86/x86/x86_mem.c

413

wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);

sys/x86/x86/x86_mem.c

620

mtrrcap = rdmsr(MSR_MTRRcap);

sys/x86/x86/x86_mem.c

621

mtrrdef = rdmsr(MSR_MTRRdefType);