rl_type
enum ice_rl_type rl_type, u16 bw_alloc)
if (rl_type == ICE_MIN_BW) {
} else if (rl_type == ICE_MAX_BW) {
enum ice_rl_type rl_type, u16 bw_alloc)
switch (rl_type) {
enum ice_rl_type rl_type, u32 bw)
switch (rl_type) {
enum ice_rl_type rl_type, u16 bw_alloc)
switch (rl_type) {
enum ice_rl_type rl_type, u32 bw)
switch (rl_type) {
enum ice_rl_type rl_type, u32 bw)
tc, rl_type, bw);
status = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, bw);
enum ice_rl_type rl_type)
tc, rl_type,
status = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type,
enum ice_rl_type rl_type, u32 bw)
tc, rl_type, bw);
status = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, bw);
enum ice_rl_type rl_type)
tc, rl_type,
status = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type,
enum ice_rl_type rl_type, u8 *bw_alloc)
status = ice_sched_cfg_node_bw_alloc(pi->hw, vsi_node, rl_type,
rl_type, bw_alloc[tc]);
enum ice_rl_type rl_type, u8 *bw_alloc)
status = ice_sched_cfg_node_bw_alloc(hw, agg_node, rl_type,
status = ice_sched_save_agg_bw_alloc(pi, agg_id, tc, rl_type,
ice_sched_add_rl_profile(struct ice_hw *hw, enum ice_rl_type rl_type,
switch (rl_type) {
enum ice_rl_type rl_type, u16 rl_prof_id)
switch (rl_type) {
enum ice_rl_type rl_type)
switch (rl_type) {
ice_sched_get_rl_prof_layer(struct ice_port_info *pi, enum ice_rl_type rl_type,
switch (rl_type) {
enum ice_rl_type rl_type, u8 layer_num)
switch (rl_type) {
old_id = ice_sched_get_node_rl_prof_id(node, rl_type);
status = ice_sched_cfg_node_bw_lmt(hw, node, rl_type, rl_prof_id);
enum ice_rl_type rl_type, u32 bw, u8 layer_num)
rl_prof_info = ice_sched_add_rl_profile(hw, rl_type, bw, layer_num);
old_id = ice_sched_get_node_rl_prof_id(node, rl_type);
status = ice_sched_cfg_node_bw_lmt(hw, node, rl_type, rl_prof_id);
if ((old_id == ICE_SCHED_DFLT_RL_PROF_ID && rl_type != ICE_SHARED_BW) ||
enum ice_rl_type rl_type, u32 bw)
layer_num = ice_sched_get_rl_prof_layer(pi, rl_type,
return ice_sched_set_node_bw_dflt(pi, node, rl_type, layer_num);
return ice_sched_set_node_bw(pi, node, rl_type, bw, layer_num);
enum ice_rl_type rl_type)
return ice_sched_set_node_bw_lmt(pi, node, rl_type,
ice_sched_save_q_bw(struct ice_q_ctx *q_ctx, enum ice_rl_type rl_type, u32 bw)
switch (rl_type) {
u16 q_handle, enum ice_rl_type rl_type, u32 bw)
if (rl_type == ICE_SHARED_BW) {
sel_layer = ice_sched_get_rl_prof_layer(pi, rl_type,
status = ice_sched_set_node_bw_dflt_lmt(pi, node, rl_type);
status = ice_sched_set_node_bw_lmt(pi, node, rl_type, bw);
status = ice_sched_save_q_bw(q_ctx, rl_type, bw);
u16 q_handle, enum ice_rl_type rl_type, u32 bw)
return ice_sched_set_q_bw_lmt(pi, vsi_handle, tc, q_handle, rl_type,
u16 q_handle, enum ice_rl_type rl_type)
return ice_sched_set_q_bw_lmt(pi, vsi_handle, tc, q_handle, rl_type,
enum ice_rl_type rl_type, u32 bw)
switch (rl_type) {
enum ice_rl_type rl_type, u32 bw)
status = ice_sched_set_node_bw_dflt_lmt(pi, tc_node, rl_type);
status = ice_sched_set_node_bw_lmt(pi, tc_node, rl_type, bw);
status = ice_sched_save_tc_node_bw(pi, tc, rl_type, bw);
enum ice_rl_type rl_type, u32 bw)
return ice_sched_set_tc_node_bw_lmt(pi, tc, rl_type, bw);
enum ice_rl_type rl_type)
return ice_sched_set_tc_node_bw_lmt(pi, tc, rl_type, ICE_SCHED_DFLT_BW);
enum ice_rl_type rl_type, u16 bw_alloc)
switch (rl_type) {
enum ice_rl_type rl_type, u8 bw_alloc)
status = ice_sched_cfg_node_bw_alloc(pi->hw, tc_node, rl_type,
status = ice_sched_save_tc_node_bw_alloc(pi, tc, rl_type, bw_alloc);
enum ice_rl_type rl_type, u8 bw_alloc)
return ice_sched_set_tc_node_bw_alloc(pi, tc, rl_type, bw_alloc);
enum ice_rl_type rl_type, u32 bw)
if (rl_type == ICE_UNKNOWN_BW)
status = ice_sched_set_node_bw_dflt_lmt(pi, node, rl_type);
status = ice_sched_set_node_bw_lmt(pi, node, rl_type, bw);
enum ice_rl_type rl_type = ICE_SHARED_BW;
layer_num = ice_sched_get_rl_prof_layer(pi, rl_type,
enum ice_rl_type rl_type, u32 bw)
status = ice_sched_set_node_bw_dflt_lmt(pi, srl_node, rl_type);
status = ice_sched_set_node_bw_lmt(pi, srl_node, rl_type, bw);
status = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, bw);
enum ice_rl_type rl_type = ICE_SHARED_BW;
layer_num = ice_sched_get_rl_prof_layer(pi, rl_type,
enum ice_rl_type rl_type, u32 bw)
status = ice_sched_set_node_bw_dflt_lmt(pi, srl_node, rl_type);
status = ice_sched_set_node_bw_lmt(pi, srl_node, rl_type, bw);
status = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, bw);
enum ice_rl_type rl_type = ICE_SHARED_BW;
layer_num = ice_sched_get_rl_prof_layer(pi, rl_type,
enum ice_rl_type rl_type, u32 bw);
enum ice_rl_type rl_type, u32 bw, u8 layer_num);
u16 q_handle, enum ice_rl_type rl_type, u32 bw);
u16 q_handle, enum ice_rl_type rl_type);
enum ice_rl_type rl_type, u32 bw);
enum ice_rl_type rl_type);
enum ice_rl_type rl_type, u32 bw);
enum ice_rl_type rl_type);
enum ice_rl_type rl_type, u32 bw);
enum ice_rl_type rl_type);
enum ice_rl_type rl_type, u8 *bw_alloc);
enum ice_rl_type rl_type, u8 *bw_alloc);
enum ice_rl_type rl_type, u32 bw);
enum ice_rl_type rl_type, u8 bw_alloc);
sc->rl_type = hw_rev->rl_type;
if (sc->rl_type == RL_8169) {
if (sc->rl_type == RL_8169)
static const struct rl_type re_devs[] = {
if (sc->rl_type == RL_8169)
if (sc->rl_type == RL_8169)
if (sc->rl_type == RL_8169) {
if (sc->rl_type == RL_8169)
if (sc->rl_type == RL_8169)
if (sc->rl_type == RL_8169)
if (sc->rl_type == RL_8169) {
if (sc->rl_type == RL_8169) {
if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
if (sc->rl_type == RL_8169) {
if (sc->rl_type == RL_8139CPLUS) {
if (sc->rl_type == RL_8169)
const struct rl_type *t;
static const struct rl_type rl_devs[] = {
if (sc->rl_type == RL_8139) {
if (sc->rl_type == RL_8139) {
const struct rl_type *t;
const struct rl_type *t;
sc->rl_type = 0;
sc->rl_type = t->rl_basetype;
if (sc->rl_type == 0) {
sc->rl_type = RL_8139;
if (sc->rl_type == RL_8139)
if (sc->rl_type == RL_8139 && pci_has_pm(sc->rl_dev)) {
int rl_type;
#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \
(x)->rl_type == RL_8169)
uint8_t rl_type;