reg_info
(struct reg_info *)malloc(sizeof(struct reg_info));
sizeof(struct reg_info));
struct reg_info *rinfo;
bxe_is_reg_in_chip(struct bxe_softc *sc, const struct reg_addr *reg_info)
return IS_E1_REG(reg_info->chips);
return IS_E1H_REG(reg_info->chips);
return IS_E2_REG(reg_info->chips);
return IS_E3A0_REG(reg_info->chips);
return IS_E3B0_REG(reg_info->chips);
struct struct_region_info *reg_info)
reg_info->exist = false;
reg_info->exist = true;
reg_info->start = payload.base - mem_region.base;
reg_info->start = 0;
reg_info->end = payload.limit - mem_region.base;
reg_info->end = mem_tot_len;
static struct reg_info adf_err_regs[] = {
dump_block_regs(const struct reg_info *reg_array, uint32_t *regs)
struct reg_info mc3_regs[] = {
struct reg_info mc4_regs[] = {
struct reg_info tpi_regs[] = {
struct reg_info tp_regs[] = {
struct reg_info rat_regs[] = {
struct reg_info cspi_regs[] = {
struct reg_info espi_regs[] = {
struct reg_info sge_regs[] = {
struct reg_info ulp_regs[] = {
struct reg_info pl_regs[] = {
struct reg_info mc5_regs[] = {
struct reg_info tp1_regs[] = {
struct reg_info ulp2_rx_regs[] = {
struct reg_info ulp2_tx_regs[] = {
struct reg_info pcix1_regs[] = {
struct reg_info pm1_rx_regs[] = {
struct reg_info pm1_tx_regs[] = {
struct reg_info mps0_regs[] = {
struct reg_info cpl_switch_regs[] = {
struct reg_info smb0_regs[] = {
struct reg_info i2cm0_regs[] = {
struct reg_info mi1_regs[] = {
struct reg_info jm1_regs[] = {
struct reg_info sf1_regs[] = {
struct reg_info pl3_regs[] = {
struct reg_info mc5a_regs[] = {
struct reg_info xgmac0_0_regs[] = {
struct reg_info pcie0_regs[] = {
struct reg_info xgmac0_1_regs[] = {
struct reg_info t3dbg_regs[] = {
struct reg_info mc7_pmrx_regs[] = {
struct reg_info mc7_pmtx_regs[] = {
struct reg_info sge3_regs[] = {
struct reg_info mc7_cm_regs[] = {
struct reg_info cim_regs[] = {
struct reg_info t3b_tp1_regs[] = {
struct reg_info t3b_ulp2_rx_regs[] = {
struct reg_info t3b_ulp2_tx_regs[] = {
struct reg_info t3b_pm1_rx_regs[] = {
struct reg_info t3b_pcix1_regs[] = {
struct reg_info t3b_pm1_tx_regs[] = {
struct reg_info t3b_mps0_regs[] = {
struct reg_info t3b_cpl_switch_regs[] = {
struct reg_info t3b_smb0_regs[] = {
struct reg_info t3b_i2cm0_regs[] = {
struct reg_info t3b_mi1_regs[] = {
struct reg_info t3b_jm1_regs[] = {
struct reg_info t3b_sf1_regs[] = {
struct reg_info t3b_pl3_regs[] = {
struct reg_info t3b_mc5a_regs[] = {
struct reg_info t3b_xgmac0_0_regs[] = {
struct reg_info t3b_pcie0_regs[] = {
struct reg_info t3b_xgmac0_1_regs[] = {
struct reg_info t3b_t3dbg_regs[] = {
struct reg_info t3b_mc7_pmrx_regs[] = {
struct reg_info t3b_sge3_regs[] = {
struct reg_info t3b_mc7_pmtx_regs[] = {
struct reg_info t3b_mc7_cm_regs[] = {
struct reg_info t3b_cim_regs[] = {
struct reg_info t3c_cim_regs[] = {
struct reg_info t3c_tp1_regs[] = {
struct reg_info t3c_ulp2_rx_regs[] = {
struct reg_info t3c_ulp2_tx_regs[] = {
struct reg_info t3c_pm1_rx_regs[] = {
struct reg_info t3c_pm1_tx_regs[] = {
struct reg_info t3c_pcix1_regs[] = {
struct reg_info t3c_mps0_regs[] = {
struct reg_info t3c_cpl_switch_regs[] = {
struct reg_info t3c_smb0_regs[] = {
struct reg_info t3c_i2cm0_regs[] = {
struct reg_info t3c_mi1_regs[] = {
struct reg_info t3c_jm1_regs[] = {
struct reg_info t3c_sf1_regs[] = {
struct reg_info t3c_pl3_regs[] = {
struct reg_info t3c_mc5a_regs[] = {
struct reg_info t3c_xgmac0_0_regs[] = {
struct reg_info t3c_xgmac0_1_regs[] = {
struct reg_info t3c_pcie0_regs[] = {
struct reg_info t3c_t3dbg_regs[] = {
struct reg_info t3c_sge3_regs[] = {
struct reg_info t3c_mc7_pmrx_regs[] = {
struct reg_info t3c_mc7_pmtx_regs[] = {
struct reg_info t3c_mc7_cm_regs[] = {
dump_block_regs(const struct reg_info *reg_array, const uint32_t *regs)
const struct reg_info *ri;
struct reg_info t4_dbg_regs[] = {
struct reg_info t4_mc_regs[] = {
struct reg_info t4_ma_regs[] = {
struct reg_info t4_edc_0_regs[] = {
struct reg_info t4_edc_1_regs[] = {
struct reg_info t4_hma_regs[] = {
struct reg_info t4_cim_regs[] = {
struct reg_info t4_tp_regs[] = {
struct reg_info t4_ulp_tx_regs[] = {
struct reg_info t4_pm_rx_regs[] = {
struct reg_info t4_pm_tx_regs[] = {
struct reg_info t4_mps_regs[] = {
struct reg_info t4_pcie_regs[] = {
struct reg_info t4_cpl_switch_regs[] = {
struct reg_info t4_smb_regs[] = {
struct reg_info t4_i2cm_regs[] = {
struct reg_info t4_mi_regs[] = {
struct reg_info t4_uart_regs[] = {
struct reg_info t4_pmu_regs[] = {
struct reg_info t4_ulp_rx_regs[] = {
struct reg_info t4_sf_regs[] = {
struct reg_info t4_pl_regs[] = {
struct reg_info t4_le_regs[] = {
struct reg_info t4_ncsi_regs[] = {
struct reg_info t4_xgmac_regs[] = {
struct reg_info t4_sge_regs[] = {
struct reg_info t6vf_pl_regs[] = {
struct reg_info t7vf_pl_regs[] = {
struct reg_info t4vf_cim_regs[] = {
struct reg_info t4vf_mbdata_regs[] = {
struct reg_info t5vf_sge_regs[] = {
struct reg_info t4vf_mps_regs[] = {
struct reg_info t4vf_sge_regs[] = {
struct reg_info t4vf_pl_regs[] = {
struct reg_info t5vf_pl_regs[] = {
struct reg_info t5_dbg_regs[] = {
struct reg_info t5_ma_regs[] = {
struct reg_info t5_pcie_regs[] = {
struct reg_info t5_cim_regs[] = {
struct reg_info t5_tp_regs[] = {
struct reg_info t5_ulp_tx_regs[] = {
struct reg_info t5_pm_rx_regs[] = {
struct reg_info t5_pm_tx_regs[] = {
struct reg_info t5_mps_regs[] = {
struct reg_info t5_sge_regs[] = {
struct reg_info t5_cpl_switch_regs[] = {
struct reg_info t5_smb_regs[] = {
struct reg_info t5_i2cm_regs[] = {
struct reg_info t5_mi_regs[] = {
struct reg_info t5_uart_regs[] = {
struct reg_info t5_pmu_regs[] = {
struct reg_info t5_ulp_rx_regs[] = {
struct reg_info t5_sf_regs[] = {
struct reg_info t5_pl_regs[] = {
struct reg_info t5_le_regs[] = {
struct reg_info t5_ncsi_regs[] = {
struct reg_info t5_mac_regs[] = {
struct reg_info t5_mc_0_regs[] = {
struct reg_info t5_mc_1_regs[] = {
struct reg_info t5_edc_t50_regs[] = {
struct reg_info t5_edc_t51_regs[] = {
struct reg_info t5_hma_t5_regs[] = {
struct reg_info t6_pcie_regs[] = {
struct reg_info t6_dbg_regs[] = {
struct reg_info t6_ma_regs[] = {
struct reg_info t6_cim_regs[] = {
struct reg_info t6_tp_regs[] = {
struct reg_info t6_ulp_tx_regs[] = {
struct reg_info t6_pm_rx_regs[] = {
struct reg_info t6_pm_tx_regs[] = {
struct reg_info t6_mps_regs[] = {
struct reg_info t6_cpl_switch_regs[] = {
struct reg_info t6_smb_regs[] = {
struct reg_info t6_i2cm_regs[] = {
struct reg_info t6_mi_regs[] = {
struct reg_info t6_uart_regs[] = {
struct reg_info t6_pmu_regs[] = {
struct reg_info t6_ulp_rx_regs[] = {
struct reg_info t6_sf_regs[] = {
struct reg_info t6_pl_regs[] = {
struct reg_info t6_le_regs[] = {
struct reg_info t6_ncsi_regs[] = {
struct reg_info t6_sge_regs[] = {
struct reg_info t6_mac_regs[] = {
struct reg_info t6_mc_0_regs[] = {
struct reg_info t6_edc_t60_regs[] = {
struct reg_info t6_edc_t61_regs[] = {
struct reg_info t6_hma_t6_regs[] = {
struct reg_info t7_pcie_regs[] = {
struct reg_info t7_cpl_switch_regs[] = {
struct reg_info t7_smb_regs[] = {
struct reg_info t7_i2cm_regs[] = {
struct reg_info t7_mi_regs[] = {
struct reg_info t7_uart_regs[] = {
struct reg_info t7_pmu_regs[] = {
struct reg_info t7_ulp_rx_regs[] = {
struct reg_info t7_sf_regs[] = {
struct reg_info t7_pl_regs[] = {
struct reg_info t7_le_regs[] = {
struct reg_info t7_ncsi_regs[] = {
struct reg_info t7_mac_t7_regs[] = {
struct reg_info t7_crypto_0_regs[] = {
struct reg_info t7_crypto_1_regs[] = {
struct reg_info t7_crypto_key_regs[] = {
struct reg_info t7_arm_regs[] = {
struct reg_info t7_mc_t70_regs[] = {
struct reg_info t7_mc_t71_regs[] = {
struct reg_info t7_edc_t60_regs[] = {
struct reg_info t7_edc_t61_regs[] = {
struct reg_info t7_hma_t6_regs[] = {
struct reg_info t7_gcache_regs[] = {
struct reg_info t7_dbg_regs[] = {
struct reg_info t7_sge_regs[] = {
struct reg_info t7_ma_regs[] = {
struct reg_info t7_cim_regs[] = {
struct reg_info t7_tp_regs[] = {
struct reg_info t7_ulp_tx_regs[] = {
struct reg_info t7_pm_rx_regs[] = {
struct reg_info t7_pm_tx_regs[] = {
struct reg_info t7_mps_regs[] = {