sys/arm/mv/armada/wdt.c

211

irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);

sys/arm/mv/armada/wdt.c

215

irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);

sys/arm/mv/armada/wdt.c

219

val = read_cpu_ctrl(RSTOUTn_MASK);

sys/arm/mv/armada/wdt.c

233

irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);

sys/arm/mv/armada/wdt.c

251

irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);

sys/arm/mv/armada/wdt.c

266

irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP);

sys/arm/mv/armada/wdt.c

286

val = read_cpu_ctrl(RSTOUTn_MASK);

sys/arm/mv/armada/wdt.c

290

irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);

sys/arm/mv/armada/wdt.c

294

irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);

sys/arm/mv/mv_common.c

206

read_cpu_ctrl_t read_cpu_ctrl;

sys/arm/mv/mv_common.c

406

cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL);

sys/arm/mv/mv_common.c

430

if (soc_decode_win_spec->read_cpu_ctrl != NULL)

sys/arm/mv/mv_common.c

431

return (soc_decode_win_spec->read_cpu_ctrl(reg));

sys/arm/mv/mv_common.c

562

mode = read_cpu_ctrl(CPU_CONFIG);

sys/arm/mv/mv_pci.c

589

(read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit))) {

sys/arm/mv/mv_pci.c

590

write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) &

sys/arm/mv/mvvar.h

105

uint32_t read_cpu_ctrl(uint32_t);

sys/arm/mv/timer.c

225

irq_cause = read_cpu_ctrl(sc->config->bridge_irq_cause);

sys/arm/mv/timer.c

229

irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);

sys/arm/mv/timer.c

260

irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);

sys/arm/mv/timer.c

375

irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);

sys/arm/mv/timer.c

405

irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);