read_config
ret = read_config();
static int read_config(void);
static int read_config(char *config_file);
if (!read_config(f_flag))
*rval = read_config(hypctx, n);
*rval = read_config(hypctx, 1);
sli4_cmd_read_config_t *read_config = buf;
read_config->hdr.command = SLI4_MBOX_COMMAND_READ_CONFIG;
sli4_res_read_config_t *read_config = sli4->bmbx.virt;
if (read_config->hdr.status) {
read_config->hdr.status);
sli4->config.has_extents = read_config->ext;
sli4->config.extent[SLI_RSRC_FCOE_VFI].base[0] = read_config->vfi_base;
sli4->config.extent[SLI_RSRC_FCOE_VFI].size = read_config->vfi_count;
sli4->config.extent[SLI_RSRC_FCOE_VPI].base[0] = read_config->vpi_base;
sli4->config.extent[SLI_RSRC_FCOE_VPI].size = read_config->vpi_count;
sli4->config.extent[SLI_RSRC_FCOE_RPI].base[0] = read_config->rpi_base;
sli4->config.extent[SLI_RSRC_FCOE_RPI].size = read_config->rpi_count;
sli4->config.extent[SLI_RSRC_FCOE_XRI].base[0] = read_config->xri_base;
sli4->config.extent[SLI_RSRC_FCOE_XRI].size = OCS_MIN(255,read_config->xri_count);
sli4->config.extent[SLI_RSRC_FCOE_FCFI].size = read_config->fcfi_count;
sli4->config.topology = read_config->topology;
sli4->config.ptv = read_config->ptv;
sli4->config.tf = read_config->tf;
sli4->config.pt = read_config->pt;
sli4->config.e_d_tov = read_config->e_d_tov;
sli4->config.r_a_tov = read_config->r_a_tov;
sli4->config.link_module_type = read_config->lmt;
sli4->config.max_qcount[SLI_QTYPE_EQ] = read_config->eq_count;
sli4->config.max_qcount[SLI_QTYPE_CQ] = read_config->cq_count;
sli4->config.max_qcount[SLI_QTYPE_WQ] = read_config->wq_count;
sli4->config.max_qcount[SLI_QTYPE_RQ] = read_config->rq_count;
*busnum = read_config(0, bus, 0x10, func, 0xd4, 1) + 1;
*busnum = read_config(0, bus, slot, func, 0x44, 1);
*busnum = read_config(0, bus, slot, func, 0xc8, 1);
host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
id = read_config(0, bus, slot, func, PCIR_DEVVENDOR, 4);
*busnum = read_config(0, bus, slot, func, 0x4a, 1);
*busnum = read_config(0, bus, 0x10, func, 0xd0, 1);
*busnum = read_config(0, bus, 0x10, func, 0xd1, 1) + 1;
*busnum = read_config(0, bus, 0x10, func, 0xd3, 1);
int host_pcib_get_busno(pci_read_config_fn read_config, int bus,
read_config();
void read_config(void);
cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4);
low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4);
high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4);
val = read_config(fd, &p->pc_sel, ptr, 4);
hdr = read_config(fd, &p->pc_sel, ptr + PCIR_VSEC_HEADER, 4);
val = read_config(fd, &p->pc_sel, ptr + i, 4);
val = read_config(fd, &p->pc_sel, ptr + 8, 4);
iov_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_CTL, 2);
total_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_TOTAL_VFS, 2);
num_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_NUM_VFS, 2);
vf_offset = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_OFF, 2);
vf_stride = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_STRIDE, 2);
vf_did = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_DID, 2);
page_caps = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_CAP, 4);
page_size = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_SIZE, 4);
acs_cap = read_config(fd, &p->pc_sel, ptr + PCIR_ACS_CAP, 2);
acs_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_ACS_CTL, 2);
ecap = read_config(fd, &p->pc_sel, ptr, 4);
ecap = read_config(fd, &p->pc_sel, ptr, 4);
sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2);
ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2);
ptr = read_config(fd, &p->pc_sel, ptr, 1);
cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);
ecap = read_config(fd, &p->pc_sel, ptr, 4);
ecap = read_config(fd, &p->pc_sel, ptr, 4);
status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4);
command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2);
reg = read_config(fd, &p->pc_sel,
reg = read_config(fd, &p->pc_sel,
length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1);
version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA,
fvec = read_config(fd, &p->pc_sel, ptr +
fvec = read_config(fd, &p->pc_sel, ptr +
debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2);
id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4);
cap_h = read_config(fd, &p->pc_sel, ptr + PCIR_AMDIOMMU_CAP_HEADER, 4);
base_low = read_config(fd, &p->pc_sel, ptr + PCIR_AMDIOMMU_BASE_LOW,
base_high = read_config(fd, &p->pc_sel, ptr + PCIR_AMDIOMMU_BASE_HIGH,
range = read_config(fd, &p->pc_sel, ptr + PCIR_AMDIOMMU_RANGE, 4);
misc0 = read_config(fd, &p->pc_sel, ptr + PCIR_AMDIOMMU_MISC0, 4);
misc1 = read_config(fd, &p->pc_sel,
cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2);
status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2);
flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2);
cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4);
ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2);
cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP2, 4);
ctl = read_config(fd, &p->pc_sel,
cap = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4);
sta = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_STA, 2);
ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2);
ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2);
cap = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CAP, 4);
sta = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_STA, 2);
ctl = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CTL, 2);
status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4);
ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2);
val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4);
command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4);
val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4);
cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1);
num_ent = read_config(fd, &p->pc_sel, ptr + PCIR_EA_NUM_ENT, 2);
val = read_config(fd, &p->pc_sel, ptr, 4);
val = read_config(fd, &p->pc_sel, ptr, 4);
dw[b] = read_config(fd, &p->pc_sel, ptr, 4);
sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2);
ptr = read_config(fd, &p->pc_sel, ptr, 1);
cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);
sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4);
mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4);
sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4);
sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2);
sta = read_config(fd, &p->pc_sel, pcie + PCIER_DEVICE_STA, 2);
mask = read_config(fd, &p->pc_sel, aer + PCIR_AER_UC_STATUS, 4);
severity = read_config(fd, &p->pc_sel, aer + PCIR_AER_UC_SEVERITY, 4);
mask = read_config(fd, &p->pc_sel, aer + PCIR_AER_COR_STATUS, 4);
printf("%0*x", width*2, read_config(fd, sel, reg, width));
val = read_config(fd, &p->pc_sel, PCIR_IOBASEL_1, 1);
if (val != 0 || read_config(fd, &p->pc_sel, PCIR_IOLIMITL_1, 1) != 0) {
read_config(fd, &p->pc_sel, PCIR_IOBASEH_1, 2),
read_config(fd, &p->pc_sel, PCIR_IOLIMITH_1, 2),
read_config(fd, &p->pc_sel, PCIR_IOLIMITL_1, 1));
read_config(fd, &p->pc_sel, PCIR_IOLIMITL_1, 1));
read_config(fd, &p->pc_sel, PCIR_MEMBASE_1, 2));
read_config(fd, &p->pc_sel, PCIR_MEMLIMIT_1, 2));
val = read_config(fd, &p->pc_sel, PCIR_PMBASEL_1, 2);
if (val != 0 || read_config(fd, &p->pc_sel, PCIR_PMLIMITL_1, 2) != 0) {
read_config(fd, &p->pc_sel, PCIR_PMBASEH_1, 4),
read_config(fd, &p->pc_sel, PCIR_PMLIMITH_1, 4),
read_config(fd, &p->pc_sel, PCIR_PMLIMITL_1, 2));
read_config(fd, &p->pc_sel, PCIR_PMLIMITL_1, 2));
bctl = read_config(fd, &p->pc_sel, PCIR_BRIDGECTL_1, 2);
PCI_CBBMEMBASE(read_config(fd, &p->pc_sel, basereg, 4)),
PCI_CBBMEMLIMIT(read_config(fd, &p->pc_sel, limitreg, 4)));
val = read_config(fd, &p->pc_sel, basereg, 2);
base = PCI_CBBIOBASE(read_config(fd, &p->pc_sel, basereg, 4));
limit = PCI_CBBIOBASE(read_config(fd, &p->pc_sel, limitreg, 4));
limit = PCI_CBBIOBASE(read_config(fd, &p->pc_sel, limitreg, 2));
bctl = read_config(fd, &p->pc_sel, PCIR_BRIDGECTL_2, 2);
uint32_t read_config(int fd, struct pcisel *sel, long reg, int width);