rdmsr_safe
int rdmsr_safe(u_int msr, uint64_t *val);
#define rdmsrl_safe(msr, val) rdmsr_safe(msr, val)
ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
ret = rdmsr_safe(data->msr, &data->data);
ret = rdmsr_safe(data->msr, ®);
ret = rdmsr_safe(data->msr, ®);
rdmsr_safe(MSR_BIOS_SIGN, &rev0); /* Get current microcode revision. */
rdmsr_safe(0x1205, &res);
rdmsr_safe(MSR_BIOS_SIGN, &rev1); /* Get new microcode revision. */
int rdmsr_safe(u_int msr, uint64_t *val);
req->err = rdmsr_safe(MSR_AMD_10H_11H_CONFIG + i,
error = rdmsr_safe(MSR_AMD_CPPC_ENABLE, &data->enable);
error = rdmsr_safe(MSR_AMD_CPPC_CAPS_1, &data->caps);
error = rdmsr_safe(MSR_AMD_CPPC_REQUEST, &data->req);
error = rdmsr_safe(MSR_AMD_CPPC_REQUEST, &val);
error = rdmsr_safe(MSR_AMD_CPPC_CAPS_1, &data->caps);
rdmsr_safe(MSR_IA32_PM_ENABLE, &data);
rdmsr_safe(MSR_IA32_HWP_CAPABILITIES, &data);
rdmsr_safe(MSR_IA32_HWP_REQUEST, &data);
rdmsr_safe(MSR_IA32_HWP_REQUEST_PKG, &data2);
ret = rdmsr_safe(MSR_IA32_ENERGY_PERF_BIAS, &epb);
ret = rdmsr_safe(MSR_IA32_HWP_REQUEST, &sc->req);
ret = rdmsr_safe(MSR_IA32_HWP_CAPABILITIES, &caps);
error = rdmsr_safe(a->msr, &v);
error = rdmsr_safe(a->msr, &v);
error = rdmsr_safe(a->msr, &v);