bin/pwd/pwd.c

45

struct stat log, phy;

bin/pwd/pwd.c

60

if (stat(pwd, &log) != 0 || stat(".", &phy) != 0 ||

bin/pwd/pwd.c

61

log.st_dev != phy.st_dev || log.st_ino != phy.st_ino)

sbin/camcontrol/camcontrol.c

8451

int phy = -1;

sbin/camcontrol/camcontrol.c

8601

phy = atoi(optarg);

sbin/camcontrol/camcontrol.c

8619

if (phy == -1) {

sbin/camcontrol/camcontrol.c

8660

phy,

sbin/etherswitchcfg/etherswitchcfg.c

143

read_phyregister(struct cfg *cfg, int phy, int reg)

sbin/etherswitchcfg/etherswitchcfg.c

147

er.phy = phy;

sbin/etherswitchcfg/etherswitchcfg.c

155

write_phyregister(struct cfg *cfg, int phy, int reg, int val)

sbin/etherswitchcfg/etherswitchcfg.c

159

er.phy = phy;

sbin/etherswitchcfg/etherswitchcfg.c

415

int phy, reg, val;

sbin/etherswitchcfg/etherswitchcfg.c

418

phy = strtol(arg, &c, 0);

sbin/etherswitchcfg/etherswitchcfg.c

429

write_phyregister(cfg, phy, reg, val);

sbin/etherswitchcfg/etherswitchcfg.c

431

printf("\treg %d.0x%02x=0x%04x\n", phy, reg, read_phyregister(cfg, phy, reg));

sys/arm/allwinner/aw_usb3phy.c

93

static int awusb3phy_phy_enable(struct phynode *phy, bool enable);

sys/arm/allwinner/aw_usb3phy.c

94

static int awusb3phy_get_mode(struct phynode *phy, int *mode);

sys/arm/allwinner/aw_usb3phy.c

95

static int awusb3phy_set_mode(struct phynode *phy, int mode);

sys/arm/allwinner/aw_usbphy.c

167

static int awusbphy_phy_enable(struct phynode *phy, bool enable);

sys/arm/allwinner/aw_usbphy.c

168

static int awusbphy_get_mode(struct phynode *phy, int *mode);

sys/arm/allwinner/aw_usbphy.c

169

static int awusbphy_set_mode(struct phynode *phy, int mode);

sys/arm/allwinner/aw_usbphy.c

354

intptr_t phy;

sys/arm/allwinner/aw_usbphy.c

360

phy = phynode_get_id(phynode);

sys/arm/allwinner/aw_usbphy.c

363

if (phy < 0 || phy >= sc->phy_conf->num_phys)

sys/arm/allwinner/aw_usbphy.c

367

awusbphy_configure(dev, phy);

sys/arm/allwinner/aw_usbphy.c

370

reg = sc->reg[phy];

sys/arm/allwinner/aw_usbphy.c

374

if (phy == 0) {

sys/arm/allwinner/aw_usbphy.c

398

enable ? "enable" : "disable", (intmax_t)phy);

sys/arm/allwinner/aw_usbphy.c

423

intptr_t phy;

sys/arm/allwinner/aw_usbphy.c

429

phy = phynode_get_id(phynode);

sys/arm/allwinner/aw_usbphy.c

432

if (phy != 0) {

sys/arm/allwinner/if_awg.c

238

awg_miibus_readreg(device_t dev, int phy, int reg)

sys/arm/allwinner/if_awg.c

248

(phy << PHY_ADDR_SHIFT) |

sys/arm/allwinner/if_awg.c

261

phy, reg);

sys/arm/allwinner/if_awg.c

267

awg_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/arm/allwinner/if_awg.c

277

(phy << PHY_ADDR_SHIFT) |

sys/arm/allwinner/if_awg.c

288

phy, reg);

sys/arm/allwinner/if_emac.c

1007

EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);

sys/arm/allwinner/if_emac.c

1023

emac_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/arm/allwinner/if_emac.c

1030

EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);

sys/arm/allwinner/if_emac.c

999

emac_miibus_readreg(device_t dev, int phy, int reg)

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

348

static int xusbpadctl_phy_enable(struct phynode *phy, bool enable);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

686

xusbpadctl_phy_enable(struct phynode *phy, bool enable)

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

695

dev = phynode_get_device(phy);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

696

id = phynode_get_id(phy);

sys/arm/nvidia/tegra_ahci.c

241

phy_t phy;

sys/arm/nvidia/tegra_ahci.c

323

rv = phy_get_by_ofw_name(sc->dev, 0, "sata-0", &sc->phy);

sys/arm/nvidia/tegra_ahci.c

325

rv = phy_get_by_ofw_idx(sc->dev, 0, 0, &sc->phy);

sys/arm/nvidia/tegra_ahci.c

431

rv = phy_enable(sc->phy);

sys/arm/nvidia/tegra_ehci.c

182

rv = phy_get_by_ofw_property(sc->dev, 0, "nvidia,phy", &sc->phy);

sys/arm/nvidia/tegra_ehci.c

215

rv = phy_enable(sc->phy);

sys/arm/nvidia/tegra_ehci.c

80

phy_t phy;

sys/arm/nvidia/tegra_pcie.c

1297

rv = phy_enable(sc->ports[i]->phy);

sys/arm/nvidia/tegra_pcie.c

319

phy_t phy; /* port phy */

sys/arm/nvidia/tegra_pcie.c

976

rv = phy_get_by_ofw_name(sc->dev, node, "pcie-0", &port->phy);

sys/arm/nvidia/tegra_usbphy.c

297

static int usbphy_phy_enable(struct phynode *phy, bool enable);

sys/arm/nvidia/tegra_usbphy.c

559

usbphy_phy_enable(struct phynode *phy, bool enable)

sys/arm/nvidia/tegra_usbphy.c

565

dev = phynode_get_device(phy);

sys/arm/ti/cpsw/if_cpsw.c

1003

sc->phy = sc->swsc->port[sc->unit].phy;

sys/arm/ti/cpsw/if_cpsw.c

1066

cpswp_ifmedia_sts, BMSR_DEFCAPMASK, sc->phy, MII_OFFSET_ANY, 0);

sys/arm/ti/cpsw/if_cpsw.c

1076

MDIO_PHYSEL_LINKINTENB | (sc->phy & 0x1F));

sys/arm/ti/cpsw/if_cpsw.c

120

static int cpswp_miibus_readreg(device_t, int phy, int reg);

sys/arm/ti/cpsw/if_cpsw.c

121

static int cpswp_miibus_writereg(device_t, int phy, int reg, int value);

sys/arm/ti/cpsw/if_cpsw.c

1479

cpswp_miibus_readreg(device_t dev, int phy, int reg)

sys/arm/ti/cpsw/if_cpsw.c

1491

cmd = MDIO_PHYACCESS_GO | (reg & 0x1F) << 21 | (phy & 0x1F) << 16;

sys/arm/ti/cpsw/if_cpsw.c

1508

cpswp_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/arm/ti/cpsw/if_cpsw.c

1521

(reg & 0x1F) << 21 | (phy & 0x1F) << 16 | (value & 0xFFFF);

sys/arm/ti/cpsw/if_cpsw.c

2998

cpsw_readphy(device_t dev, int phy, int reg)

sys/arm/ti/cpsw/if_cpsw.c

3006

cpsw_writephy(device_t dev, int phy, int reg, int data)

sys/arm/ti/cpsw/if_cpsw.c

737

int len, phy, vlan;

sys/arm/ti/cpsw/if_cpsw.c

743

phy = -1;

sys/arm/ti/cpsw/if_cpsw.c

758

if (fdt_get_phyaddr(child, NULL, &phy, NULL) != 0){

sys/arm/ti/cpsw/if_cpsw.c

760

phy = -1;

sys/arm/ti/cpsw/if_cpsw.c

765

phy = phy_id[1];

sys/arm/ti/cpsw/if_cpsw.c

780

if (phy == -1)

sys/arm/ti/cpsw/if_cpsw.c

782

sc->port[port].phy = phy;

sys/arm/ti/cpsw/if_cpswvar.h

144

uint32_t phy;

sys/arm/ti/cpsw/if_cpswvar.h

83

int phy;

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

257

brcm_iproc_mdio_write_mux(device_t dev, int bus, int phy, int reg, int val)

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

268

return (brcm_iproc_mdio_op(sc, phy, reg, val, MDIO_CTRL_WRITE_OP));

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

272

brcm_iproc_mdio_read_mux(device_t dev, int bus, int phy, int reg)

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

283

return (brcm_iproc_mdio_op(sc, phy, reg, 0, MDIO_CTRL_READ_OP));

sys/arm64/broadcom/brcmmdio/mdio_nexus_iproc.c

107

brcm_mdionexus_mdio_readreg(device_t dev, int phy, int reg)

sys/arm64/broadcom/brcmmdio/mdio_nexus_iproc.c

114

sc->mux_id, phy, reg));

sys/arm64/broadcom/brcmmdio/mdio_nexus_iproc.c

118

brcm_mdionexus_mdio_writereg(device_t dev, int phy, int reg, int val)

sys/arm64/broadcom/brcmmdio/mdio_nexus_iproc.c

125

sc->mux_id, phy, reg, val));

sys/arm64/broadcom/genet/if_genet.c

1672

gen_miibus_readreg(device_t dev, int phy, int reg)

sys/arm64/broadcom/genet/if_genet.c

1681

(phy << GENET_MDIO_ADDR_SHIFT) | (reg << GENET_MDIO_REG_SHIFT));

sys/arm64/broadcom/genet/if_genet.c

1697

phy, reg);

sys/arm64/broadcom/genet/if_genet.c

1703

gen_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/arm64/broadcom/genet/if_genet.c

1711

(phy << GENET_MDIO_ADDR_SHIFT) | (reg << GENET_MDIO_REG_SHIFT) |

sys/arm64/broadcom/genet/if_genet.c

1723

phy, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1421

xusbpadctl_phy_enable(struct phynode *phy, bool enable)

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1430

dev = phynode_get_device(phy);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1431

id = phynode_get_id(phy);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

520

static int xusbpadctl_phy_enable(struct phynode *phy, bool enable);

sys/arm64/rockchip/rk3399_emmcphy.c

130

intptr_t phy;

sys/arm64/rockchip/rk3399_emmcphy.c

136

phy = phynode_get_id(phynode);

sys/arm64/rockchip/rk3399_emmcphy.c

140

device_printf(dev, "Phy id: %ld\n", phy);

sys/arm64/rockchip/rk3399_emmcphy.c

142

if (phy != 0) {

sys/arm64/rockchip/rk3399_emmcphy.c

143

device_printf(dev, "Unknown phy: %ld\n", phy);

sys/arm64/rockchip/rk3399_emmcphy.c

278

intptr_t phy;

sys/arm64/rockchip/rk3399_emmcphy.c

315

phy = phynode_get_id(phynode);

sys/arm64/rockchip/rk3399_emmcphy.c

316

device_printf(dev, "Attached phy id: %ld\n", phy);

sys/arm64/rockchip/rk3568_pcie.c

102

phy_t phy;

sys/arm64/rockchip/rk3568_pcie.c

169

if (phy_enable(sc->phy)) {

sys/arm64/rockchip/rk3568_pcie.c

264

if (sc->phy)

sys/arm64/rockchip/rk3568_pcie.c

265

phy_release(sc->phy);

sys/arm64/rockchip/rk3568_pcie.c

374

if (phy_get_by_ofw_name(dev, 0, "pcie-phy", &sc->phy)) {

sys/arm64/rockchip/rk_pcie_phy.c

236

intptr_t phy;

sys/arm64/rockchip/rk_pcie_phy.c

240

phy = phynode_get_id(phynode);

sys/arm64/rockchip/rk_pcie_phy.c

244

rv = rk_pcie_phy_up(sc, (int)phy);

sys/arm64/rockchip/rk_pcie_phy.c

246

rv = rk_pcie_phy_down(sc, (int) phy);

sys/arm64/rockchip/rk_typec_phy.c

139

static int rk_typec_phy_get_mode(struct phynode *phy, int *mode);

sys/arm64/rockchip/rk_typec_phy.c

140

static int rk_typec_phy_set_mode(struct phynode *phy, int mode);

sys/arm64/rockchip/rk_typec_phy.c

189

intptr_t phy;

sys/arm64/rockchip/rk_typec_phy.c

194

phy = phynode_get_id(phynode);

sys/arm64/rockchip/rk_typec_phy.c

197

if (phy != RK3399_TYPEC_PHY_USB3)

sys/arm64/rockchip/rk_typec_phy.c

291

intptr_t phy;

sys/arm64/rockchip/rk_typec_phy.c

295

phy = phynode_get_id(phynode);

sys/arm64/rockchip/rk_typec_phy.c

298

if (phy != RK3399_TYPEC_PHY_USB3)

sys/arm64/rockchip/rk_typec_phy.c

310

intptr_t phy;

sys/arm64/rockchip/rk_typec_phy.c

314

phy = phynode_get_id(phynode);

sys/arm64/rockchip/rk_typec_phy.c

317

if (phy != RK3399_TYPEC_PHY_USB3)

sys/arm64/rockchip/rk_usb2phy.c

122

intptr_t phy;

sys/arm64/rockchip/rk_usb2phy.c

126

phy = phynode_get_id(phynode);

sys/arm64/rockchip/rk_usb2phy.c

129

if (phy != RK_USBPHY_HOST)

sys/arm64/rockchip/rk_usb2phy.c

153

intptr_t phy;

sys/arm64/rockchip/rk_usb2phy.c

157

phy = phynode_get_id(phynode);

sys/arm64/rockchip/rk_usb2phy.c

160

if (phy != RK_USBPHY_HOST)

sys/arm64/rockchip/rk_usb2phy.c

172

intptr_t phy;

sys/arm64/rockchip/rk_usb2phy.c

176

phy = phynode_get_id(phynode);

sys/arm64/rockchip/rk_usb2phy.c

179

if (phy != RK_USBPHY_HOST)

sys/arm64/rockchip/rk_usb2phy.c

98

static int rk_usb2phy_get_mode(struct phynode *phy, int *mode);

sys/arm64/rockchip/rk_usb2phy.c

99

static int rk_usb2phy_set_mode(struct phynode *phy, int mode);

sys/arm64/rockchip/rk_usbphy.c

91

rk_phynode_phy_enable(struct phynode *phy, bool enable)

sys/arm64/rockchip/rk_usbphy.c

96

sc = phynode_get_softc(phy);

sys/cam/scsi/scsi_enc_ses.c

2292

struct ses_elm_sas_device_phy *phy;

sys/cam/scsi/scsi_enc_ses.c

2306

phy = &addl->proto_data.sasdev_phys[i];

sys/cam/scsi/scsi_enc_ses.c

2308

if (ses_elm_sas_dev_phy_sata_dev(phy))

sys/cam/scsi/scsi_enc_ses.c

2313

ses_elm_sas_dev_phy_dev_type(phy), phy->phy_id);

sys/cam/scsi/scsi_enc_ses.c

2314

SES_PRINT_PORTS(phy->initiator_ports, "Initiator");

sys/cam/scsi/scsi_enc_ses.c

2315

SES_PRINT_PORTS(phy->target_ports, "Target");

sys/cam/scsi/scsi_enc_ses.c

2320

(uintmax_t)scsi_8btou64(phy->parent_addr),

sys/cam/scsi/scsi_enc_ses.c

2321

(uintmax_t)scsi_8btou64(phy->phy_addr));

sys/cam/scsi/scsi_enc_ses.c

757

ses_elm_sas_dev_phy_sata_dev(struct ses_elm_sas_device_phy *phy)

sys/cam/scsi/scsi_enc_ses.c

759

return ((phy)->target_ports & 0x1);

sys/cam/scsi/scsi_enc_ses.c

762

ses_elm_sas_dev_phy_sata_port(struct ses_elm_sas_device_phy *phy)

sys/cam/scsi/scsi_enc_ses.c

764

return ((phy)->target_ports >> 7);

sys/cam/scsi/scsi_enc_ses.c

767

ses_elm_sas_dev_phy_dev_type(struct ses_elm_sas_device_phy *phy)

sys/cam/scsi/scsi_enc_ses.c

769

return (((phy)->byte0 >> 4) & 0x7);

sys/cam/scsi/smp_all.c

522

int ignore_zone_group, int phy, uint32_t timeout)

sys/cam/scsi/smp_all.c

541

request->phy = phy;

sys/cam/scsi/smp_all.c

582

uint32_t expected_exp_change_count, int phy, int phy_op,

sys/cam/scsi/smp_all.c

604

request->phy = phy;

sys/cam/scsi/smp_all.h

253

uint8_t phy;

sys/cam/scsi/smp_all.h

267

uint8_t phy;

sys/cam/scsi/smp_all.h

409

uint8_t phy;

sys/cam/scsi/smp_all.h

503

int ignore_zone_group, int phy, uint32_t timeout);

sys/cam/scsi/smp_all.h

515

uint32_t expected_exp_change_count, int phy, int phy_op,

sys/dev/ae/if_ae.c

111

static int ae_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/ae/if_ae.c

112

static int ae_miibus_writereg(device_t dev, int phy, int reg, int val);

sys/dev/ae/if_ae.c

786

ae_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/ae/if_ae.c

821

ae_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/age/if_age.c

207

age_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/age/if_age.c

236

age_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/al_eth/al_eth.c

3420

al_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/al_eth/al_eth.c

3448

al_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/alc/if_alc.c

274

alc_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/alc/if_alc.c

281

v = alc_mii_readreg_816x(sc, phy, reg);

sys/dev/alc/if_alc.c

283

v = alc_mii_readreg_813x(sc, phy, reg);

sys/dev/alc/if_alc.c

288

alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg)

sys/dev/alc/if_alc.c

321

alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg)

sys/dev/alc/if_alc.c

348

alc_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/alc/if_alc.c

355

v = alc_mii_writereg_816x(sc, phy, reg, val);

sys/dev/alc/if_alc.c

357

v = alc_mii_writereg_813x(sc, phy, reg, val);

sys/dev/alc/if_alc.c

362

alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val)

sys/dev/alc/if_alc.c

384

alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val)

sys/dev/ale/if_ale.c

201

ale_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/ale/if_ale.c

227

ale_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/ath/ath_hal/ah.c

449

switch (rates->info[rateix].phy) {

sys/dev/ath/ath_hal/ah.c

507

__func__, rates->info[rateix].phy, rateix);

sys/dev/ath/ath_hal/ah.h

684

uint8_t phy; /* CCK/OFDM/XR */

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2743

if (rt->info[i].phy != IEEE80211_T_CCK)

sys/dev/ath/ath_rate/sample/sample.c

1480

if (rt->info[y].phy == IEEE80211_T_HT)

sys/dev/ath/ath_rate/sample/sample.c

186

if (rt->info[rix0].phy != IEEE80211_T_HT) {

sys/dev/ath/ath_rate/sample/sample.c

297

return rt->info[rix].phy == IEEE80211_T_HT ?

sys/dev/ath/ath_rate/sample/sample.c

306

return rt->info[rix].phy == IEEE80211_T_HT ? "MCS" : "Mb ";

sys/dev/ath/ath_rate/sample/sample.c

331

(rt->info[rix].phy != IEEE80211_T_HT)) {

sys/dev/ath/ath_rate/sample/sample.c

462

(rt->info[rix].phy != IEEE80211_T_HT)) {

sys/dev/ath/ath_rate/sample/sample.c

589

if (rt->info[rix].phy == IEEE80211_T_HT)

sys/dev/ath/ath_rate/sample/sample.c

631

if (rt->info[rix].phy == IEEE80211_T_HT)

sys/dev/ath/ath_rate/sample/sample.c

635

if (rt->info[rix].phy != IEEE80211_T_HT)

sys/dev/ath/ath_rate/sample/sample.c

858

if (rt->info[best_rix].phy == IEEE80211_T_HT)

sys/dev/ath/ath_rate/sample/sample.h

160

switch (rt->info[rix].phy) {

sys/dev/ath/ath_rate/sample/sample.h

188

rt->info[rix].phy == IEEE80211_T_OFDM) {

sys/dev/ath/if_ath.c

6511

if (rt->info[i].phy != IEEE80211_T_HT)

sys/dev/ath/if_ath.c

6525

if (rt->info[i].phy == IEEE80211_T_HT)

sys/dev/ath/if_ath.c

6529

rt->info[i].phy == IEEE80211_T_OFDM)

sys/dev/ath/if_ath_ioctl.c

265

if (rt->info[sc->sc_txrix].phy & IEEE80211_T_HT)

sys/dev/ath/if_ath_tx.c

1078

rt->info[rix].phy == IEEE80211_T_OFDM &&

sys/dev/ath/if_ath_tx.c

1106

rt->info[rix].phy == IEEE80211_T_HT &&

sys/dev/ath/if_ath_tx.c

1214

if (rt->info[cix].phy == IEEE80211_T_HT) {

sys/dev/axgbe/if_axgbe.c

188

sc->prv.phy.speed = SPEED_10000;

sys/dev/axgbe/if_axgbe.c

189

sc->prv.phy.autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/if_axgbe.c

192

sc->prv.phy.speed = SPEED_2500;

sys/dev/axgbe/if_axgbe.c

193

sc->prv.phy.autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/if_axgbe.c

196

sc->prv.phy.speed = SPEED_1000;

sys/dev/axgbe/if_axgbe.c

197

sc->prv.phy.autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/if_axgbe.c

200

sc->prv.phy.autoneg = AUTONEG_ENABLE;

sys/dev/axgbe/if_axgbe.c

216

if (!sc->prv.phy.link)

sys/dev/axgbe/if_axgbe.c

222

if (sc->prv.phy.duplex == DUPLEX_FULL)

sys/dev/axgbe/if_axgbe.c

227

switch (sc->prv.phy.speed) {

sys/dev/axgbe/if_axgbe.c

393

sc->prv.phy.advertising = ADVERTISED_10000baseKR_Full |

sys/dev/axgbe/if_axgbe_pci.c

2289

pdata->phy_link, sc->link_status, pdata->phy.speed);

sys/dev/axgbe/if_axgbe_pci.c

2297

if (pdata->phy.speed & SPEED_10000)

sys/dev/axgbe/if_axgbe_pci.c

2300

else if (pdata->phy.speed & SPEED_2500)

sys/dev/axgbe/if_axgbe_pci.c

2303

else if (pdata->phy.speed & SPEED_1000)

sys/dev/axgbe/if_axgbe_pci.c

2306

else if (pdata->phy.speed & SPEED_100)

sys/dev/axgbe/if_axgbe_pci.c

2309

else if (pdata->phy.speed & SPEED_10)

sys/dev/axgbe/if_axgbe_pci.c

2333

sc->pdata.phy.speed = SPEED_10000;

sys/dev/axgbe/if_axgbe_pci.c

2334

sc->pdata.phy.autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/if_axgbe_pci.c

2337

sc->pdata.phy.speed = SPEED_2500;

sys/dev/axgbe/if_axgbe_pci.c

2338

sc->pdata.phy.autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/if_axgbe_pci.c

2341

sc->pdata.phy.speed = SPEED_1000;

sys/dev/axgbe/if_axgbe_pci.c

2342

sc->pdata.phy.autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/if_axgbe_pci.c

2345

sc->pdata.phy.speed = SPEED_100;

sys/dev/axgbe/if_axgbe_pci.c

2346

sc->pdata.phy.autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/if_axgbe_pci.c

2349

sc->pdata.phy.autoneg = AUTONEG_ENABLE;

sys/dev/axgbe/if_axgbe_pci.c

2454

if (!sc->pdata.phy.link)

sys/dev/axgbe/if_axgbe_pci.c

2460

axgbe_printf(1, "Speed 0x%x Mode %d\n", sc->pdata.phy.speed,

sys/dev/axgbe/if_axgbe_pci.c

317

axgbe_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/axgbe/if_axgbe_pci.c

323

axgbe_printf(3, "%s: phy %d reg %d\n", __func__, phy, reg);

sys/dev/axgbe/if_axgbe_pci.c

325

val = xgbe_phy_mii_read(pdata, phy, reg);

sys/dev/axgbe/if_axgbe_pci.c

332

axgbe_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/axgbe/if_axgbe_pci.c

337

axgbe_printf(3, "%s: phy %d reg %d val 0x%x\n", __func__, phy, reg, val);

sys/dev/axgbe/if_axgbe_pci.c

339

xgbe_phy_mii_write(pdata, phy, reg, val);

sys/dev/axgbe/if_axgbe_pci.c

353

axgbe_printf(2, "%s: Link %d/%d\n", __func__, pdata->phy.link,

sys/dev/axgbe/if_axgbe_pci.c

366

pdata->phy.link = 1;

sys/dev/axgbe/if_axgbe_pci.c

371

pdata->phy.link = 1;

sys/dev/axgbe/if_axgbe_pci.c

374

pdata->phy.link = 0;

sys/dev/axgbe/if_axgbe_pci.c

838

prev_state = pdata->phy.link;

sys/dev/axgbe/if_axgbe_pci.c

842

if (prev_state != pdata->phy.link) {

sys/dev/axgbe/if_axgbe_pci.c

843

pdata->phy_link = pdata->phy.link;

sys/dev/axgbe/xgbe-mdio.c

1072

if (pdata->phy.link)

sys/dev/axgbe/xgbe-mdio.c

1075

xgbe_phy_speed_string(pdata->phy.speed),

sys/dev/axgbe/xgbe-mdio.c

1076

pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",

sys/dev/axgbe/xgbe-mdio.c

1088

pdata->phy_link, pdata->phy.link,

sys/dev/axgbe/xgbe-mdio.c

1089

pdata->tx_pause, pdata->phy.tx_pause,

sys/dev/axgbe/xgbe-mdio.c

1090

pdata->rx_pause, pdata->phy.rx_pause,

sys/dev/axgbe/xgbe-mdio.c

1091

pdata->phy_speed, pdata->phy.speed,

sys/dev/axgbe/xgbe-mdio.c

1092

pdata->pause_autoneg, pdata->phy.pause_autoneg);

sys/dev/axgbe/xgbe-mdio.c

1094

if (pdata->phy.link) {

sys/dev/axgbe/xgbe-mdio.c

1096

pdata->pause_autoneg = pdata->phy.pause_autoneg;

sys/dev/axgbe/xgbe-mdio.c

1098

if (pdata->tx_pause != pdata->phy.tx_pause) {

sys/dev/axgbe/xgbe-mdio.c

1101

pdata->phy.tx_pause);

sys/dev/axgbe/xgbe-mdio.c

1102

pdata->tx_pause = pdata->phy.tx_pause;

sys/dev/axgbe/xgbe-mdio.c

1106

if (pdata->rx_pause != pdata->phy.rx_pause) {

sys/dev/axgbe/xgbe-mdio.c

1109

pdata->phy.rx_pause);

sys/dev/axgbe/xgbe-mdio.c

1110

pdata->rx_pause = pdata->phy.rx_pause;

sys/dev/axgbe/xgbe-mdio.c

1115

if (pdata->phy_speed != pdata->phy.speed) {

sys/dev/axgbe/xgbe-mdio.c

1117

pdata->phy_speed = pdata->phy.speed;

sys/dev/axgbe/xgbe-mdio.c

1120

if (pdata->phy_link != pdata->phy.link) {

sys/dev/axgbe/xgbe-mdio.c

1122

pdata->phy_link = pdata->phy.link;

sys/dev/axgbe/xgbe-mdio.c

1131

pdata->phy.link, new_state);

sys/dev/axgbe/xgbe-mdio.c

1154

mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed);

sys/dev/axgbe/xgbe-mdio.c

1170

if (pdata->phy.duplex != DUPLEX_FULL)

sys/dev/axgbe/xgbe-mdio.c

1195

if (pdata->phy.autoneg != AUTONEG_ENABLE) {

sys/dev/axgbe/xgbe-mdio.c

1315

XGBE_ZERO_LP_ADV(&pdata->phy);

sys/dev/axgbe/xgbe-mdio.c

1317

if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)

sys/dev/axgbe/xgbe-mdio.c

1325

pdata->phy.speed = SPEED_100;

sys/dev/axgbe/xgbe-mdio.c

1330

pdata->phy.speed = SPEED_1000;

sys/dev/axgbe/xgbe-mdio.c

1333

pdata->phy.speed = SPEED_2500;

sys/dev/axgbe/xgbe-mdio.c

1337

pdata->phy.speed = SPEED_10000;

sys/dev/axgbe/xgbe-mdio.c

1342

pdata->phy.speed = SPEED_UNKNOWN;

sys/dev/axgbe/xgbe-mdio.c

1345

pdata->phy.duplex = DUPLEX_FULL;

sys/dev/axgbe/xgbe-mdio.c

1346

axgbe_printf(2, "%s: speed %d duplex %d\n", __func__, pdata->phy.speed,

sys/dev/axgbe/xgbe-mdio.c

1347

pdata->phy.duplex);

sys/dev/axgbe/xgbe-mdio.c

1361

pdata->phy.link = 0;

sys/dev/axgbe/xgbe-mdio.c

1366

link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);

sys/dev/axgbe/xgbe-mdio.c

1372

pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata,

sys/dev/axgbe/xgbe-mdio.c

1376

pdata->phy.link, an_restart, link_aneg);

sys/dev/axgbe/xgbe-mdio.c

1383

if (pdata->phy.link) {

sys/dev/axgbe/xgbe-mdio.c

1414

axgbe_printf(2, "%s: Link %d\n", __func__, pdata->phy.link);

sys/dev/axgbe/xgbe-mdio.c

1434

pdata->phy.link = 0;

sys/dev/axgbe/xgbe-mdio.c

1530

if (XGBE_ADV(&pdata->phy, 10000baseKR_Full))

sys/dev/axgbe/xgbe-mdio.c

1532

else if (XGBE_ADV(&pdata->phy, 10000baseT_Full))

sys/dev/axgbe/xgbe-mdio.c

1534

else if (XGBE_ADV(&pdata->phy, 2500baseX_Full))

sys/dev/axgbe/xgbe-mdio.c

1536

else if (XGBE_ADV(&pdata->phy, 2500baseT_Full))

sys/dev/axgbe/xgbe-mdio.c

1538

else if (XGBE_ADV(&pdata->phy, 1000baseKX_Full))

sys/dev/axgbe/xgbe-mdio.c

1540

else if (XGBE_ADV(&pdata->phy, 1000baseT_Full))

sys/dev/axgbe/xgbe-mdio.c

1542

else if (XGBE_ADV(&pdata->phy, 100baseT_Full))

sys/dev/axgbe/xgbe-mdio.c

1576

XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);

sys/dev/axgbe/xgbe-mdio.c

1578

pdata->phy.address = 0;

sys/dev/axgbe/xgbe-mdio.c

1580

if (XGBE_ADV(&pdata->phy, Autoneg)) {

sys/dev/axgbe/xgbe-mdio.c

1581

pdata->phy.autoneg = AUTONEG_ENABLE;

sys/dev/axgbe/xgbe-mdio.c

1582

pdata->phy.speed = SPEED_UNKNOWN;

sys/dev/axgbe/xgbe-mdio.c

1583

pdata->phy.duplex = DUPLEX_UNKNOWN;

sys/dev/axgbe/xgbe-mdio.c

1585

pdata->phy.autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/xgbe-mdio.c

1586

pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata);

sys/dev/axgbe/xgbe-mdio.c

1587

pdata->phy.duplex = DUPLEX_FULL;

sys/dev/axgbe/xgbe-mdio.c

1591

pdata->phy.link = 0;

sys/dev/axgbe/xgbe-mdio.c

1593

pdata->phy.pause_autoneg = pdata->pause_autoneg;

sys/dev/axgbe/xgbe-mdio.c

1594

pdata->phy.tx_pause = pdata->tx_pause;

sys/dev/axgbe/xgbe-mdio.c

1595

pdata->phy.rx_pause = pdata->rx_pause;

sys/dev/axgbe/xgbe-mdio.c

1598

XGBE_CLR_ADV(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-mdio.c

1599

XGBE_CLR_ADV(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-mdio.c

1602

XGBE_SET_ADV(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-mdio.c

1603

XGBE_SET_ADV(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-mdio.c

1607

if (XGBE_ADV(&pdata->phy, Asym_Pause))

sys/dev/axgbe/xgbe-mdio.c

1608

XGBE_CLR_ADV(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-mdio.c

1610

XGBE_SET_ADV(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-mdio.c

600

if (!(XGBE_ADV(&pdata->phy, 1000baseKX_Full)) &&

sys/dev/axgbe/xgbe-mdio.c

601

!(XGBE_ADV(&pdata->phy, 2500baseX_Full)))

sys/dev/axgbe/xgbe-mdio.c

609

if (!(XGBE_ADV(&pdata->phy, 10000baseKR_Full)))

sys/dev/axgbe/xgbe-phy-v1.c

155

XGBE_SET_LP_ADV(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v1.c

156

XGBE_SET_LP_ADV(&pdata->phy, Backplane);

sys/dev/axgbe/xgbe-phy-v1.c

162

XGBE_SET_LP_ADV(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v1.c

164

XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v1.c

167

__func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);

sys/dev/axgbe/xgbe-phy-v1.c

169

if (pdata->phy.pause_autoneg) {

sys/dev/axgbe/xgbe-phy-v1.c

171

pdata->phy.tx_pause = 0;

sys/dev/axgbe/xgbe-phy-v1.c

172

pdata->phy.rx_pause = 0;

sys/dev/axgbe/xgbe-phy-v1.c

175

pdata->phy.tx_pause = 1;

sys/dev/axgbe/xgbe-phy-v1.c

176

pdata->phy.rx_pause = 1;

sys/dev/axgbe/xgbe-phy-v1.c

179

pdata->phy.rx_pause = 1;

sys/dev/axgbe/xgbe-phy-v1.c

181

pdata->phy.tx_pause = 1;

sys/dev/axgbe/xgbe-phy-v1.c

189

XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);

sys/dev/axgbe/xgbe-phy-v1.c

192

XGBE_SET_LP_ADV(&pdata->phy, 2500baseX_Full);

sys/dev/axgbe/xgbe-phy-v1.c

194

XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);

sys/dev/axgbe/xgbe-phy-v1.c

199

pdata->phy.speed = SPEED_10000;

sys/dev/axgbe/xgbe-phy-v1.c

204

pdata->phy.speed = SPEED_1000;

sys/dev/axgbe/xgbe-phy-v1.c

209

pdata->phy.speed = SPEED_2500;

sys/dev/axgbe/xgbe-phy-v1.c

215

pdata->phy.speed = SPEED_UNKNOWN;

sys/dev/axgbe/xgbe-phy-v1.c

222

XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);

sys/dev/axgbe/xgbe-phy-v1.c

230

XGBE_LM_COPY(dphy, advertising, &pdata->phy, advertising);

sys/dev/axgbe/xgbe-phy-v1.c

511

switch (pdata->phy.speed) {

sys/dev/axgbe/xgbe-phy-v1.c

531

if (pdata->phy.autoneg == AUTONEG_ENABLE)

sys/dev/axgbe/xgbe-phy-v1.c

536

cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);

sys/dev/axgbe/xgbe-phy-v1.c

551

XGBE_ADV(&pdata->phy, 1000baseKX_Full)));

sys/dev/axgbe/xgbe-phy-v1.c

554

XGBE_ADV(&pdata->phy, 2500baseX_Full)));

sys/dev/axgbe/xgbe-phy-v1.c

557

XGBE_ADV(&pdata->phy, 10000baseKR_Full)));

sys/dev/axgbe/xgbe-phy-v1.c

649

XGBE_ZERO_SUP(&pdata->phy);

sys/dev/axgbe/xgbe-phy-v1.c

650

XGBE_SET_SUP(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v1.c

651

XGBE_SET_SUP(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v1.c

652

XGBE_SET_SUP(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v1.c

653

XGBE_SET_SUP(&pdata->phy, Backplane);

sys/dev/axgbe/xgbe-phy-v1.c

654

XGBE_SET_SUP(&pdata->phy, 10000baseKR_Full);

sys/dev/axgbe/xgbe-phy-v1.c

657

XGBE_SET_SUP(&pdata->phy, 1000baseKX_Full);

sys/dev/axgbe/xgbe-phy-v1.c

660

XGBE_SET_SUP(&pdata->phy, 2500baseX_Full);

sys/dev/axgbe/xgbe-phy-v1.c

665

XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);

sys/dev/axgbe/xgbe-phy-v2.c

1689

"pause_autoneg: 0x%x\n", __func__, pdata->phy.speed,

sys/dev/axgbe/xgbe-phy-v2.c

1690

pdata->phy.duplex, pdata->phy.autoneg, pdata->phy.pause_autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

1782

pdata->phy.tx_pause = 0;

sys/dev/axgbe/xgbe-phy-v2.c

1783

pdata->phy.rx_pause = 0;

sys/dev/axgbe/xgbe-phy-v2.c

1788

if (pdata->phy.pause)

sys/dev/axgbe/xgbe-phy-v2.c

1789

XGBE_SET_LP_ADV(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v2.c

1791

if (pdata->phy.asym_pause)

sys/dev/axgbe/xgbe-phy-v2.c

1792

XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v2.c

1795

pdata->phy.tx_pause, pdata->phy.rx_pause);

sys/dev/axgbe/xgbe-phy-v2.c

1803

XGBE_SET_LP_ADV(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

1804

XGBE_SET_LP_ADV(&pdata->phy, TP);

sys/dev/axgbe/xgbe-phy-v2.c

1807

pdata->phy.pause_autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

1810

if (pdata->phy.pause_autoneg)

sys/dev/axgbe/xgbe-phy-v2.c

1816

XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Full);

sys/dev/axgbe/xgbe-phy-v2.c

1820

XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Half);

sys/dev/axgbe/xgbe-phy-v2.c

1828

XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Full);

sys/dev/axgbe/xgbe-phy-v2.c

1832

XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Half);

sys/dev/axgbe/xgbe-phy-v2.c

1847

XGBE_SET_LP_ADV(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

1848

XGBE_SET_LP_ADV(&pdata->phy, FIBRE);

sys/dev/axgbe/xgbe-phy-v2.c

1854

XGBE_SET_LP_ADV(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v2.c

1856

XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v2.c

1859

__func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);

sys/dev/axgbe/xgbe-phy-v2.c

1861

if (pdata->phy.pause_autoneg) {

sys/dev/axgbe/xgbe-phy-v2.c

1863

pdata->phy.tx_pause = 0;

sys/dev/axgbe/xgbe-phy-v2.c

1864

pdata->phy.rx_pause = 0;

sys/dev/axgbe/xgbe-phy-v2.c

1867

pdata->phy.tx_pause = 1;

sys/dev/axgbe/xgbe-phy-v2.c

1868

pdata->phy.rx_pause = 1;

sys/dev/axgbe/xgbe-phy-v2.c

1871

pdata->phy.rx_pause = 1;

sys/dev/axgbe/xgbe-phy-v2.c

1873

pdata->phy.tx_pause = 1;

sys/dev/axgbe/xgbe-phy-v2.c

1877

axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause,

sys/dev/axgbe/xgbe-phy-v2.c

1878

pdata->phy.rx_pause);

sys/dev/axgbe/xgbe-phy-v2.c

1881

XGBE_SET_LP_ADV(&pdata->phy, 1000baseX_Full);

sys/dev/axgbe/xgbe-phy-v2.c

1897

XGBE_SET_LP_ADV(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

1898

XGBE_SET_LP_ADV(&pdata->phy, Backplane);

sys/dev/axgbe/xgbe-phy-v2.c

1901

pdata->phy.pause_autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

1904

if (pdata->phy.pause_autoneg)

sys/dev/axgbe/xgbe-phy-v2.c

1911

XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);

sys/dev/axgbe/xgbe-phy-v2.c

1913

XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);

sys/dev/axgbe/xgbe-phy-v2.c

1937

(pdata->phy.speed == SPEED_100))

sys/dev/axgbe/xgbe-phy-v2.c

1952

(pdata->phy.speed == SPEED_100))

sys/dev/axgbe/xgbe-phy-v2.c

1966

XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);

sys/dev/axgbe/xgbe-phy-v2.c

1977

XGBE_SET_LP_ADV(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

1978

XGBE_SET_LP_ADV(&pdata->phy, Backplane);

sys/dev/axgbe/xgbe-phy-v2.c

1984

XGBE_SET_LP_ADV(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v2.c

1986

XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v2.c

1989

__func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);

sys/dev/axgbe/xgbe-phy-v2.c

1991

if (pdata->phy.pause_autoneg) {

sys/dev/axgbe/xgbe-phy-v2.c

1993

pdata->phy.tx_pause = 0;

sys/dev/axgbe/xgbe-phy-v2.c

1994

pdata->phy.rx_pause = 0;

sys/dev/axgbe/xgbe-phy-v2.c

1997

pdata->phy.tx_pause = 1;

sys/dev/axgbe/xgbe-phy-v2.c

1998

pdata->phy.rx_pause = 1;

sys/dev/axgbe/xgbe-phy-v2.c

2001

pdata->phy.rx_pause = 1;

sys/dev/axgbe/xgbe-phy-v2.c

2003

pdata->phy.tx_pause = 1;

sys/dev/axgbe/xgbe-phy-v2.c

2007

axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause,

sys/dev/axgbe/xgbe-phy-v2.c

2008

pdata->phy.rx_pause);

sys/dev/axgbe/xgbe-phy-v2.c

2014

XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);

sys/dev/axgbe/xgbe-phy-v2.c

2016

XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);

sys/dev/axgbe/xgbe-phy-v2.c

2030

XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);

sys/dev/axgbe/xgbe-phy-v2.c

2057

XGBE_LM_COPY(dphy, advertising, &pdata->phy, advertising);

sys/dev/axgbe/xgbe-phy-v2.c

2085

(pdata->phy.speed == SPEED_10000))

sys/dev/axgbe/xgbe-phy-v2.c

2652

switch (pdata->phy.speed) {

sys/dev/axgbe/xgbe-phy-v2.c

2707

if (pdata->phy.autoneg == AUTONEG_ENABLE)

sys/dev/axgbe/xgbe-phy-v2.c

2712

cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);

sys/dev/axgbe/xgbe-phy-v2.c

2726

return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,

sys/dev/axgbe/xgbe-phy-v2.c

2729

return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,

sys/dev/axgbe/xgbe-phy-v2.c

2743

return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,

sys/dev/axgbe/xgbe-phy-v2.c

2746

return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,

sys/dev/axgbe/xgbe-phy-v2.c

2749

return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,

sys/dev/axgbe/xgbe-phy-v2.c

2752

return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,

sys/dev/axgbe/xgbe-phy-v2.c

2769

XGBE_ADV(&pdata->phy, 1000baseX_Full)));

sys/dev/axgbe/xgbe-phy-v2.c

2774

XGBE_ADV(&pdata->phy, 100baseT_Full)));

sys/dev/axgbe/xgbe-phy-v2.c

2779

XGBE_ADV(&pdata->phy, 1000baseT_Full)));

sys/dev/axgbe/xgbe-phy-v2.c

2784

XGBE_ADV(&pdata->phy, 10000baseSR_Full) ||

sys/dev/axgbe/xgbe-phy-v2.c

2785

XGBE_ADV(&pdata->phy, 10000baseLR_Full) ||

sys/dev/axgbe/xgbe-phy-v2.c

2786

XGBE_ADV(&pdata->phy, 10000baseLRM_Full) ||

sys/dev/axgbe/xgbe-phy-v2.c

2787

XGBE_ADV(&pdata->phy, 10000baseER_Full) ||

sys/dev/axgbe/xgbe-phy-v2.c

2788

XGBE_ADV(&pdata->phy, 10000baseCR_Full)));

sys/dev/axgbe/xgbe-phy-v2.c

2801

XGBE_ADV(&pdata->phy, 2500baseX_Full)));

sys/dev/axgbe/xgbe-phy-v2.c

2814

XGBE_ADV(&pdata->phy, 1000baseKX_Full)));

sys/dev/axgbe/xgbe-phy-v2.c

2817

XGBE_ADV(&pdata->phy, 10000baseKR_Full)));

sys/dev/axgbe/xgbe-phy-v2.c

2952

axgbe_printf(2, "%s: Link %d\n", __func__, pdata->phy.link);

sys/dev/axgbe/xgbe-phy-v2.c

2959

pdata->phy.link = 0;

sys/dev/axgbe/xgbe-phy-v2.c

2961

pdata->phy.link = 1;

sys/dev/axgbe/xgbe-phy-v2.c

2963

axgbe_printf(2, "Link: %d updated reg %#x\n", pdata->phy.link, reg);

sys/dev/axgbe/xgbe-phy-v2.c

2982

if (AUTONEG_ENABLE == pdata->phy.autoneg) {

sys/dev/axgbe/xgbe-phy-v2.c

2983

if (pdata->phy.supported == SUPPORTED_1000baseT_Half ||

sys/dev/axgbe/xgbe-phy-v2.c

2984

pdata->phy.supported == SUPPORTED_1000baseT_Full) {

sys/dev/axgbe/xgbe-phy-v2.c

3004

if (pdata->phy.supported == SUPPORTED_1000baseT_Half)

sys/dev/axgbe/xgbe-phy-v2.c

3005

XGBE_SET_ADV(&pdata->phy, 1000baseT_Half);

sys/dev/axgbe/xgbe-phy-v2.c

3006

else if (pdata->phy.supported == SUPPORTED_1000baseT_Full)

sys/dev/axgbe/xgbe-phy-v2.c

3007

XGBE_SET_ADV(&pdata->phy, 1000baseT_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3016

if (pdata->phy.supported == SUPPORTED_Autoneg)

sys/dev/axgbe/xgbe-phy-v2.c

3017

XGBE_SET_ADV(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

3025

pdata->phy.speed = SPEED_10;

sys/dev/axgbe/xgbe-phy-v2.c

3026

pdata->phy.duplex = DUPLEX_HALF;

sys/dev/axgbe/xgbe-phy-v2.c

3027

pdata->phy.pause = 0;

sys/dev/axgbe/xgbe-phy-v2.c

3028

pdata->phy.asym_pause = 0;

sys/dev/axgbe/xgbe-phy-v2.c

3035

pdata->phy.speed = SPEED_1000;

sys/dev/axgbe/xgbe-phy-v2.c

3038

pdata->phy.duplex = DUPLEX_FULL;

sys/dev/axgbe/xgbe-phy-v2.c

3041

pdata->phy.speed = SPEED_100;

sys/dev/axgbe/xgbe-phy-v2.c

3044

pdata->phy.duplex = DUPLEX_FULL;

sys/dev/axgbe/xgbe-phy-v2.c

3047

pdata->phy.duplex = DUPLEX_FULL;

sys/dev/axgbe/xgbe-phy-v2.c

3049

if (pdata->phy.duplex == DUPLEX_FULL) {

sys/dev/axgbe/xgbe-phy-v2.c

3050

pdata->phy.pause = lpa & ANLPAR_FC ? 1 : 0;

sys/dev/axgbe/xgbe-phy-v2.c

3051

pdata->phy.asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;

sys/dev/axgbe/xgbe-phy-v2.c

3059

pdata->phy.duplex = DUPLEX_FULL;

sys/dev/axgbe/xgbe-phy-v2.c

3061

pdata->phy.duplex = DUPLEX_HALF;

sys/dev/axgbe/xgbe-phy-v2.c

3064

pdata->phy.speed = SPEED_1000;

sys/dev/axgbe/xgbe-phy-v2.c

3066

pdata->phy.speed = SPEED_100;

sys/dev/axgbe/xgbe-phy-v2.c

3068

pdata->phy.speed = SPEED_10;

sys/dev/axgbe/xgbe-phy-v2.c

3070

pdata->phy.pause = 0;

sys/dev/axgbe/xgbe-phy-v2.c

3071

pdata->phy.asym_pause = 0;

sys/dev/axgbe/xgbe-phy-v2.c

3073

"autoneg %#x\n", __func__, pdata->phy.speed,

sys/dev/axgbe/xgbe-phy-v2.c

3074

pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

3149

"autoneg %#x\n", __func__, pdata->phy.speed,

sys/dev/axgbe/xgbe-phy-v2.c

3150

pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

3154

if ((pdata->phy.autoneg == AUTONEG_ENABLE) && !ret)

sys/dev/axgbe/xgbe-phy-v2.c

3157

if (pdata->phy.link)

sys/dev/axgbe/xgbe-phy-v2.c

3837

XGBE_ZERO_SUP(&pdata->phy);

sys/dev/axgbe/xgbe-phy-v2.c

3843

XGBE_SET_SUP(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

3844

XGBE_SET_SUP(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3845

XGBE_SET_SUP(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3846

XGBE_SET_SUP(&pdata->phy, Backplane);

sys/dev/axgbe/xgbe-phy-v2.c

3848

XGBE_SET_SUP(&pdata->phy, 1000baseKX_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3852

XGBE_SET_SUP(&pdata->phy, 10000baseKR_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3854

XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);

sys/dev/axgbe/xgbe-phy-v2.c

3861

XGBE_SET_SUP(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3862

XGBE_SET_SUP(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3863

XGBE_SET_SUP(&pdata->phy, Backplane);

sys/dev/axgbe/xgbe-phy-v2.c

3864

XGBE_SET_SUP(&pdata->phy, 2500baseX_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3872

XGBE_SET_SUP(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

3873

XGBE_SET_SUP(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3874

XGBE_SET_SUP(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3875

XGBE_SET_SUP(&pdata->phy, TP);

sys/dev/axgbe/xgbe-phy-v2.c

3877

XGBE_SET_SUP(&pdata->phy, 100baseT_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3881

XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3890

XGBE_SET_SUP(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

3891

XGBE_SET_SUP(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3892

XGBE_SET_SUP(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3893

XGBE_SET_SUP(&pdata->phy, FIBRE);

sys/dev/axgbe/xgbe-phy-v2.c

3894

XGBE_SET_SUP(&pdata->phy, 1000baseX_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3902

XGBE_SET_SUP(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

3903

XGBE_SET_SUP(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3904

XGBE_SET_SUP(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3905

XGBE_SET_SUP(&pdata->phy, TP);

sys/dev/axgbe/xgbe-phy-v2.c

3907

XGBE_SET_SUP(&pdata->phy, 100baseT_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3911

XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3915

XGBE_SET_SUP(&pdata->phy, 2500baseT_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3924

XGBE_SET_SUP(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

3925

XGBE_SET_SUP(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3926

XGBE_SET_SUP(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3927

XGBE_SET_SUP(&pdata->phy, TP);

sys/dev/axgbe/xgbe-phy-v2.c

3929

XGBE_SET_SUP(&pdata->phy, 100baseT_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3933

XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3937

XGBE_SET_SUP(&pdata->phy, 10000baseT_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3946

XGBE_SET_SUP(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

3947

XGBE_SET_SUP(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3948

XGBE_SET_SUP(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3949

XGBE_SET_SUP(&pdata->phy, FIBRE);

sys/dev/axgbe/xgbe-phy-v2.c

3950

XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3951

XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3952

XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3953

XGBE_SET_SUP(&pdata->phy, 10000baseER_Full);

sys/dev/axgbe/xgbe-phy-v2.c

3955

XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);

sys/dev/axgbe/xgbe-phy-v2.c

3963

XGBE_SET_SUP(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

3964

XGBE_SET_SUP(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3965

XGBE_SET_SUP(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v2.c

3966

XGBE_SET_SUP(&pdata->phy, TP);

sys/dev/axgbe/xgbe-phy-v2.c

3967

XGBE_SET_SUP(&pdata->phy, FIBRE);

sys/dev/axgbe/xgbe-phy-v2.c

3980

pdata->phy.advertising);

sys/dev/axgbe/xgbe-phy-v2.c

3987

phy_data->start_mode, phy_data->phydev_mode, pdata->phy.advertising);

sys/dev/axgbe/xgbe-phy-v2.c

779

XGBE_ZERO_SUP(&pdata->phy);

sys/dev/axgbe/xgbe-phy-v2.c

782

pdata->phy.speed = SPEED_UNKNOWN;

sys/dev/axgbe/xgbe-phy-v2.c

783

pdata->phy.duplex = DUPLEX_UNKNOWN;

sys/dev/axgbe/xgbe-phy-v2.c

784

pdata->phy.autoneg = AUTONEG_ENABLE;

sys/dev/axgbe/xgbe-phy-v2.c

785

pdata->phy.pause_autoneg = AUTONEG_ENABLE;

sys/dev/axgbe/xgbe-phy-v2.c

787

XGBE_SET_SUP(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

788

XGBE_SET_SUP(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v2.c

789

XGBE_SET_SUP(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v2.c

790

XGBE_SET_SUP(&pdata->phy, TP);

sys/dev/axgbe/xgbe-phy-v2.c

791

XGBE_SET_SUP(&pdata->phy, FIBRE);

sys/dev/axgbe/xgbe-phy-v2.c

793

XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);

sys/dev/axgbe/xgbe-phy-v2.c

802

pdata->phy.speed = SPEED_100;

sys/dev/axgbe/xgbe-phy-v2.c

803

pdata->phy.duplex = DUPLEX_FULL;

sys/dev/axgbe/xgbe-phy-v2.c

804

pdata->phy.autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/xgbe-phy-v2.c

805

pdata->phy.pause_autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/xgbe-phy-v2.c

811

pdata->phy.speed = SPEED_UNKNOWN;

sys/dev/axgbe/xgbe-phy-v2.c

812

pdata->phy.duplex = DUPLEX_UNKNOWN;

sys/dev/axgbe/xgbe-phy-v2.c

813

pdata->phy.autoneg = AUTONEG_ENABLE;

sys/dev/axgbe/xgbe-phy-v2.c

814

pdata->phy.pause_autoneg = AUTONEG_ENABLE;

sys/dev/axgbe/xgbe-phy-v2.c

815

XGBE_SET_SUP(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-phy-v2.c

816

XGBE_SET_SUP(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-phy-v2.c

817

XGBE_SET_SUP(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-phy-v2.c

820

XGBE_SET_SUP(&pdata->phy, 100baseT_Full);

sys/dev/axgbe/xgbe-phy-v2.c

822

XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);

sys/dev/axgbe/xgbe-phy-v2.c

825

XGBE_SET_SUP(&pdata->phy, 1000baseX_Full);

sys/dev/axgbe/xgbe-phy-v2.c

830

pdata->phy.speed = SPEED_1000;

sys/dev/axgbe/xgbe-phy-v2.c

831

pdata->phy.duplex = DUPLEX_FULL;

sys/dev/axgbe/xgbe-phy-v2.c

832

pdata->phy.autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/xgbe-phy-v2.c

833

pdata->phy.pause_autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/xgbe-phy-v2.c

840

pdata->phy.speed = SPEED_10000;

sys/dev/axgbe/xgbe-phy-v2.c

841

pdata->phy.duplex = DUPLEX_FULL;

sys/dev/axgbe/xgbe-phy-v2.c

842

pdata->phy.autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/xgbe-phy-v2.c

843

pdata->phy.pause_autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/xgbe-phy-v2.c

847

XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full);

sys/dev/axgbe/xgbe-phy-v2.c

850

XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full);

sys/dev/axgbe/xgbe-phy-v2.c

853

XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full);

sys/dev/axgbe/xgbe-phy-v2.c

856

XGBE_SET_SUP(&pdata->phy, 10000baseER_Full);

sys/dev/axgbe/xgbe-phy-v2.c

859

XGBE_SET_SUP(&pdata->phy, 10000baseCR_Full);

sys/dev/axgbe/xgbe-phy-v2.c

867

pdata->phy.speed = SPEED_UNKNOWN;

sys/dev/axgbe/xgbe-phy-v2.c

868

pdata->phy.duplex = DUPLEX_UNKNOWN;

sys/dev/axgbe/xgbe-phy-v2.c

869

pdata->phy.autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/xgbe-phy-v2.c

870

pdata->phy.pause_autoneg = AUTONEG_DISABLE;

sys/dev/axgbe/xgbe-phy-v2.c

878

XGBE_SET_SUP(&pdata->phy, TP);

sys/dev/axgbe/xgbe-phy-v2.c

881

XGBE_SET_SUP(&pdata->phy, FIBRE);

sys/dev/axgbe/xgbe-phy-v2.c

885

XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);

sys/dev/axgbe/xgbe-phy-v2.c

888

"advert 0x%x support 0x%x\n", __func__, pdata->phy.speed,

sys/dev/axgbe/xgbe-phy-v2.c

889

phy_data->sfp_base, pdata->phy.pause_autoneg,

sys/dev/axgbe/xgbe-phy-v2.c

890

pdata->phy.advertising, pdata->phy.supported);

sys/dev/axgbe/xgbe-sysctl.c

571

sbuf_printf(sb, "\nLink is %s", pdata->phy.link ? "Up" : "Down");

sys/dev/axgbe/xgbe-sysctl.c

757

sys_op->autoneg = pdata->phy.pause_autoneg;

sys/dev/axgbe/xgbe-sysctl.c

758

sys_op->tx_pause = pdata->phy.tx_pause;

sys/dev/axgbe/xgbe-sysctl.c

759

sys_op->rx_pause = pdata->phy.rx_pause;

sys/dev/axgbe/xgbe-sysctl.c

769

if (pdata->phy.lp_advertising) {

sys/dev/axgbe/xgbe-sysctl.c

772

if (pdata->phy.advertising & pdata->phy.lp_advertising &

sys/dev/axgbe/xgbe-sysctl.c

776

} else if (pdata->phy.advertising &

sys/dev/axgbe/xgbe-sysctl.c

777

pdata->phy.lp_advertising & ADVERTISED_Asym_Pause) {

sys/dev/axgbe/xgbe-sysctl.c

778

if (pdata->phy.advertising & ADVERTISED_Pause)

sys/dev/axgbe/xgbe-sysctl.c

780

else if (pdata->phy.lp_advertising &

sys/dev/axgbe/xgbe-sysctl.c

800

if (sys_op->autoneg && (pdata->phy.autoneg != AUTONEG_ENABLE)) {

sys/dev/axgbe/xgbe-sysctl.c

805

pdata->phy.pause_autoneg = sys_op->autoneg;

sys/dev/axgbe/xgbe-sysctl.c

806

pdata->phy.tx_pause = sys_op->tx_pause;

sys/dev/axgbe/xgbe-sysctl.c

807

pdata->phy.rx_pause = sys_op->rx_pause;

sys/dev/axgbe/xgbe-sysctl.c

809

XGBE_CLR_ADV(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-sysctl.c

810

XGBE_CLR_ADV(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-sysctl.c

813

XGBE_SET_ADV(&pdata->phy, Pause);

sys/dev/axgbe/xgbe-sysctl.c

814

XGBE_SET_ADV(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-sysctl.c

819

if (XGBE_ADV(&pdata->phy, Asym_Pause))

sys/dev/axgbe/xgbe-sysctl.c

820

XGBE_CLR_ADV(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-sysctl.c

822

XGBE_SET_ADV(&pdata->phy, Asym_Pause);

sys/dev/axgbe/xgbe-sysctl.c

855

sys_op->autoneg = pdata->phy.autoneg;

sys/dev/axgbe/xgbe-sysctl.c

856

sys_op->speed = pdata->phy.speed;

sys/dev/axgbe/xgbe-sysctl.c

857

sys_op->duplex = pdata->phy.duplex;

sys/dev/axgbe/xgbe-sysctl.c

859

XGBE_LM_COPY(&pdata->phy, supported, &pdata->phy, supported);

sys/dev/axgbe/xgbe-sysctl.c

860

XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, advertising);

sys/dev/axgbe/xgbe-sysctl.c

861

XGBE_LM_COPY(&pdata->phy, lp_advertising, &pdata->phy, lp_advertising);

sys/dev/axgbe/xgbe-sysctl.c

941

pdata->phy.autoneg = sys_op->autoneg;

sys/dev/axgbe/xgbe-sysctl.c

942

pdata->phy.speed = speed;

sys/dev/axgbe/xgbe-sysctl.c

943

pdata->phy.duplex = sys_op->duplex;

sys/dev/axgbe/xgbe-sysctl.c

946

XGBE_SET_ADV(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe-sysctl.c

948

XGBE_CLR_ADV(&pdata->phy, Autoneg);

sys/dev/axgbe/xgbe.h

1222

struct xgbe_phy phy;

sys/dev/bce/if_bce.c

1823

bce_miibus_read_reg(device_t dev, int phy, int reg)

sys/dev/bce/if_bce.c

1851

val = BCE_MIPHY(phy) | BCE_MIREG(reg) |

sys/dev/bce/if_bce.c

1872

"reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);

sys/dev/bce/if_bce.c

1901

bce_miibus_write_reg(device_t dev, int phy, int reg, int val)

sys/dev/bce/if_bce.c

1931

val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |

sys/dev/bce/if_bcereg.h

433

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

437

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

441

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

445

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

449

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

453

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

457

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

461

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

465

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); \

sys/dev/bfe/if_bfe.c

615

bfe_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/bfe/if_bfe.c

627

bfe_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/bge/if_bge.c

1094

bge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/bge/if_bge.c

1113

BGE_MIPHY(phy) | BGE_MIREG(reg));

sys/dev/bge/if_bge.c

1129

phy, reg, val);

sys/dev/bge/if_bge.c

1148

bge_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/bge/if_bge.c

1170

BGE_MIPHY(phy) | BGE_MIREG(reg) | val);

sys/dev/bge/if_bge.c

1192

phy, reg, val);

sys/dev/bhnd/cores/pci/bhnd_pci.c

371

bhnd_pcie_mdio_read(struct bhnd_pci_softc *sc, int phy, int reg)

sys/dev/bhnd/cores/pci/bhnd_pci.c

382

cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg);

sys/dev/bhnd/cores/pci/bhnd_pci.c

396

bhnd_pcie_mdio_write(struct bhnd_pci_softc *sc, int phy, int reg, int val)

sys/dev/bhnd/cores/pci/bhnd_pci.c

406

cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg) | (val & BHND_PCIE_MDIODATA_DATA_MASK);

sys/dev/bhnd/cores/pci/bhnd_pci.c

417

bhnd_pcie_mdio_read_ext(struct bhnd_pci_softc *sc, int phy, int devaddr,

sys/dev/bhnd/cores/pci/bhnd_pci.c

425

return (bhnd_pcie_mdio_read(sc, phy, reg));

sys/dev/bhnd/cores/pci/bhnd_pci.c

430

phy != BHND_PCIE_PHYADDR_SD)

sys/dev/bhnd/cores/pci/bhnd_pci.c

440

cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | devaddr;

sys/dev/bhnd/cores/pci/bhnd_pci.c

445

cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg);

sys/dev/bhnd/cores/pci/bhnd_pci.c

459

bhnd_pcie_mdio_write_ext(struct bhnd_pci_softc *sc, int phy, int devaddr,

sys/dev/bhnd/cores/pci/bhnd_pci.c

466

return (bhnd_pcie_mdio_write(sc, phy, reg, val));

sys/dev/bhnd/cores/pci/bhnd_pci.c

471

phy != BHND_PCIE_PHYADDR_SD)

sys/dev/bhnd/cores/pci/bhnd_pci.c

481

cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | devaddr;

sys/dev/bhnd/cores/pci/bhnd_pci.c

486

cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg) |

sys/dev/bhnd/cores/pci/bhnd_pcivar.h

56

int bhnd_pcie_mdio_read(struct bhnd_pci_softc *sc, int phy,

sys/dev/bhnd/cores/pci/bhnd_pcivar.h

58

int bhnd_pcie_mdio_write(struct bhnd_pci_softc *sc, int phy,

sys/dev/bhnd/cores/pci/bhnd_pcivar.h

60

int bhnd_pcie_mdio_read_ext(struct bhnd_pci_softc *sc, int phy,

sys/dev/bhnd/cores/pci/bhnd_pcivar.h

62

int bhnd_pcie_mdio_write_ext(struct bhnd_pci_softc *sc, int phy,

sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c

222

bhnd_pcie2_mdio_read(struct bhnd_pcie2_softc *sc, int phy, int reg)

sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c

229

bhnd_pcie2_mdio_write(struct bhnd_pcie2_softc *sc, int phy, int reg, int val)

sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c

236

bhnd_pcie2_mdio_read_ext(struct bhnd_pcie2_softc *sc, int phy, int devaddr,

sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c

244

bhnd_pcie2_mdio_write_ext(struct bhnd_pcie2_softc *sc, int phy, int devaddr,

sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h

56

int bhnd_pcie2_mdio_read(struct bhnd_pcie2_softc *sc, int phy,

sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h

58

int bhnd_pcie2_mdio_write(struct bhnd_pcie2_softc *sc, int phy,

sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h

60

int bhnd_pcie2_mdio_read_ext(struct bhnd_pcie2_softc *sc, int phy,

sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h

63

int phy, int devaddr, int reg, int val);

sys/dev/bwi/bwimac.c

1308

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwimac.c

1312

if (phy->phy_mode == IEEE80211_MODE_11A)

sys/dev/bwi/bwimac.c

1318

if (phy->phy_mode == IEEE80211_MODE_11G) {

sys/dev/bwi/bwimac.c

1319

if (phy->phy_rev == 1)

sys/dev/bwi/bwimac.c

1323

} else if (phy->phy_mode == IEEE80211_MODE_11B) {

sys/dev/bwi/bwimac.c

1324

if (phy->phy_rev >= 2 && rf->rf_type == BWI_RF_T_BCM2050)

sys/dev/bwi/bwimac.c

1327

panic("unknown PHY mode %u\n", phy->phy_mode);

sys/dev/bwi/bwimac.c

1337

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwimac.c

1364

if (phy->phy_mode == IEEE80211_MODE_11B) {

sys/dev/bwi/bwimac.c

1379

if (phy->phy_mode == IEEE80211_MODE_11B)

sys/dev/bwi/bwimac.c

594

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwimac.c

620

if (phy->phy_mode == IEEE80211_MODE_11A) {

sys/dev/bwi/bwimac.c

646

if (phy->phy_mode == IEEE80211_MODE_11G) {

sys/dev/bwi/bwimac.c

659

if (phy->phy_mode == IEEE80211_MODE_11G) {

sys/dev/bwi/bwimac.c

759

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwimac.c

764

KASSERT(phy->phy_mode != IEEE80211_MODE_11A,

sys/dev/bwi/bwimac.c

765

("phy_mode %d", phy->phy_mode));

sys/dev/bwi/bwimac.c

773

if (phy->phy_mode == IEEE80211_MODE_11G) {

sys/dev/bwi/bwimac.c

774

if ((phy->phy_flags & BWI_PHY_F_LINKED) == 0)

sys/dev/bwi/bwimac.c

781

if (phy->phy_mode == IEEE80211_MODE_11B && phy->phy_rev >= 2 &&

sys/dev/bwi/bwiphy.c

1013

bwi_phy_clear_state(struct bwi_phy *phy)

sys/dev/bwi/bwiphy.c

1015

phy->phy_flags &= ~BWI_CLEAR_PHY_FLAGS;

sys/dev/bwi/bwiphy.c

156

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwiphy.c

180

phy->phy_init = bwi_phy_init_11a;

sys/dev/bwi/bwiphy.c

181

phy->phy_mode = IEEE80211_MODE_11A;

sys/dev/bwi/bwiphy.c

182

phy->phy_tbl_ctrl = BWI_PHYR_TBL_CTRL_11A;

sys/dev/bwi/bwiphy.c

183

phy->phy_tbl_data_lo = BWI_PHYR_TBL_DATA_LO_11A;

sys/dev/bwi/bwiphy.c

184

phy->phy_tbl_data_hi = BWI_PHYR_TBL_DATA_HI_11A;

sys/dev/bwi/bwiphy.c

189

phy->phy_init = bwi_sup_bphy[i].init;

sys/dev/bwi/bwiphy.c

198

phy->phy_mode = IEEE80211_MODE_11B;

sys/dev/bwi/bwiphy.c

206

phy->phy_init = bwi_phy_init_11g;

sys/dev/bwi/bwiphy.c

207

phy->phy_mode = IEEE80211_MODE_11G;

sys/dev/bwi/bwiphy.c

208

phy->phy_tbl_ctrl = BWI_PHYR_TBL_CTRL_11G;

sys/dev/bwi/bwiphy.c

209

phy->phy_tbl_data_lo = BWI_PHYR_TBL_DATA_LO_11G;

sys/dev/bwi/bwiphy.c

210

phy->phy_tbl_data_hi = BWI_PHYR_TBL_DATA_HI_11G;

sys/dev/bwi/bwiphy.c

217

phy->phy_rev = phyrev;

sys/dev/bwi/bwiphy.c

218

phy->phy_version = phyver;

sys/dev/bwi/bwiphy.c

225

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwiphy.c

228

if (phy->phy_version == 0) {

sys/dev/bwi/bwiphy.c

232

if (phy->phy_version > 1)

sys/dev/bwi/bwiphy.c

244

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwiphy.c

250

if (phy->phy_flags & BWI_PHY_F_CALIBRATED)

sys/dev/bwi/bwiphy.c

253

if (phy->phy_mode == IEEE80211_MODE_11G && phy->phy_rev == 1) {

sys/dev/bwi/bwiphy.c

259

phy->phy_flags |= BWI_PHY_F_CALIBRATED;

sys/dev/bwi/bwiphy.c

266

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwiphy.c

268

KASSERT(phy->phy_tbl_ctrl != 0 && phy->phy_tbl_data_lo != 0,

sys/dev/bwi/bwiphy.c

270

phy->phy_tbl_ctrl, phy->phy_tbl_data_lo));

sys/dev/bwi/bwiphy.c

271

PHY_WRITE(mac, phy->phy_tbl_ctrl, ofs);

sys/dev/bwi/bwiphy.c

272

PHY_WRITE(mac, phy->phy_tbl_data_lo, data);

sys/dev/bwi/bwiphy.c

278

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwiphy.c

280

KASSERT(phy->phy_tbl_data_lo != 0 && phy->phy_tbl_data_hi != 0 &&

sys/dev/bwi/bwiphy.c

281

phy->phy_tbl_ctrl != 0,

sys/dev/bwi/bwiphy.c

283

phy->phy_tbl_data_lo, phy->phy_tbl_data_hi, phy->phy_tbl_ctrl));

sys/dev/bwi/bwiphy.c

285

PHY_WRITE(mac, phy->phy_tbl_ctrl, ofs);

sys/dev/bwi/bwiphy.c

286

PHY_WRITE(mac, phy->phy_tbl_data_hi, data >> 16);

sys/dev/bwi/bwiphy.c

287

PHY_WRITE(mac, phy->phy_tbl_data_lo, data & 0xffff);

sys/dev/bwi/bwiphy.c

314

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwiphy.c

318

if (phy->phy_rev == 1)

sys/dev/bwi/bwiphy.c

323

if (phy->phy_rev >= 2 || (phy->phy_flags & BWI_PHY_F_LINKED))

sys/dev/bwi/bwiphy.c

326

if (phy->phy_rev >= 2) {

sys/dev/bwi/bwiphy.c

330

if (phy->phy_rev == 2) {

sys/dev/bwi/bwiphy.c

333

} else if (phy->phy_rev > 5) {

sys/dev/bwi/bwiphy.c

339

if (phy->phy_rev >= 2 || (phy->phy_flags & BWI_PHY_F_LINKED)) {

sys/dev/bwi/bwiphy.c

353

if ((phy->phy_rev <= 2 && (phy->phy_flags & BWI_PHY_F_LINKED)) ||

sys/dev/bwi/bwiphy.c

354

phy->phy_rev >= 2)

sys/dev/bwi/bwiphy.c

362

if (phy->phy_rev >= 2 && (phy->phy_flags & BWI_PHY_F_LINKED))

sys/dev/bwi/bwiphy.c

378

if (phy->phy_rev >= 6) {

sys/dev/bwi/bwiphy.c

388

if (phy->phy_rev < 2)

sys/dev/bwi/bwiphy.c

394

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/bwi/bwiphy.c

402

} else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/bwi/bwiphy.c

507

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwiphy.c

510

if (phy->phy_version == 1)

sys/dev/bwi/bwiphy.c

529

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/bwi/bwiphy.c

548

if (phy->phy_version == 1) {

sys/dev/bwi/bwiphy.c

561

if (phy->phy_version == 1)

sys/dev/bwi/bwiphy.c

566

if (phy->phy_version == 0)

sys/dev/bwi/bwiphy.c

609

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwiphy.c

669

if (phy->phy_mode == IEEE80211_MODE_11G) {

sys/dev/bwi/bwiphy.c

720

if (phy->phy_version == 4) {

sys/dev/bwi/bwiphy.c

727

if (phy->phy_mode == IEEE80211_MODE_11B) {

sys/dev/bwi/bwiphy.c

749

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwiphy.c

754

if (phy->phy_rev == 1) {

sys/dev/bwi/bwiphy.c

781

if (phy->phy_rev == 2) {

sys/dev/bwi/bwiphy.c

784

} else if (phy->phy_rev > 2) {

sys/dev/bwi/bwiphy.c

805

if (phy->phy_rev <= 2) {

sys/dev/bwi/bwiphy.c

808

} else if (phy->phy_rev >= 7 && (PHY_READ(mac, 0x449) & 0x200)) {

sys/dev/bwi/bwiphy.c

821

if (phy->phy_rev == 2) {

sys/dev/bwi/bwiphy.c

824

} else if (phy->phy_rev > 2 && phy->phy_rev <= 8) {

sys/dev/bwi/bwiphy.c

834

if (phy->phy_rev == 1) {

sys/dev/bwi/bwiphy.c

881

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwiphy.c

884

ofs = phy->phy_rev == 1 ? 0x4c00 : 0;

sys/dev/bwi/bwiphy.c

891

if (phy->phy_rev == 1) {

sys/dev/bwi/bwiphy.c

911

if (phy->phy_rev == 1)

sys/dev/bwi/bwiphy.c

924

if (phy->phy_rev == 1) {

sys/dev/bwi/bwiphy.c

932

if (phy->phy_rev >= 6) {

sys/dev/bwi/bwiphy.c

941

if (phy->phy_rev == 1) {

sys/dev/bwi/bwiphy.c

953

if (phy->phy_rev >= 6) {

sys/dev/bwi/bwiphy.c

962

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwiphy.c

966

if (phy->phy_rev <= 1) {

sys/dev/bwi/bwirf.c

1087

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwirf.c

1096

if (phy->phy_mode == IEEE80211_MODE_11A) {

sys/dev/bwi/bwirf.c

1104

phy->phy_mode == IEEE80211_MODE_11G)

sys/dev/bwi/bwirf.c

1120

if (phy->phy_mode == IEEE80211_MODE_11A)

sys/dev/bwi/bwirf.c

1161

if (phy->phy_mode == IEEE80211_MODE_11A)

sys/dev/bwi/bwirf.c

1176

if (phy->phy_mode == IEEE80211_MODE_11A) {

sys/dev/bwi/bwirf.c

1182

if (phy->phy_mode == IEEE80211_MODE_11G) {

sys/dev/bwi/bwirf.c

1212

if (phy->phy_mode == IEEE80211_MODE_11A)

sys/dev/bwi/bwirf.c

1260

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwirf.c

1273

if (phy->phy_flags & BWI_PHY_F_LINKED) {

sys/dev/bwi/bwirf.c

1292

if (phy->phy_flags & BWI_PHY_F_LINKED) {

sys/dev/bwi/bwirf.c

1302

if (phy->phy_flags & BWI_PHY_F_LINKED) {

sys/dev/bwi/bwirf.c

1320

if (phy->phy_flags & BWI_PHY_F_LINKED) {

sys/dev/bwi/bwirf.c

1339

if (phy->phy_flags & BWI_PHY_F_LINKED) {

sys/dev/bwi/bwirf.c

1355

if (phy->phy_flags & BWI_PHY_F_LINKED)

sys/dev/bwi/bwirf.c

1376

if (phy->phy_flags & BWI_PHY_F_LINKED) {

sys/dev/bwi/bwirf.c

1391

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwirf.c

1395

if (phy->phy_flags & BWI_PHY_F_LINKED)

sys/dev/bwi/bwirf.c

1399

if (phy->phy_flags & BWI_PHY_F_LINKED) {

sys/dev/bwi/bwirf.c

1647

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwirf.c

1669

if (phy->phy_rev >= 5)

sys/dev/bwi/bwirf.c

1688

if (phy->phy_version >= 2)

sys/dev/bwi/bwirf.c

1690

else if (phy->phy_version == 0)

sys/dev/bwi/bwirf.c

1722

if (phy->phy_version != 0)

sys/dev/bwi/bwirf.c

1766

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwirf.c

1785

if (phy->phy_rev >= 6) {

sys/dev/bwi/bwirf.c

1829

if (phy->phy_version == 0)

sys/dev/bwi/bwirf.c

1867

if (phy->phy_rev >= 6) {

sys/dev/bwi/bwirf.c

1886

if (phy->phy_rev >= 6) {

sys/dev/bwi/bwirf.c

1919

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwirf.c

1951

if (phy->phy_rev >= 3) {

sys/dev/bwi/bwirf.c

1958

if (phy->phy_rev == 4 || phy->phy_rev == 6 ||

sys/dev/bwi/bwirf.c

1959

phy->phy_rev == 7) {

sys/dev/bwi/bwirf.c

1962

} else if (phy->phy_rev == 3 || phy->phy_rev == 5) {

sys/dev/bwi/bwirf.c

1982

if (phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

1995

if (phy->phy_version >= 2)

sys/dev/bwi/bwirf.c

2001

if (phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

2040

if (phy->phy_rev >= 3) {

sys/dev/bwi/bwirf.c

2046

if (phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

2066

if (phy->phy_rev >= 3) {

sys/dev/bwi/bwirf.c

2277

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwirf.c

228

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwirf.c

2281

if (phy->phy_flags & BWI_PHY_F_LINKED)

sys/dev/bwi/bwirf.c

2293

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwirf.c

2302

if (phy->phy_mode == IEEE80211_MODE_11B) {

sys/dev/bwi/bwirf.c

2318

if (phy->phy_mode == IEEE80211_MODE_11A) {

sys/dev/bwi/bwirf.c

2326

if (phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

2329

if (phy->phy_rev == 2) {

sys/dev/bwi/bwirf.c

2336

if (phy->phy_rev >= 6)

sys/dev/bwi/bwirf.c

2355

if (phy->phy_mode == IEEE80211_MODE_11B)

sys/dev/bwi/bwirf.c

270

switch (phy->phy_mode) {

sys/dev/bwi/bwirf.c

303

if (phy->phy_rev == 6)

sys/dev/bwi/bwirf.c

386

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwirf.c

442

if (phy->phy_rev >= 3)

sys/dev/bwi/bwirf.c

454

phy->phy_rev >= 7) {

sys/dev/bwi/bwirf.c

678

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwirf.c

682

if ((phy->phy_flags & BWI_PHY_F_LINKED) == 0)

sys/dev/bwi/bwirf.c

711

if (phy->phy_rev >= 7 && (sc->sc_card_flags & BWI_CARD_F_EXT_LNA)) {

sys/dev/bwi/bwirf.c

769

struct bwi_phy *phy = &mac->mac_phy;

sys/dev/bwi/bwirf.c

781

if (phy->phy_mode == IEEE80211_MODE_11B) {

sys/dev/bwi/bwirf.c

787

} else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

801

if (phy->phy_rev >= 3)

sys/dev/bwi/bwirf.c

809

if (phy->phy_rev < 7 ||

sys/dev/bwi/bwirf.c

823

if (phy->phy_version == 0) {

sys/dev/bwi/bwirf.c

826

if (phy->phy_version >= 2)

sys/dev/bwi/bwirf.c

833

if (phy->phy_mode == IEEE80211_MODE_11B)

sys/dev/bwi/bwirf.c

836

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

844

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

866

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

873

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

880

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

890

if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

916

if ((phy->phy_flags & BWI_PHY_F_LINKED) ||

sys/dev/bwi/bwirf.c

917

phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

924

if ((phy->phy_flags & BWI_PHY_F_LINKED) ||

sys/dev/bwi/bwirf.c

925

phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

932

if ((phy->phy_flags & BWI_PHY_F_LINKED) ||

sys/dev/bwi/bwirf.c

933

phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

943

if ((phy->phy_flags & BWI_PHY_F_LINKED) ||

sys/dev/bwi/bwirf.c

944

phy->phy_rev >= 2) {

sys/dev/bwi/bwirf.c

981

if (phy->phy_version != 0)

sys/dev/bwi/bwirf.c

987

if (phy->phy_mode == IEEE80211_MODE_11B) {

sys/dev/bwi/bwirf.c

990

} else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {

sys/dev/bwi/if_bwi.c

1688

struct bwi_phy *phy;

sys/dev/bwi/if_bwi.c

1696

phy = &mac->mac_phy;

sys/dev/bwi/if_bwi.c

1699

switch (phy->phy_mode) {

sys/dev/bwi/if_bwi.c

1712

panic("unknown phymode %d\n", phy->phy_mode);

sys/dev/bwi/if_bwi.c

359

struct bwi_phy *phy;

sys/dev/bwi/if_bwi.c

440

phy = &mac->mac_phy;

sys/dev/bwi/if_bwi.c

457

if (phy->phy_mode == IEEE80211_MODE_11B ||

sys/dev/bwi/if_bwi.c

458

phy->phy_mode == IEEE80211_MODE_11G) {

sys/dev/bwi/if_bwi.c

459

if (phy->phy_mode == IEEE80211_MODE_11B) {

sys/dev/bwi/if_bwi.c

474

} else if (phy->phy_mode == IEEE80211_MODE_11A) {

sys/dev/bwi/if_bwi.c

479

panic("unknown phymode %d\n", phy->phy_mode);

sys/dev/bwn/if_bwn.c

1571

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn.c

1577

phy->gmode = gmode;

sys/dev/bwn/if_bwn.c

1578

phy->rf_on = 1;

sys/dev/bwn/if_bwn.c

1579

phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12;

sys/dev/bwn/if_bwn.c

1580

phy->type = (tmp & BWN_PHYVER_TYPE) >> 8;

sys/dev/bwn/if_bwn.c

1581

phy->rev = (tmp & BWN_PHYVER_VERSION);

sys/dev/bwn/if_bwn.c

1582

if ((phy->type == BWN_PHYTYPE_A && phy->rev >= 4) ||

sys/dev/bwn/if_bwn.c

1583

(phy->type == BWN_PHYTYPE_B && phy->rev != 2 &&

sys/dev/bwn/if_bwn.c

1584

phy->rev != 4 && phy->rev != 6 && phy->rev != 7) ||

sys/dev/bwn/if_bwn.c

1585

(phy->type == BWN_PHYTYPE_G && phy->rev > 9) ||

sys/dev/bwn/if_bwn.c

1586

(phy->type == BWN_PHYTYPE_N && phy->rev > 6) ||

sys/dev/bwn/if_bwn.c

1587

(phy->type == BWN_PHYTYPE_LP && phy->rev > 2))

sys/dev/bwn/if_bwn.c

1596

phy->rf_rev = (tmp & 0xf0000000) >> 28;

sys/dev/bwn/if_bwn.c

1597

phy->rf_ver = (tmp & 0x0ffff000) >> 12;

sys/dev/bwn/if_bwn.c

1598

phy->rf_manuf = (tmp & 0x00000fff);

sys/dev/bwn/if_bwn.c

1604

phy->phy_do_full_init = 1;

sys/dev/bwn/if_bwn.c

1606

if (phy->rf_manuf != 0x17f) /* 0x17f is broadcom */

sys/dev/bwn/if_bwn.c

1608

if ((phy->type == BWN_PHYTYPE_A && (phy->rf_ver != 0x2060 ||

sys/dev/bwn/if_bwn.c

1609

phy->rf_rev != 1 || phy->rf_manuf != 0x17f)) ||

sys/dev/bwn/if_bwn.c

1610

(phy->type == BWN_PHYTYPE_B && (phy->rf_ver & 0xfff0) != 0x2050) ||

sys/dev/bwn/if_bwn.c

1611

(phy->type == BWN_PHYTYPE_G && phy->rf_ver != 0x2050) ||

sys/dev/bwn/if_bwn.c

1612

(phy->type == BWN_PHYTYPE_N &&

sys/dev/bwn/if_bwn.c

1613

phy->rf_ver != 0x2055 && phy->rf_ver != 0x2056) ||

sys/dev/bwn/if_bwn.c

1614

(phy->type == BWN_PHYTYPE_LP &&

sys/dev/bwn/if_bwn.c

1615

phy->rf_ver != 0x2062 && phy->rf_ver != 0x2063))

sys/dev/bwn/if_bwn.c

1622

phy->type, phy->rev, phy->analog);

sys/dev/bwn/if_bwn.c

1627

phy->rf_manuf, phy->rf_ver, phy->rf_rev);

sys/dev/bwn/if_bwn.c

1970

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn.c

1981

if (chan != phy->chan)

sys/dev/bwn/if_bwn.c

1986

ic->ic_curchan->ic_maxpower != phy->txpower) {

sys/dev/bwn/if_bwn.c

1987

phy->txpower = ic->ic_curchan->ic_maxpower / 2;

sys/dev/bwn/if_bwn.c

1993

if (phy->set_antenna)

sys/dev/bwn/if_bwn.c

1994

phy->set_antenna(mac, BWN_ANT_DEFAULT);

sys/dev/bwn/if_bwn.c

1996

if (sc->sc_rf_enabled != phy->rf_on) {

sys/dev/bwn/if_bwn.c

2406

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn.c

2412

if (phy->gmode)

sys/dev/bwn/if_bwn.c

2431

phy->switch_analog(mac, 1);

sys/dev/bwn/if_bwn.c

2436

if (phy->set_im)

sys/dev/bwn/if_bwn.c

2437

phy->set_im(mac, BWN_IMMODE_NONE);

sys/dev/bwn/if_bwn.c

2438

if (phy->set_antenna)

sys/dev/bwn/if_bwn.c

2439

phy->set_antenna(mac, BWN_ANT_DEFAULT);

sys/dev/bwn/if_bwn.c

2442

if (phy->type == BWN_PHYTYPE_B)

sys/dev/bwn/if_bwn.c

3840

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn.c

3868

if (phy->type == BWN_PHYTYPE_N || phy->type == BWN_PHYTYPE_LP ||

sys/dev/bwn/if_bwn.c

3869

phy->type == BWN_PHYTYPE_LCN)

sys/dev/bwn/if_bwn.c

3880

switch (phy->type) {

sys/dev/bwn/if_bwn.c

3896

if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5)

sys/dev/bwn/if_bwn.c

3916

if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5)

sys/dev/bwn/if_bwn.c

4552

struct bwn_phy *phy = &(mac->mac_phy);

sys/dev/bwn/if_bwn.c

4559

chan = phy->get_default_chan(mac);

sys/dev/bwn/if_bwn.c

4566

error = phy->switch_channel(mac, chan);

sys/dev/bwn/if_bwn.c

5926

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn.c

5927

struct bwn_phy_g *gphy = &phy->phy_g;

sys/dev/bwn/if_bwn.c

5930

switch (phy->rf_ver) {

sys/dev/bwn/if_bwn.c

5952

if (phy->type == BWN_PHYTYPE_G && adjust_2050)

sys/dev/bwn/if_bwn.c

6058

rssi = bwn_rx_rssi_calc(mac, rxhdr->phy.abg.rssi,

sys/dev/bwn/if_bwn.c

6065

if (rxhdr->phy.n.power0 == 16 || rxhdr->phy.n.power0 == 32)

sys/dev/bwn/if_bwn.c

6066

rssi = max(rxhdr->phy.n.power1, rxhdr->ps2.n.power2);

sys/dev/bwn/if_bwn.c

6068

rssi = max(rxhdr->phy.n.power0, rxhdr->phy.n.power1);

sys/dev/bwn/if_bwn.c

6073

rxhdr->phy.n.power0,

sys/dev/bwn/if_bwn.c

6074

rxhdr->phy.n.power1,

sys/dev/bwn/if_bwn.c

6227

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn.c

6234

if (!(flags & BWN_TXPWR_IGNORE_TIME) && ieee80211_time_before(now, phy->nexttime))

sys/dev/bwn/if_bwn.c

6236

phy->nexttime = now + 2 * 1000;

sys/dev/bwn/if_bwn.c

6242

if (phy->recalc_txpwr != NULL) {

sys/dev/bwn/if_bwn.c

6243

result = phy->recalc_txpwr(mac,

sys/dev/bwn/if_bwn.c

6249

KASSERT(phy->set_txpwr != NULL, ("%s: fail", __func__));

sys/dev/bwn/if_bwn.c

6323

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn.c

6330

if (BWN_ISCCKRATE(bitrate) && phy->type != BWN_PHYTYPE_LP) {

sys/dev/bwn/if_bwn.c

6395

const struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn.c

6418

if ((phy->type == BWN_PHYTYPE_N) || (phy->type == BWN_PHYTYPE_LP)

sys/dev/bwn/if_bwn.c

6419

|| (phy->type == BWN_PHYTYPE_HT))

sys/dev/bwn/if_bwn.c

6480

txhdr->chan = phy->chan;

sys/dev/bwn/if_bwn.c

6488

if (! phy->gmode)

sys/dev/bwn/if_bwn.c

6524

if (phy->gmode)

sys/dev/bwn/if_bwn_phy_g.c

1000

if (phy->analog == 1)

sys/dev/bwn/if_bwn_phy_g.c

1005

if (phy->analog == 0)

sys/dev/bwn/if_bwn_phy_g.c

1008

old_channel = phy->chan;

sys/dev/bwn/if_bwn_phy_g.c

1011

if (phy->rf_ver != 0x2050) {

sys/dev/bwn/if_bwn_phy_g.c

1019

if (phy->rf_ver == 0x2050) {

sys/dev/bwn/if_bwn_phy_g.c

1036

if (phy->rf_ver == 0x2050)

sys/dev/bwn/if_bwn_phy_g.c

1045

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

1046

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

1059

if (phy->rev != 1) {

sys/dev/bwn/if_bwn_phy_g.c

1084

if (phy->rev != 1) {

sys/dev/bwn/if_bwn_phy_g.c

1100

if (phy->rev != 1) {

sys/dev/bwn/if_bwn_phy_g.c

1106

if (phy->rf_rev == 8)

sys/dev/bwn/if_bwn_phy_g.c

1114

if (phy->rev >= 3)

sys/dev/bwn/if_bwn_phy_g.c

1127

if (phy->rev >= 7) {

sys/dev/bwn/if_bwn_phy_g.c

1135

loop_i_max = (phy->rf_rev == 8) ? 15 : 9;

sys/dev/bwn/if_bwn_phy_g.c

1167

if (phy->rev != 1) {

sys/dev/bwn/if_bwn_phy_g.c

1202

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

1224

if (phy->type == BWN_PHYTYPE_B) {

sys/dev/bwn/if_bwn_phy_g.c

1230

} else if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

1242

if (BWN_HAS_LOOPBACK(phy)) {

sys/dev/bwn/if_bwn_phy_g.c

1245

if (phy->rev >= 3)

sys/dev/bwn/if_bwn_phy_g.c

1265

if (phy->analog == 0)

sys/dev/bwn/if_bwn_phy_g.c

1268

if (phy->analog >= 2)

sys/dev/bwn/if_bwn_phy_g.c

1278

if (phy->type == BWN_PHYTYPE_B)

sys/dev/bwn/if_bwn_phy_g.c

1280

if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

1287

if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

1294

if (phy->rf_rev == 8)

sys/dev/bwn/if_bwn_phy_g.c

1306

if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

1313

if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

1320

if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

1329

if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

1350

if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

1357

if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

1364

if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

1373

if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

1394

if (phy->analog != 0)

sys/dev/bwn/if_bwn_phy_g.c

1397

bwn_spu_workaround(mac, phy->chan);

sys/dev/bwn/if_bwn_phy_g.c

1398

if (phy->type == BWN_PHYTYPE_B) {

sys/dev/bwn/if_bwn_phy_g.c

1401

} else if (phy->gmode) {

sys/dev/bwn/if_bwn_phy_g.c

1412

if (BWN_HAS_LOOPBACK(phy)) {

sys/dev/bwn/if_bwn_phy_g.c

1424

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

1425

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

1430

KASSERT(!(phy->rf_rev == 6 || phy->rf_rev == 7),

sys/dev/bwn/if_bwn_phy_g.c

1435

if (phy->rf_rev == 4 || phy->rf_rev == 5) {

sys/dev/bwn/if_bwn_phy_g.c

1448

if (phy->rf_rev == 8) {

sys/dev/bwn/if_bwn_phy_g.c

1480

if (phy->type == BWN_PHYTYPE_G) {

sys/dev/bwn/if_bwn_phy_g.c

1489

old_channel = phy->chan;

sys/dev/bwn/if_bwn_phy_g.c

1495

if (phy->rf_rev < 6 || phy->rf_rev == 8) {

sys/dev/bwn/if_bwn_phy_g.c

1499

if (phy->rf_rev <= 2) {

sys/dev/bwn/if_bwn_phy_g.c

1510

if (phy->rf_rev >= 6)

sys/dev/bwn/if_bwn_phy_g.c

1517

if (phy->rf_rev <= 5)

sys/dev/bwn/if_bwn_phy_g.c

1519

if (phy->rf_rev <= 2)

sys/dev/bwn/if_bwn_phy_g.c

152

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

1522

if (phy->analog == 4) {

sys/dev/bwn/if_bwn_phy_g.c

1527

if (phy->type == BWN_PHYTYPE_B)

sys/dev/bwn/if_bwn_phy_g.c

1529

else if (phy->type == BWN_PHYTYPE_G)

sys/dev/bwn/if_bwn_phy_g.c

153

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

1536

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

1539

KASSERT(phy->type == BWN_PHYTYPE_A || phy->type == BWN_PHYTYPE_G,

sys/dev/bwn/if_bwn_phy_g.c

1542

if (phy->rev >= 6) {

sys/dev/bwn/if_bwn_phy_g.c

1543

if (phy->type == BWN_PHYTYPE_A)

sys/dev/bwn/if_bwn_phy_g.c

1553

if (phy->type == BWN_PHYTYPE_G &&

sys/dev/bwn/if_bwn_phy_g.c

1570

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

1572

if (phy->rev == 1) {

sys/dev/bwn/if_bwn_phy_g.c

1599

if (phy->rev == 1)

sys/dev/bwn/if_bwn_phy_g.c

1610

if (phy->rev == 1) {

sys/dev/bwn/if_bwn_phy_g.c

1617

if (phy->rev >= 6) {

sys/dev/bwn/if_bwn_phy_g.c

1625

if (phy->rev == 1) {

sys/dev/bwn/if_bwn_phy_g.c

1640

if (phy->rev >= 6) {

sys/dev/bwn/if_bwn_phy_g.c

1650

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

1656

KASSERT(phy->type == BWN_PHYTYPE_G, ("%s fail", __func__));

sys/dev/bwn/if_bwn_phy_g.c

1659

if (phy->rev == 1) {

sys/dev/bwn/if_bwn_phy_g.c

1661

} else if (phy->rev == 2) {

sys/dev/bwn/if_bwn_phy_g.c

1681

if (phy->rev == 1)

sys/dev/bwn/if_bwn_phy_g.c

1695

if (phy->rev >= 6) {

sys/dev/bwn/if_bwn_phy_g.c

1708

if (phy->rev == 1) {

sys/dev/bwn/if_bwn_phy_g.c

1723

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

1728

KASSERT(phy->type == BWN_PHYTYPE_G, ("%s fail", __func__));

sys/dev/bwn/if_bwn_phy_g.c

1733

if (phy->rev == 1)

sys/dev/bwn/if_bwn_phy_g.c

1735

else if (phy->rev == 2) {

sys/dev/bwn/if_bwn_phy_g.c

1750

if (phy->rev == 1)

sys/dev/bwn/if_bwn_phy_g.c

1760

if (phy->rev >= 6) {

sys/dev/bwn/if_bwn_phy_g.c

1773

if (phy->rev == 1) {

sys/dev/bwn/if_bwn_phy_g.c

1786

if (phy->type == BWN_PHYTYPE_A)

sys/dev/bwn/if_bwn_phy_g.c

1803

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

1806

KASSERT(phy->type == BWN_PHYTYPE_G, ("%s fail", __func__));

sys/dev/bwn/if_bwn_phy_g.c

1808

switch (phy->rev) {

sys/dev/bwn/if_bwn_phy_g.c

1826

if (phy->rev < 2) {

sys/dev/bwn/if_bwn_phy_g.c

1836

(phy->rev >= 7)) {

sys/dev/bwn/if_bwn_phy_g.c

1924

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

1929

if (phy->gmode) {

sys/dev/bwn/if_bwn_phy_g.c

1942

phy->rev > 6)

sys/dev/bwn/if_bwn_phy_g.c

1975

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

1978

if (phy->type == BWN_PHYTYPE_B) {

sys/dev/bwn/if_bwn_phy_g.c

1980

if (phy->rf_rev <= 5) {

sys/dev/bwn/if_bwn_phy_g.c

1988

if (phy->rev >= 2 && phy->rf_rev == 8) {

sys/dev/bwn/if_bwn_phy_g.c

2009

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

2010

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

2024

if (!BWN_HAS_LOOPBACK(phy)) {

sys/dev/bwn/if_bwn_phy_g.c

2043

if ((phy->rev >= 2) &&

sys/dev/bwn/if_bwn_phy_g.c

2044

(phy->rf_ver == 0x2050) && (phy->rf_rev == 8))

sys/dev/bwn/if_bwn_phy_g.c

2068

if (BWN_HAS_TXMAG(phy)) {

sys/dev/bwn/if_bwn_phy_g.c

2107

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

2108

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

2129

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

2130

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

2136

if (BWN_HAS_LOOPBACK(phy)) {

sys/dev/bwn/if_bwn_phy_g.c

2188

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

2189

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

2207

if (phy->type == BWN_PHYTYPE_B &&

sys/dev/bwn/if_bwn_phy_g.c

2208

phy->rf_ver == 0x2050 && phy->rf_rev < 6) {

sys/dev/bwn/if_bwn_phy_g.c

2212

if (phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

2226

if (phy->type == BWN_PHYTYPE_G) {

sys/dev/bwn/if_bwn_phy_g.c

2227

if ((phy->rev >= 7) &&

sys/dev/bwn/if_bwn_phy_g.c

2248

if (!BWN_HAS_TXMAG(phy)) {

sys/dev/bwn/if_bwn_phy_g.c

2252

if (phy->type == BWN_PHYTYPE_B) {

sys/dev/bwn/if_bwn_phy_g.c

2265

(phy->type == BWN_PHYTYPE_G) ? BWN_PHY_LO_MASK : BWN_PHY_CCK(0x2e);

sys/dev/bwn/if_bwn_phy_g.c

2274

if (phy->type == BWN_PHYTYPE_G ||

sys/dev/bwn/if_bwn_phy_g.c

2275

(phy->type == BWN_PHYTYPE_B &&

sys/dev/bwn/if_bwn_phy_g.c

2276

phy->rf_ver == 0x2050 && phy->rf_rev >= 6)) {

sys/dev/bwn/if_bwn_phy_g.c

2280

if (phy->rev >= 2)

sys/dev/bwn/if_bwn_phy_g.c

2284

if (phy->type == BWN_PHYTYPE_G)

sys/dev/bwn/if_bwn_phy_g.c

2292

if (phy->type == BWN_PHYTYPE_G && phy->rev >= 3)

sys/dev/bwn/if_bwn_phy_g.c

2295

if (phy->type == BWN_PHYTYPE_B)

sys/dev/bwn/if_bwn_phy_g.c

2305

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

2306

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

2309

if (phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

2321

if (phy->type == BWN_PHYTYPE_G) {

sys/dev/bwn/if_bwn_phy_g.c

2322

if (phy->rev >= 3)

sys/dev/bwn/if_bwn_phy_g.c

2326

if (phy->rev >= 2)

sys/dev/bwn/if_bwn_phy_g.c

2338

if (!BWN_HAS_TXMAG(phy)) {

sys/dev/bwn/if_bwn_phy_g.c

2343

if (phy->type == BWN_PHYTYPE_B &&

sys/dev/bwn/if_bwn_phy_g.c

2344

phy->rf_ver == 0x2050 && phy->rf_rev <= 5) {

sys/dev/bwn/if_bwn_phy_g.c

2348

if (phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

2373

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

2374

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

239

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

240

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

2417

if (d->nmeasure < 2 && !BWN_HAS_LOOPBACK(phy))

sys/dev/bwn/if_bwn_phy_g.c

2437

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

2438

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

2446

if (BWN_HAS_LOOPBACK(phy))

sys/dev/bwn/if_bwn_phy_g.c

2450

repeat = (BWN_HAS_LOOPBACK(phy)) ? 4 : 1;

sys/dev/bwn/if_bwn_phy_g.c

2481

if (BWN_HAS_LOOPBACK(phy)) {

sys/dev/bwn/if_bwn_phy_g.c

2495

bwn_lo_measure_gain_values(mac, *rxgain, BWN_HAS_LOOPBACK(phy));

sys/dev/bwn/if_bwn_phy_g.c

2503

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

2504

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

2511

sval.old_channel = phy->chan;

sys/dev/bwn/if_bwn_phy_g.c

2522

if (BWN_HAS_LOOPBACK(phy))

sys/dev/bwn/if_bwn_phy_g.c

2524

bwn_lo_measure_gain_values(mac, rxgain, BWN_HAS_LOOPBACK(phy));

sys/dev/bwn/if_bwn_phy_g.c

2571

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

2572

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

2678

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

2679

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

2685

KASSERT(phy->type == BWN_PHYTYPE_G, ("%s: fail", __func__));

sys/dev/bwn/if_bwn_phy_g.c

2687

if (phy->gmode && (sc->sc_board_info.board_flags & BHND_BFL_ADCDIV)) {

sys/dev/bwn/if_bwn_phy_g.c

272

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

273

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

2738

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

2739

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

2748

KASSERT(phy->type == BWN_PHYTYPE_G,

sys/dev/bwn/if_bwn_phy_g.c

2751

if (phy->rf_rev >= 9)

sys/dev/bwn/if_bwn_phy_g.c

2753

if (phy->rf_rev == 8)

sys/dev/bwn/if_bwn_phy_g.c

2771

if (phy->rev >= 3) {

sys/dev/bwn/if_bwn_phy_g.c

2776

switch (phy->rev) {

sys/dev/bwn/if_bwn_phy_g.c

2797

if (phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

2812

if (phy->rev >= 2)

sys/dev/bwn/if_bwn_phy_g.c

2819

if (phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

2825

if (phy->rf_rev == 8) {

sys/dev/bwn/if_bwn_phy_g.c

2856

if (phy->rev >= 3) {

sys/dev/bwn/if_bwn_phy_g.c

2862

if (phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

2877

bwn_spu_workaround(mac, phy->chan);

sys/dev/bwn/if_bwn_phy_g.c

2881

if (phy->rev >= 3) {

sys/dev/bwn/if_bwn_phy_g.c

2918

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

293

KASSERT(phy->type == BWN_PHYTYPE_G, ("%s fail", __func__));

sys/dev/bwn/if_bwn_phy_g.c

2936

if (phy->rev >= 6) {

sys/dev/bwn/if_bwn_phy_g.c

295

if (phy->rf_ver == 0x2050 && phy->rf_rev < 6)

sys/dev/bwn/if_bwn_phy_g.c

2971

if (phy->rev != 1) {

sys/dev/bwn/if_bwn_phy_g.c

2982

if (phy->rev == 0)

sys/dev/bwn/if_bwn_phy_g.c

2986

if (phy->rev != 1) {

sys/dev/bwn/if_bwn_phy_g.c

3019

if (phy->rev >= 6) {

sys/dev/bwn/if_bwn_phy_g.c

3025

if (phy->rev != 1) {

sys/dev/bwn/if_bwn_phy_g.c

3039

if (phy->rev >= 6) {

sys/dev/bwn/if_bwn_phy_g.c

3055

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

3061

if (phy->rev <= 1) {

sys/dev/bwn/if_bwn_phy_g.c

3067

if (phy->rev <= 1)

sys/dev/bwn/if_bwn_phy_g.c

3087

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

3092

if (phy->rev <= 1) {

sys/dev/bwn/if_bwn_phy_g.c

3098

if (phy->rev <= 1)

sys/dev/bwn/if_bwn_phy_g.c

3120

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

3121

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

3127

KASSERT(phy->type == BWN_PHYTYPE_G,

sys/dev/bwn/if_bwn_phy_g.c

3138

if (!phy->gmode)

sys/dev/bwn/if_bwn_phy_g.c

314

if (phy->type == BWN_PHYTYPE_A) {

sys/dev/bwn/if_bwn_phy_g.c

3142

if (phy->rf_ver == 0x2050 && phy->analog == 0) {

sys/dev/bwn/if_bwn_phy_g.c

3150

if (phy->rf_rev == 8) {

sys/dev/bwn/if_bwn_phy_g.c

3161

if (phy->rf_ver == 0x2050 && phy->analog == 0)

sys/dev/bwn/if_bwn_phy_g.c

3179

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

319

switch (phy->rf_ver) {

sys/dev/bwn/if_bwn_phy_g.c

3190

if (phy->rf_ver == 0x2050 && phy->rf_rev == 8) {

sys/dev/bwn/if_bwn_phy_g.c

321

switch (phy->rf_rev) {

sys/dev/bwn/if_bwn_phy_g.c

3210

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

3211

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

3243

if (phy->rf_rev == 8)

sys/dev/bwn/if_bwn_phy_g.c

3256

KASSERT(phy->rev >= 6, ("%s:%d: fail", __func__, __LINE__));

sys/dev/bwn/if_bwn_phy_g.c

326

if (phy->type == BWN_PHYTYPE_G) {

sys/dev/bwn/if_bwn_phy_g.c

3317

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

3318

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

3336

if (phy->rf_ver == 0x2050 && phy->rf_rev == 8)

sys/dev/bwn/if_bwn_phy_g.c

3342

if (BWN_HAS_TXMAG(phy))

sys/dev/bwn/if_bwn_phy_g.c

3353

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

3355

if (phy->analog == 0) {

sys/dev/bwn/if_bwn_phy_g.c

3360

if (phy->analog > 1) {

sys/dev/bwn/if_bwn_phy_g.c

3370

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

3371

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

3377

if (phy->gmode == 0)

sys/dev/bwn/if_bwn_phy_g.c

3380

if (BWN_HAS_LOOPBACK(phy)) {

sys/dev/bwn/if_bwn_phy_g.c

3382

max_lb_gain += (phy->rf_rev == 8) ? 0x3e : 0x26;

sys/dev/bwn/if_bwn_phy_g.c

3403

if ((phy->rev < 7) ||

sys/dev/bwn/if_bwn_phy_g.c

3447

if ((phy->rev < 7) ||

sys/dev/bwn/if_bwn_phy_g.c

352

if (phy->type == BWN_PHYTYPE_G) {

sys/dev/bwn/if_bwn_phy_g.c

394

switch (phy->rf_rev) {

sys/dev/bwn/if_bwn_phy_g.c

412

if (phy->rf_ver == 0x2050 && phy->rf_rev == 8) {

sys/dev/bwn/if_bwn_phy_g.c

430

if (phy->rev == 1) {

sys/dev/bwn/if_bwn_phy_g.c

431

phy->gmode = 0;

sys/dev/bwn/if_bwn_phy_g.c

434

phy->gmode = 1;

sys/dev/bwn/if_bwn_phy_g.c

443

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

445

if (phy->rf_ver != 0x2050)

sys/dev/bwn/if_bwn_phy_g.c

447

if (phy->rf_rev == 1)

sys/dev/bwn/if_bwn_phy_g.c

449

if (phy->rf_rev < 6)

sys/dev/bwn/if_bwn_phy_g.c

451

if (phy->rf_rev == 8)

sys/dev/bwn/if_bwn_phy_g.c

522

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

523

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

528

if (phy->rf_on)

sys/dev/bwn/if_bwn_phy_g.c

533

BWN_PHY_WRITE(mac, 0x15, (phy->gmode ? 0xc0 : 0x0));

sys/dev/bwn/if_bwn_phy_g.c

541

channel = phy->chan;

sys/dev/bwn/if_bwn_phy_g.c

577

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

607

if (phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

613

if (phy->rev == 2)

sys/dev/bwn/if_bwn_phy_g.c

620

if (phy->rev >= 6)

sys/dev/bwn/if_bwn_phy_g.c

630

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

631

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

633

KASSERT(phy->type == BWN_PHYTYPE_G, ("%s: fail", __func__));

sys/dev/bwn/if_bwn_phy_g.c

636

if (phy->rev == 0 || !phy->gmode)

sys/dev/bwn/if_bwn_phy_g.c

646

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

647

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

655

KASSERT(phy->type == BWN_PHYTYPE_G, ("%s: fail", __func__));

sys/dev/bwn/if_bwn_phy_g.c

680

power = MIN(MAX((phy->txpower < 0) ? 0 : (phy->txpower << 2), 0), max) -

sys/dev/bwn/if_bwn_phy_g.c

698

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

699

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

715

if ((phy->rf_ver == 0x2050) && (phy->rf_rev == 2)) {

sys/dev/bwn/if_bwn_phy_g.c

757

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

758

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

816

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

818

uint8_t old = phy->chan;

sys/dev/bwn/if_bwn_phy_g.c

825

if ((phy->rf_ver == 0x2050) && (phy->rf_rev == 8)) {

sys/dev/bwn/if_bwn_phy_g.c

842

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

843

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

847

if (phy->rev == 1)

sys/dev/bwn/if_bwn_phy_g.c

852

if (phy->rev >= 2 || phy->gmode)

sys/dev/bwn/if_bwn_phy_g.c

855

if (phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

859

if (phy->rev == 2) {

sys/dev/bwn/if_bwn_phy_g.c

863

if (phy->rev > 5) {

sys/dev/bwn/if_bwn_phy_g.c

867

if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

879

if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)

sys/dev/bwn/if_bwn_phy_g.c

881

if (phy->rf_rev == 8) {

sys/dev/bwn/if_bwn_phy_g.c

885

if (BWN_HAS_LOOPBACK(phy))

sys/dev/bwn/if_bwn_phy_g.c

888

if (phy->rf_rev != 8) {

sys/dev/bwn/if_bwn_phy_g.c

895

if (BWN_HAS_TXMAG(phy)) {

sys/dev/bwn/if_bwn_phy_g.c

903

if (phy->rev >= 6) {

sys/dev/bwn/if_bwn_phy_g.c

911

if (phy->rev < 2)

sys/dev/bwn/if_bwn_phy_g.c

915

if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

928

} else if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

936

if (phy->rf_rev == 8)

sys/dev/bwn/if_bwn_phy_g.c

949

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_g.c

950

struct bwn_phy_g *pg = &phy->phy_g;

sys/dev/bwn/if_bwn_phy_g.c

955

if (phy->analog == 1)

sys/dev/bwn/if_bwn_phy_g.c

966

if (phy->rf_ver == 0x2050)

sys/dev/bwn/if_bwn_phy_g.c

969

if (phy->gmode || phy->rev >= 2) {

sys/dev/bwn/if_bwn_phy_g.c

970

if (phy->rf_ver == 0x2050) {

sys/dev/bwn/if_bwn_phy_g.c

989

if (phy->analog == 1) {

sys/dev/bwn/if_bwn_phy_lp.c

382

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_lp.c

383

struct bwn_phy_lp *plp = &phy->phy_lp;

sys/dev/bwn/if_bwn_phy_lp.c

553

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_lp.c

554

struct bwn_phy_lp *plp = &phy->phy_lp;

sys/dev/bwn/if_bwn_phy_lp.c

557

if (phy->rf_ver == 0x2063) {

sys/dev/bwn/if_bwn_phy_lp.c

586

struct bwn_phy *phy = &mac->mac_phy;

sys/dev/bwn/if_bwn_phy_lp.c

587

struct bwn_phy_lp *plp = &phy->phy_lp;

sys/dev/bwn/if_bwn_phy_lp.c

589

if (phy->rev >= 2 || antenna > BWN_ANTAUTO1)

sys/dev/bwn/if_bwnvar.h

263

} __packed phy;

sys/dev/bwn/if_bwnvar.h

47

#define BWN_HAS_TXMAG(phy) \

sys/dev/bwn/if_bwnvar.h

48

(((phy)->rev >= 2) && ((phy)->rf_ver == 0x2050) && \

sys/dev/bwn/if_bwnvar.h

49

((phy)->rf_rev == 8))

sys/dev/bwn/if_bwnvar.h

50

#define BWN_HAS_LOOPBACK(phy) \

sys/dev/bwn/if_bwnvar.h

51

(((phy)->rev > 1) || ((phy)->gmode))

sys/dev/bxe/bxe.c

11629

(sc->link_params.phy[ELINK_EXT_PHY2].supported &

sys/dev/bxe/bxe.c

13844

switch (sc->link_params.phy[phy_idx].media_type) {

sys/dev/bxe/bxe.c

14220

sc->port.supported[0] = sc->link_params.phy[ELINK_INT_PHY].supported;

sys/dev/bxe/bxe.c

14224

sc->port.supported[0] = sc->link_params.phy[ELINK_EXT_PHY1].supported;

sys/dev/bxe/bxe.c

14231

sc->link_params.phy[ELINK_EXT_PHY1].supported;

sys/dev/bxe/bxe.c

14233

sc->link_params.phy[ELINK_EXT_PHY2].supported;

sys/dev/bxe/bxe.c

14236

sc->link_params.phy[ELINK_EXT_PHY1].supported;

sys/dev/bxe/bxe.c

14238

sc->link_params.phy[ELINK_EXT_PHY2].supported;

sys/dev/bxe/bxe.c

14352

if (sc->link_params.phy[ELINK_EXT_PHY1].type ==

sys/dev/bxe/bxe.c

19208

if(sc->link_params.phy[bxe_get_cur_phy_idx(sc)].media_type ==

sys/dev/bxe/bxe_elink.c

10000

if (phy->req_line_speed == ELINK_SPEED_1000) {

sys/dev/bxe/bxe_elink.c

10002

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10004

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10006

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10008

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10011

} else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&

sys/dev/bxe/bxe_elink.c

10012

(phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

10014

((phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

10019

elink_ext_phy_set_pause(params, phy, vars);

sys/dev/bxe/bxe_elink.c

10020

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10022

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10024

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10026

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10028

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10033

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10035

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10040

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10049

phy->tx_preemphasis[0],

sys/dev/bxe/bxe_elink.c

10050

phy->tx_preemphasis[1]);

sys/dev/bxe/bxe_elink.c

10051

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10054

phy->tx_preemphasis[0]);

sys/dev/bxe/bxe_elink.c

10056

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10059

phy->tx_preemphasis[1]);

sys/dev/bxe/bxe_elink.c

10066

static void elink_8726_link_reset(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

10072

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10081

static void elink_8727_set_link_led(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

10089

if (!(phy->flags & ELINK_FLAGS_NOC))

sys/dev/bxe/bxe_elink.c

10106

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10112

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10116

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10122

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10127

static void elink_8727_hw_reset(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

10142

static void elink_8727_config_speed(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

10148

if ((phy->req_line_speed == ELINK_SPEED_1000) ||

sys/dev/bxe/bxe_elink.c

10149

(phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {

sys/dev/bxe/bxe_elink.c

10151

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10153

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10155

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10162

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10166

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10170

} else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&

sys/dev/bxe/bxe_elink.c

10171

((phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

10173

((phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

10178

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10180

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10186

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10189

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10191

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10193

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10199

static elink_status_t elink_8727_config_init(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

10208

elink_wait_reset_complete(sc, phy, params);

sys/dev/bxe/bxe_elink.c

10212

elink_8727_specific_func(phy, params, ELINK_PHY_INIT);

sys/dev/bxe/bxe_elink.c

10216

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10223

if (!(phy->flags & ELINK_FLAGS_NOC))

sys/dev/bxe/bxe_elink.c

10225

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10229

elink_set_disable_pmd_transmit(params, phy, 0);

sys/dev/bxe/bxe_elink.c

10231

elink_8727_power_module(sc, phy, 1);

sys/dev/bxe/bxe_elink.c

10233

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10236

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10239

elink_8727_config_speed(phy, params);

sys/dev/bxe/bxe_elink.c

10246

phy->tx_preemphasis[0],

sys/dev/bxe/bxe_elink.c

10247

phy->tx_preemphasis[1]);

sys/dev/bxe/bxe_elink.c

10248

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10250

phy->tx_preemphasis[0]);

sys/dev/bxe/bxe_elink.c

10252

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10254

phy->tx_preemphasis[1]);

sys/dev/bxe/bxe_elink.c

10268

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10272

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10274

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10277

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10285

static void elink_8727_handle_mod_abs(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

10294

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10302

phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;

sys/dev/bxe/bxe_elink.c

10311

if (!(phy->flags & ELINK_FLAGS_NOC))

sys/dev/bxe/bxe_elink.c

10313

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10320

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10336

if (!(phy->flags & ELINK_FLAGS_NOC))

sys/dev/bxe/bxe_elink.c

10338

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10347

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10354

elink_sfp_set_transmitter(params, phy, 0);

sys/dev/bxe/bxe_elink.c

10356

if (elink_wait_for_sfp_module_initialized(phy, params) == 0)

sys/dev/bxe/bxe_elink.c

10357

elink_sfp_module_detection(phy, params);

sys/dev/bxe/bxe_elink.c

10362

elink_8727_config_speed(phy, params);

sys/dev/bxe/bxe_elink.c

10370

static uint8_t elink_8727_read_status(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

10381

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10388

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10394

elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,

sys/dev/bxe/bxe_elink.c

10397

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10403

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10409

if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {

sys/dev/bxe/bxe_elink.c

10411

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10430

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10434

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10439

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10443

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10446

elink_8727_power_module(params->sc, phy, 0);

sys/dev/bxe/bxe_elink.c

10453

elink_8727_handle_mod_abs(phy, params);

sys/dev/bxe/bxe_elink.c

10455

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10460

if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {

sys/dev/bxe/bxe_elink.c

10462

elink_sfp_set_transmitter(params, phy, 1);

sys/dev/bxe/bxe_elink.c

10468

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10493

elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,

sys/dev/bxe/bxe_elink.c

10496

elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,

sys/dev/bxe/bxe_elink.c

10505

elink_ext_phy_resolve_fc(phy, params, vars);

sys/dev/bxe/bxe_elink.c

10511

(phy->req_line_speed == ELINK_SPEED_1000)) {

sys/dev/bxe/bxe_elink.c

10512

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10522

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10529

static void elink_8727_link_reset(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

10535

elink_set_disable_pmd_transmit(params, phy, 1);

sys/dev/bxe/bxe_elink.c

10538

elink_sfp_set_transmitter(params, phy, 0);

sys/dev/bxe/bxe_elink.c

10540

elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);

sys/dev/bxe/bxe_elink.c

10547

static int elink_is_8483x_8485x(struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

10549

return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||

sys/dev/bxe/bxe_elink.c

10550

(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) ||

sys/dev/bxe/bxe_elink.c

10551

(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858));

sys/dev/bxe/bxe_elink.c

10554

static void elink_save_848xx_spirom_version(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

10568

if (elink_is_8483x_8485x(phy)) {

sys/dev/bxe/bxe_elink.c

10569

elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);

sys/dev/bxe/bxe_elink.c

10571

phy->ver_addr);

sys/dev/bxe/bxe_elink.c

10576

elink_cl45_write(sc, phy, reg_set[i].devad,

sys/dev/bxe/bxe_elink.c

10580

elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);

sys/dev/bxe/bxe_elink.c

10589

phy->ver_addr);

sys/dev/bxe/bxe_elink.c

10595

elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);

sys/dev/bxe/bxe_elink.c

10596

elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);

sys/dev/bxe/bxe_elink.c

10597

elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);

sys/dev/bxe/bxe_elink.c

10599

elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);

sys/dev/bxe/bxe_elink.c

10608

phy->ver_addr);

sys/dev/bxe/bxe_elink.c

10613

elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);

sys/dev/bxe/bxe_elink.c

10615

elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);

sys/dev/bxe/bxe_elink.c

10618

phy->ver_addr);

sys/dev/bxe/bxe_elink.c

10623

struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

10636

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10642

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10647

elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,

sys/dev/bxe/bxe_elink.c

10650

if (elink_is_8483x_8485x(phy))

sys/dev/bxe/bxe_elink.c

10656

elink_cl45_read_or_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10661

static void elink_848xx_specific_func(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

10668

if (!elink_is_8483x_8485x(phy)) {

sys/dev/bxe/bxe_elink.c

10670

elink_save_848xx_spirom_version(phy, sc, params->port);

sys/dev/bxe/bxe_elink.c

10679

elink_848xx_set_led(sc, phy);

sys/dev/bxe/bxe_elink.c

10684

static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

10691

elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);

sys/dev/bxe/bxe_elink.c

10692

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10696

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10700

elink_ext_phy_set_pause(params, phy, vars);

sys/dev/bxe/bxe_elink.c

10701

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10705

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

10712

if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&

sys/dev/bxe/bxe_elink.c

10713

(phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

10715

(phy->req_line_speed == ELINK_SPEED_1000)) {

sys/dev/bxe/bxe_elink.c

10718

if (phy->req_duplex == DUPLEX_FULL)

sys/dev/bxe/bxe_elink.c

10724

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10729

if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {

sys/dev/bxe/bxe_elink.c

10730

if (phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

10739

if (phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

10748

if ((phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

10750

(phy->supported & ELINK_SUPPORTED_10baseT_Full)) {

sys/dev/bxe/bxe_elink.c

10756

if ((phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

10758

(phy->supported & ELINK_SUPPORTED_10baseT_Half)) {

sys/dev/bxe/bxe_elink.c

10766

if ((phy->req_line_speed == ELINK_SPEED_100) &&

sys/dev/bxe/bxe_elink.c

10767

(phy->supported &

sys/dev/bxe/bxe_elink.c

10772

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10779

if ((phy->req_line_speed == ELINK_SPEED_10) &&

sys/dev/bxe/bxe_elink.c

10780

(phy->supported &

sys/dev/bxe/bxe_elink.c

10784

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10790

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10794

if (phy->req_duplex == DUPLEX_FULL)

sys/dev/bxe/bxe_elink.c

10800

if (!elink_is_8483x_8485x(phy) ||

sys/dev/bxe/bxe_elink.c

10802

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10806

if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&

sys/dev/bxe/bxe_elink.c

10807

(phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

10809

(phy->req_line_speed == ELINK_SPEED_10000)) {

sys/dev/bxe/bxe_elink.c

10814

sc, phy,

sys/dev/bxe/bxe_elink.c

10818

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10822

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

10830

static elink_status_t elink_8481_config_init(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

10841

elink_wait_reset_complete(sc, phy, params);

sys/dev/bxe/bxe_elink.c

10843

elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);

sys/dev/bxe/bxe_elink.c

10844

return elink_848xx_cmn_config_init(phy, params, vars);

sys/dev/bxe/bxe_elink.c

10850

static elink_status_t elink_84858_cmd_hdlr(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

10867

elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

10884

elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

10892

elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

10901

elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

10919

elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

10927

static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

10938

elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

10944

elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

10957

elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

10967

elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

10974

elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

10977

elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

10992

elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

10999

elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

11006

static elink_status_t elink_848xx_cmd_hdlr(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

11014

if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) ||

sys/dev/bxe/bxe_elink.c

11018

return elink_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,

sys/dev/bxe/bxe_elink.c

11021

return elink_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,

sys/dev/bxe/bxe_elink.c

11026

static elink_status_t elink_848xx_pair_swap_cfg(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

11047

status = elink_848xx_cmd_hdlr(phy, params,

sys/dev/bxe/bxe_elink.c

11094

static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

11106

elink_cl45_write(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

11109

elink_cl45_write(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

11127

static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

11138

rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,

sys/dev/bxe/bxe_elink.c

11145

return elink_eee_disable(phy, params, vars);

sys/dev/bxe/bxe_elink.c

11148

static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

11156

rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,

sys/dev/bxe/bxe_elink.c

11163

return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);

sys/dev/bxe/bxe_elink.c

11167

static elink_status_t elink_848x3_config_init(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

11185

if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {

sys/dev/bxe/bxe_elink.c

11191

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11196

elink_wait_reset_complete(sc, phy, params);

sys/dev/bxe/bxe_elink.c

11200

if (!elink_is_8483x_8485x(phy)) {

sys/dev/bxe/bxe_elink.c

11207

elink_set_autoneg(&params->phy[ELINK_INT_PHY], params, vars, 0);

sys/dev/bxe/bxe_elink.c

11208

elink_program_serdes(&params->phy[ELINK_INT_PHY], params, vars);

sys/dev/bxe/bxe_elink.c

11212

if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {

sys/dev/bxe/bxe_elink.c

11215

elink_cl45_read(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

11224

elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

11260

if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)

sys/dev/bxe/bxe_elink.c

11263

elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

11268

if (elink_is_8483x_8485x(phy)) {

sys/dev/bxe/bxe_elink.c

11269

elink_848xx_pair_swap_cfg(phy, params, vars);

sys/dev/bxe/bxe_elink.c

11276

rc = elink_848xx_cmd_hdlr(phy, params,

sys/dev/bxe/bxe_elink.c

11283

rc = elink_848xx_cmn_config_init(phy, params, vars);

sys/dev/bxe/bxe_elink.c

11285

elink_save_848xx_spirom_version(phy, sc, params->port);

sys/dev/bxe/bxe_elink.c

11287

if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {

sys/dev/bxe/bxe_elink.c

11293

elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

11299

elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

11303

elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,

sys/dev/bxe/bxe_elink.c

11313

elink_8483x_disable_eee(phy, params, vars);

sys/dev/bxe/bxe_elink.c

11317

if ((phy->req_duplex == DUPLEX_FULL) &&

sys/dev/bxe/bxe_elink.c

11321

rc = elink_8483x_enable_eee(phy, params, vars);

sys/dev/bxe/bxe_elink.c

11323

rc = elink_8483x_disable_eee(phy, params, vars);

sys/dev/bxe/bxe_elink.c

11332

if (elink_is_8483x_8485x(phy)) {

sys/dev/bxe/bxe_elink.c

11334

elink_cl45_read_and_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11342

static uint8_t elink_848xx_read_status(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

11353

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11355

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11365

elink_ext_phy_10G_an_resolve(sc, phy, vars);

sys/dev/bxe/bxe_elink.c

11370

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11375

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11399

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11418

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11425

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11437

elink_ext_phy_resolve_fc(phy, params, vars);

sys/dev/bxe/bxe_elink.c

11440

elink_cl45_read(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

11458

elink_cl45_read(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

11468

elink_cl45_read(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

11476

if (elink_is_8483x_8485x(phy))

sys/dev/bxe/bxe_elink.c

11477

elink_eee_an_resolve(phy, params, vars);

sys/dev/bxe/bxe_elink.c

11492

static void elink_8481_hw_reset(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

11501

static void elink_8481_link_reset(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

11504

elink_cl45_write(params->sc, phy,

sys/dev/bxe/bxe_elink.c

11506

elink_cl45_write(params->sc, phy,

sys/dev/bxe/bxe_elink.c

11510

static void elink_848x3_link_reset(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

11522

if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {

sys/dev/bxe/bxe_elink.c

11527

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11531

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11537

static void elink_848xx_set_link_led(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

11557

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11562

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11567

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11572

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11578

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11593

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11598

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11603

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11608

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11614

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11618

if (phy->type ==

sys/dev/bxe/bxe_elink.c

11635

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11649

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11656

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11662

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11667

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11672

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11677

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11682

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11686

if (phy->type ==

sys/dev/bxe/bxe_elink.c

11703

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11719

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11728

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11735

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11740

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11745

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11750

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11764

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11770

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11776

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11780

if (phy->type ==

sys/dev/bxe/bxe_elink.c

11785

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11804

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

11812

static void elink_54618se_specific_func(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

11822

elink_cl22_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11825

elink_cl22_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11830

elink_cl22_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11834

elink_cl22_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11841

static elink_status_t elink_54618se_config_init(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

11871

elink_cl22_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11873

elink_wait_reset_complete(sc, phy, params);

sys/dev/bxe/bxe_elink.c

11879

elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);

sys/dev/bxe/bxe_elink.c

11881

elink_cl22_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11884

elink_cl22_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11888

elink_cl22_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11894

elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);

sys/dev/bxe/bxe_elink.c

11905

elink_cl22_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11909

elink_cl22_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11913

elink_cl22_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11922

if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&

sys/dev/bxe/bxe_elink.c

11923

(phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

11925

(phy->req_line_speed == ELINK_SPEED_1000)) {

sys/dev/bxe/bxe_elink.c

11928

if (phy->req_duplex == DUPLEX_FULL)

sys/dev/bxe/bxe_elink.c

11934

elink_cl22_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11937

elink_cl22_read(sc, phy,

sys/dev/bxe/bxe_elink.c

11942

if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {

sys/dev/bxe/bxe_elink.c

11943

if (phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

11949

if (phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

11955

if (phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

11961

if (phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

11970

if (phy->req_line_speed == ELINK_SPEED_100) {

sys/dev/bxe/bxe_elink.c

11973

elink_cl22_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11978

if (phy->req_line_speed == ELINK_SPEED_10) {

sys/dev/bxe/bxe_elink.c

11980

elink_cl22_write(sc, phy,

sys/dev/bxe/bxe_elink.c

11986

if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {

sys/dev/bxe/bxe_elink.c

11989

elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,

sys/dev/bxe/bxe_elink.c

11992

elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);

sys/dev/bxe/bxe_elink.c

11994

elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);

sys/dev/bxe/bxe_elink.c

11999

elink_eee_disable(phy, params, vars);

sys/dev/bxe/bxe_elink.c

12001

(phy->req_duplex == DUPLEX_FULL) &&

sys/dev/bxe/bxe_elink.c

12009

elink_eee_advertise(phy, params, vars,

sys/dev/bxe/bxe_elink.c

12013

elink_eee_disable(phy, params, vars);

sys/dev/bxe/bxe_elink.c

12019

if (phy->flags & ELINK_FLAGS_EEE) {

sys/dev/bxe/bxe_elink.c

12029

elink_cl45_write(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

12034

elink_cl22_write(sc, phy,

sys/dev/bxe/bxe_elink.c

12038

if (phy->req_duplex == DUPLEX_FULL)

sys/dev/bxe/bxe_elink.c

12041

elink_cl22_write(sc, phy,

sys/dev/bxe/bxe_elink.c

12048

static void elink_5461x_set_link_led(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

12054

elink_cl22_write(sc, phy,

sys/dev/bxe/bxe_elink.c

12057

elink_cl22_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12077

elink_cl22_write(sc, phy,

sys/dev/bxe/bxe_elink.c

12084

static void elink_54618se_link_reset(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

12094

elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);

sys/dev/bxe/bxe_elink.c

12109

static uint8_t elink_54618se_read_status(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

12119

elink_cl22_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12125

elink_cl22_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12162

elink_cl22_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12168

elink_cl22_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12178

elink_ext_phy_resolve_fc(phy, params, vars);

sys/dev/bxe/bxe_elink.c

12182

elink_cl22_read(sc, phy, 0x5, &val);

sys/dev/bxe/bxe_elink.c

12200

elink_cl22_read(sc, phy, 0xa, &val);

sys/dev/bxe/bxe_elink.c

12208

if ((phy->flags & ELINK_FLAGS_EEE) &&

sys/dev/bxe/bxe_elink.c

12210

elink_eee_an_resolve(phy, params, vars);

sys/dev/bxe/bxe_elink.c

12216

static void elink_54618se_config_loopback(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

12227

elink_cl22_write(sc, phy, 0x09, 3<<11);

sys/dev/bxe/bxe_elink.c

12234

elink_cl22_read(sc, phy, 0x00, &val);

sys/dev/bxe/bxe_elink.c

12237

elink_cl22_write(sc, phy, 0x00, val);

sys/dev/bxe/bxe_elink.c

12243

elink_cl22_write(sc, phy, 0x18, 7);

sys/dev/bxe/bxe_elink.c

12244

elink_cl22_read(sc, phy, 0x18, &val);

sys/dev/bxe/bxe_elink.c

12245

elink_cl22_write(sc, phy, 0x18, val | (1<<10) | (1<<15));

sys/dev/bxe/bxe_elink.c

12259

static void elink_7101_config_loopback(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

12264

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

12268

static elink_status_t elink_7101_config_init(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

12281

elink_wait_reset_complete(sc, phy, params);

sys/dev/bxe/bxe_elink.c

12283

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

12286

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

12289

elink_ext_phy_set_pause(params, phy, vars);

sys/dev/bxe/bxe_elink.c

12291

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12294

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

12298

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12301

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12304

(uint32_t)(fw_ver1<<16 | fw_ver2), phy->ver_addr);

sys/dev/bxe/bxe_elink.c

12308

static uint8_t elink_7101_read_status(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

12315

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12317

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12321

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12323

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12330

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12337

elink_ext_phy_10G_an_resolve(sc, phy, vars);

sys/dev/bxe/bxe_elink.c

12338

elink_ext_phy_resolve_fc(phy, params, vars);

sys/dev/bxe/bxe_elink.c

12361

void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

12365

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12372

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

12377

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

12386

static void elink_7101_hw_reset(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

12396

static void elink_7101_set_link_led(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

12413

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

12957

struct elink_phy *phy, uint8_t port,

sys/dev/bxe/bxe_elink.c

12985

phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);

sys/dev/bxe/bxe_elink.c

12986

phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);

sys/dev/bxe/bxe_elink.c

12988

phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);

sys/dev/bxe/bxe_elink.c

12989

phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);

sys/dev/bxe/bxe_elink.c

12991

phy->rx_preemphasis[i << 1], phy->tx_preemphasis[i << 1]);

sys/dev/bxe/bxe_elink.c

13018

struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

13034

*phy = phy_warpcore;

sys/dev/bxe/bxe_elink.c

13036

phy->flags |= ELINK_FLAGS_4_PORT_MODE;

sys/dev/bxe/bxe_elink.c

13038

phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;

sys/dev/bxe/bxe_elink.c

13049

phy->supported &= (ELINK_SUPPORTED_10baseT_Half |

sys/dev/bxe/bxe_elink.c

13058

phy->media_type = ELINK_ETH_PHY_BASE_T;

sys/dev/bxe/bxe_elink.c

13061

phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |

sys/dev/bxe/bxe_elink.c

13066

phy->media_type = ELINK_ETH_PHY_XFP_FIBER;

sys/dev/bxe/bxe_elink.c

13069

phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |

sys/dev/bxe/bxe_elink.c

13074

phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;

sys/dev/bxe/bxe_elink.c

13077

phy->media_type = ELINK_ETH_PHY_KR;

sys/dev/bxe/bxe_elink.c

13078

phy->supported &= (ELINK_SUPPORTED_1000baseKX_Full |

sys/dev/bxe/bxe_elink.c

13086

phy->media_type = ELINK_ETH_PHY_KR;

sys/dev/bxe/bxe_elink.c

13087

phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;

sys/dev/bxe/bxe_elink.c

13088

phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |

sys/dev/bxe/bxe_elink.c

13094

phy->media_type = ELINK_ETH_PHY_KR;

sys/dev/bxe/bxe_elink.c

13095

phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;

sys/dev/bxe/bxe_elink.c

13096

phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |

sys/dev/bxe/bxe_elink.c

13103

phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;

sys/dev/bxe/bxe_elink.c

13116

phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;

sys/dev/bxe/bxe_elink.c

13118

phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;

sys/dev/bxe/bxe_elink.c

13120

phy->media_type, phy->flags, phy->supported);

sys/dev/bxe/bxe_elink.c

13128

*phy = phy_serdes;

sys/dev/bxe/bxe_elink.c

13134

*phy = phy_xgxs;

sys/dev/bxe/bxe_elink.c

13141

phy->addr = (uint8_t)phy_addr;

sys/dev/bxe/bxe_elink.c

13142

phy->mdio_ctrl = elink_get_emac_base(sc,

sys/dev/bxe/bxe_elink.c

13146

phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;

sys/dev/bxe/bxe_elink.c

13148

phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;

sys/dev/bxe/bxe_elink.c

13151

port, phy->addr, phy->mdio_ctrl);

sys/dev/bxe/bxe_elink.c

13153

elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);

sys/dev/bxe/bxe_elink.c

13162

struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

13173

*phy = phy_8073;

sys/dev/bxe/bxe_elink.c

13176

*phy = phy_8705;

sys/dev/bxe/bxe_elink.c

13179

*phy = phy_8706;

sys/dev/bxe/bxe_elink.c

13183

*phy = phy_8726;

sys/dev/bxe/bxe_elink.c

13188

*phy = phy_8727;

sys/dev/bxe/bxe_elink.c

13189

phy->flags |= ELINK_FLAGS_NOC;

sys/dev/bxe/bxe_elink.c

13194

*phy = phy_8727;

sys/dev/bxe/bxe_elink.c

13197

*phy = phy_8481;

sys/dev/bxe/bxe_elink.c

13200

*phy = phy_84823;

sys/dev/bxe/bxe_elink.c

13203

*phy = phy_84833;

sys/dev/bxe/bxe_elink.c

13206

*phy = phy_84834;

sys/dev/bxe/bxe_elink.c

13209

*phy = phy_84858;

sys/dev/bxe/bxe_elink.c

13213

*phy = phy_54618se;

sys/dev/bxe/bxe_elink.c

13215

phy->flags |= ELINK_FLAGS_EEE;

sys/dev/bxe/bxe_elink.c

13218

*phy = phy_7101;

sys/dev/bxe/bxe_elink.c

13221

*phy = phy_null;

sys/dev/bxe/bxe_elink.c

13224

*phy = phy_null;

sys/dev/bxe/bxe_elink.c

13232

phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);

sys/dev/bxe/bxe_elink.c

13233

elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);

sys/dev/bxe/bxe_elink.c

13242

phy->ver_addr = shmem_base + offsetof(struct shmem_region,

sys/dev/bxe/bxe_elink.c

13254

phy->ver_addr = shmem2_base +

sys/dev/bxe/bxe_elink.c

13265

phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);

sys/dev/bxe/bxe_elink.c

13267

if (elink_is_8483x_8485x(phy) && (phy->ver_addr)) {

sys/dev/bxe/bxe_elink.c

13271

uint32_t raw_ver = REG_RD(sc, phy->ver_addr);

sys/dev/bxe/bxe_elink.c

13274

phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |

sys/dev/bxe/bxe_elink.c

13281

phy->addr, phy->mdio_ctrl);

sys/dev/bxe/bxe_elink.c

13286

uint32_t shmem2_base, uint8_t port, struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

13289

phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;

sys/dev/bxe/bxe_elink.c

13291

return elink_populate_int_phy(sc, shmem_base, port, phy);

sys/dev/bxe/bxe_elink.c

13293

port, phy);

sys/dev/bxe/bxe_elink.c

13298

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

13308

phy->speed_cap_mask = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

13316

phy->speed_cap_mask = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

13323

phy_index, link_config, phy->speed_cap_mask);

sys/dev/bxe/bxe_elink.c

13325

phy->req_duplex = DUPLEX_FULL;

sys/dev/bxe/bxe_elink.c

13328

phy->req_duplex = DUPLEX_HALF;

sys/dev/bxe/bxe_elink.c

13330

phy->req_line_speed = ELINK_SPEED_10;

sys/dev/bxe/bxe_elink.c

13333

phy->req_duplex = DUPLEX_HALF;

sys/dev/bxe/bxe_elink.c

13335

phy->req_line_speed = ELINK_SPEED_100;

sys/dev/bxe/bxe_elink.c

13338

phy->req_line_speed = ELINK_SPEED_1000;

sys/dev/bxe/bxe_elink.c

13341

phy->req_line_speed = ELINK_SPEED_2500;

sys/dev/bxe/bxe_elink.c

13344

phy->req_line_speed = ELINK_SPEED_10000;

sys/dev/bxe/bxe_elink.c

13347

phy->req_line_speed = ELINK_SPEED_AUTO_NEG;

sys/dev/bxe/bxe_elink.c

13352

phy_index, phy->req_duplex);

sys/dev/bxe/bxe_elink.c

13356

phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;

sys/dev/bxe/bxe_elink.c

13359

phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;

sys/dev/bxe/bxe_elink.c

13362

phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;

sys/dev/bxe/bxe_elink.c

13365

phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;

sys/dev/bxe/bxe_elink.c

13368

phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;

sys/dev/bxe/bxe_elink.c

13372

phy->req_duplex, phy->req_line_speed, phy->req_flow_ctrl);

sys/dev/bxe/bxe_elink.c

13412

struct elink_phy *phy;

sys/dev/bxe/bxe_elink.c

13434

phy = &params->phy[actual_phy_idx];

sys/dev/bxe/bxe_elink.c

13437

phy) != ELINK_STATUS_OK) {

sys/dev/bxe/bxe_elink.c

13444

*phy = phy_null;

sys/dev/bxe/bxe_elink.c

13447

if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)

sys/dev/bxe/bxe_elink.c

13452

phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;

sys/dev/bxe/bxe_elink.c

13456

phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;

sys/dev/bxe/bxe_elink.c

13470

media_types |= ((phy->media_type &

sys/dev/bxe/bxe_elink.c

13477

elink_phy_def_cfg(params, phy, phy_index);

sys/dev/bxe/bxe_elink.c

13724

elink_set_aer_mmd(params, &params->phy[0]);

sys/dev/bxe/bxe_elink.c

13725

elink_warpcore_reset_lane(sc, &params->phy[0], 0);

sys/dev/bxe/bxe_elink.c

13726

params->phy[ELINK_INT_PHY].config_loopback(

sys/dev/bxe/bxe_elink.c

13727

&params->phy[ELINK_INT_PHY],

sys/dev/bxe/bxe_elink.c

13753

struct elink_phy *int_phy = &params->phy[ELINK_INT_PHY];

sys/dev/bxe/bxe_elink.c

13791

if (params->phy[phy_index].config_loopback)

sys/dev/bxe/bxe_elink.c

13792

params->phy[phy_index].config_loopback(

sys/dev/bxe/bxe_elink.c

13793

&params->phy[phy_index],

sys/dev/bxe/bxe_elink.c

13836

struct elink_phy *phy = &params->phy[phy_idx];

sys/dev/bxe/bxe_elink.c

13837

if (phy->phy_specific_func) {

sys/dev/bxe/bxe_elink.c

13839

phy->phy_specific_func(phy, params, ELINK_PHY_INIT);

sys/dev/bxe/bxe_elink.c

13841

if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||

sys/dev/bxe/bxe_elink.c

13842

(phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||

sys/dev/bxe/bxe_elink.c

13843

(phy->media_type == ELINK_ETH_PHY_DA_TWINAX))

sys/dev/bxe/bxe_elink.c

13844

elink_verify_sfp_module(phy, params);

sys/dev/bxe/bxe_elink.c

14130

if (params->phy[phy_index].link_reset) {

sys/dev/bxe/bxe_elink.c

14132

&params->phy[phy_index]);

sys/dev/bxe/bxe_elink.c

14133

params->phy[phy_index].link_reset(

sys/dev/bxe/bxe_elink.c

14134

&params->phy[phy_index],

sys/dev/bxe/bxe_elink.c

14137

if (params->phy[phy_index].flags &

sys/dev/bxe/bxe_elink.c

14152

if (params->phy[ELINK_INT_PHY].link_reset)

sys/dev/bxe/bxe_elink.c

14153

params->phy[ELINK_INT_PHY].link_reset(

sys/dev/bxe/bxe_elink.c

14154

&params->phy[ELINK_INT_PHY], params);

sys/dev/bxe/bxe_elink.c

14235

struct elink_phy phy[PORT_MAX];

sys/dev/bxe/bxe_elink.c

14261

port_of_path, &phy[port]) !=

sys/dev/bxe/bxe_elink.c

14282

elink_cl45_write(sc, &phy[port],

sys/dev/bxe/bxe_elink.c

14291

if (phy[PORT_0].addr & 0x1) {

sys/dev/bxe/bxe_elink.c

14292

phy_blk[PORT_0] = &(phy[PORT_1]);

sys/dev/bxe/bxe_elink.c

14293

phy_blk[PORT_1] = &(phy[PORT_0]);

sys/dev/bxe/bxe_elink.c

14295

phy_blk[PORT_0] = &(phy[PORT_0]);

sys/dev/bxe/bxe_elink.c

14296

phy_blk[PORT_1] = &(phy[PORT_1]);

sys/dev/bxe/bxe_elink.c

14363

struct elink_phy phy;

sys/dev/bxe/bxe_elink.c

14386

port, &phy) !=

sys/dev/bxe/bxe_elink.c

14393

elink_cl45_write(sc, &phy,

sys/dev/bxe/bxe_elink.c

14458

struct elink_phy phy[PORT_MAX];

sys/dev/bxe/bxe_elink.c

14502

port_of_path, &phy[port]) !=

sys/dev/bxe/bxe_elink.c

14517

elink_cl45_write(sc, &phy[port],

sys/dev/bxe/bxe_elink.c

14523

if (phy[PORT_0].addr & 0x1) {

sys/dev/bxe/bxe_elink.c

14524

phy_blk[PORT_0] = &(phy[PORT_1]);

sys/dev/bxe/bxe_elink.c

14525

phy_blk[PORT_1] = &(phy[PORT_0]);

sys/dev/bxe/bxe_elink.c

14527

phy_blk[PORT_0] = &(phy[PORT_0]);

sys/dev/bxe/bxe_elink.c

14528

phy_blk[PORT_1] = &(phy[PORT_1]);

sys/dev/bxe/bxe_elink.c

14836

static void elink_sfp_tx_fault_detection(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

14872

if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {

sys/dev/bxe/bxe_elink.c

14881

struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

14885

elink_warpcore_enable_AN_KR2(phy, params, vars);

sys/dev/bxe/bxe_elink.c

14886

elink_warpcore_restart_AN_KR(phy, params);

sys/dev/bxe/bxe_elink.c

14891

struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

14907

sigdet = elink_warpcore_get_sigdet(phy, params);

sys/dev/bxe/bxe_elink.c

14910

elink_kr2_recovery(params, vars, phy);

sys/dev/bxe/bxe_elink.c

14916

lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

14917

CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,

sys/dev/bxe/bxe_elink.c

14919

elink_cl45_read(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

14921

elink_cl45_read(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

14923

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

14928

elink_kr2_recovery(params, vars, phy);

sys/dev/bxe/bxe_elink.c

14947

elink_kr2_recovery(params, vars, phy);

sys/dev/bxe/bxe_elink.c

14955

elink_disable_kr2(params, vars, phy);

sys/dev/bxe/bxe_elink.c

14957

elink_warpcore_restart_AN_KR(phy, params);

sys/dev/bxe/bxe_elink.c

14967

if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {

sys/dev/bxe/bxe_elink.c

14968

elink_set_aer_mmd(params, &params->phy[phy_idx]);

sys/dev/bxe/bxe_elink.c

14977

struct elink_phy *phy = &params->phy[ELINK_INT_PHY];

sys/dev/bxe/bxe_elink.c

14978

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

14979

if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&

sys/dev/bxe/bxe_elink.c

14980

(phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

14982

(phy->req_line_speed == ELINK_SPEED_20000))

sys/dev/bxe/bxe_elink.c

14983

elink_check_kr2_wa(params, vars, phy);

sys/dev/bxe/bxe_elink.c

14986

elink_warpcore_config_runtime(phy, params, vars);

sys/dev/bxe/bxe_elink.c

14993

if (elink_is_sfp_module_plugged(phy, params)) {

sys/dev/bxe/bxe_elink.c

14994

elink_sfp_tx_fault_detection(phy, params, vars);

sys/dev/bxe/bxe_elink.c

15013

struct elink_phy phy;

sys/dev/bxe/bxe_elink.c

15017

port, &phy)

sys/dev/bxe/bxe_elink.c

15022

fan_failure_det_req |= (phy.flags &

sys/dev/bxe/bxe_elink.c

15041

if (params->phy[phy_index].hw_reset) {

sys/dev/bxe/bxe_elink.c

15042

params->phy[phy_index].hw_reset(

sys/dev/bxe/bxe_elink.c

15043

&params->phy[phy_index],

sys/dev/bxe/bxe_elink.c

15045

params->phy[phy_index] = phy_null;

sys/dev/bxe/bxe_elink.c

15065

struct elink_phy phy;

sys/dev/bxe/bxe_elink.c

15069

shmem2_base, port, &phy)

sys/dev/bxe/bxe_elink.c

15074

if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {

sys/dev/bxe/bxe_elink.c

2250

params->phy[phy_index].mdio_ctrl);

sys/dev/bxe/bxe_elink.c

2543

if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {

sys/dev/bxe/bxe_elink.c

2574

(params->phy[ELINK_INT_PHY].supported &

sys/dev/bxe/bxe_elink.c

3413

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

3420

mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);

sys/dev/bxe/bxe_elink.c

3421

REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,

sys/dev/bxe/bxe_elink.c

3425

tmp = ((phy->addr << 21) | (reg << 16) | val |

sys/dev/bxe/bxe_elink.c

3428

REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);

sys/dev/bxe/bxe_elink.c

3433

tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);

sys/dev/bxe/bxe_elink.c

3443

REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);

sys/dev/bxe/bxe_elink.c

3448

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

3456

mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);

sys/dev/bxe/bxe_elink.c

3457

REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,

sys/dev/bxe/bxe_elink.c

3461

val = ((phy->addr << 21) | (reg << 16) |

sys/dev/bxe/bxe_elink.c

3464

REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);

sys/dev/bxe/bxe_elink.c

3469

val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);

sys/dev/bxe/bxe_elink.c

3482

REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);

sys/dev/bxe/bxe_elink.c

3489

static elink_status_t elink_cl45_read(struct bxe_softc *sc, struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

3496

if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {

sys/dev/bxe/bxe_elink.c

3499

elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);

sys/dev/bxe/bxe_elink.c

3502

if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)

sys/dev/bxe/bxe_elink.c

3503

elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,

sys/dev/bxe/bxe_elink.c

3506

val = ((phy->addr << 21) | (devad << 16) | reg |

sys/dev/bxe/bxe_elink.c

3509

REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);

sys/dev/bxe/bxe_elink.c

3514

val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);

sys/dev/bxe/bxe_elink.c

3528

val = ((phy->addr << 21) | (devad << 16) |

sys/dev/bxe/bxe_elink.c

3531

REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);

sys/dev/bxe/bxe_elink.c

3536

val = REG_RD(sc, phy->mdio_ctrl +

sys/dev/bxe/bxe_elink.c

3552

if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {

sys/dev/bxe/bxe_elink.c

3553

phy->flags ^= ELINK_FLAGS_DUMMY_READ;

sys/dev/bxe/bxe_elink.c

3554

if (phy->flags & ELINK_FLAGS_DUMMY_READ) {

sys/dev/bxe/bxe_elink.c

3556

elink_cl45_read(sc, phy, devad, 0xf, &temp_val);

sys/dev/bxe/bxe_elink.c

3560

if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)

sys/dev/bxe/bxe_elink.c

3561

elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,

sys/dev/bxe/bxe_elink.c

3566

static elink_status_t elink_cl45_write(struct bxe_softc *sc, struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

3573

if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {

sys/dev/bxe/bxe_elink.c

3576

elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);

sys/dev/bxe/bxe_elink.c

3579

if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)

sys/dev/bxe/bxe_elink.c

3580

elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,

sys/dev/bxe/bxe_elink.c

3584

tmp = ((phy->addr << 21) | (devad << 16) | reg |

sys/dev/bxe/bxe_elink.c

3587

REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);

sys/dev/bxe/bxe_elink.c

3592

tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);

sys/dev/bxe/bxe_elink.c

3605

tmp = ((phy->addr << 21) | (devad << 16) | val |

sys/dev/bxe/bxe_elink.c

3608

REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);

sys/dev/bxe/bxe_elink.c

3613

tmp = REG_RD(sc, phy->mdio_ctrl +

sys/dev/bxe/bxe_elink.c

3628

if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {

sys/dev/bxe/bxe_elink.c

3629

phy->flags ^= ELINK_FLAGS_DUMMY_READ;

sys/dev/bxe/bxe_elink.c

3630

if (phy->flags & ELINK_FLAGS_DUMMY_READ) {

sys/dev/bxe/bxe_elink.c

3632

elink_cl45_read(sc, phy, devad, 0xf, &temp_val);

sys/dev/bxe/bxe_elink.c

3635

if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)

sys/dev/bxe/bxe_elink.c

3636

elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,

sys/dev/bxe/bxe_elink.c

3779

static elink_status_t elink_eee_disable(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

3788

elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);

sys/dev/bxe/bxe_elink.c

3795

static elink_status_t elink_eee_advertise(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

3814

elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);

sys/dev/bxe/bxe_elink.c

3832

static void elink_eee_an_resolve(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

3841

elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);

sys/dev/bxe/bxe_elink.c

3842

elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);

sys/dev/bxe/bxe_elink.c

3992

static void elink_cl45_read_or_write(struct bxe_softc *sc, struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

3996

elink_cl45_read(sc, phy, devad, reg, &val);

sys/dev/bxe/bxe_elink.c

3997

elink_cl45_write(sc, phy, devad, reg, val | or_val);

sys/dev/bxe/bxe_elink.c

4001

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4005

elink_cl45_read(sc, phy, devad, reg, &val);

sys/dev/bxe/bxe_elink.c

4006

elink_cl45_write(sc, phy, devad, reg, val & and_val);

sys/dev/bxe/bxe_elink.c

4017

if (params->phy[phy_index].addr == phy_addr) {

sys/dev/bxe/bxe_elink.c

4019

&params->phy[phy_index], devad,

sys/dev/bxe/bxe_elink.c

4034

if (params->phy[phy_index].addr == phy_addr) {

sys/dev/bxe/bxe_elink.c

4036

&params->phy[phy_index], devad,

sys/dev/bxe/bxe_elink.c

4043

static uint8_t elink_get_warpcore_lane(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4099

struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

4108

offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?

sys/dev/bxe/bxe_elink.c

4109

(phy->addr + ser_lane) : 0;

sys/dev/bxe/bxe_elink.c

4112

aer_val = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

4119

if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)

sys/dev/bxe/bxe_elink.c

4126

CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,

sys/dev/bxe/bxe_elink.c

4168

static void elink_xgxs_specific_func(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4178

phy->def_md_devad);

sys/dev/bxe/bxe_elink.c

4197

elink_xgxs_specific_func(&params->phy[ELINK_INT_PHY], params,

sys/dev/bxe/bxe_elink.c

4201

static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4210

switch (phy->req_flow_ctrl) {

sys/dev/bxe/bxe_elink.c

4259

params->phy[actual_phy_idx].req_flow_ctrl =

sys/dev/bxe/bxe_elink.c

4262

params->phy[actual_phy_idx].req_line_speed =

sys/dev/bxe/bxe_elink.c

4265

params->phy[actual_phy_idx].speed_cap_mask =

sys/dev/bxe/bxe_elink.c

4268

params->phy[actual_phy_idx].req_duplex =

sys/dev/bxe/bxe_elink.c

4277

params->phy[actual_phy_idx].req_flow_ctrl,

sys/dev/bxe/bxe_elink.c

4278

params->phy[actual_phy_idx].req_line_speed,

sys/dev/bxe/bxe_elink.c

4279

params->phy[actual_phy_idx].speed_cap_mask);

sys/dev/bxe/bxe_elink.c

4284

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4290

elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);

sys/dev/bxe/bxe_elink.c

4295

elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);

sys/dev/bxe/bxe_elink.c

4307

elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);

sys/dev/bxe/bxe_elink.c

4310

static void elink_pause_resolve(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4357

static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4365

if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {

sys/dev/bxe/bxe_elink.c

4366

elink_cl22_read(sc, phy, 0x4, &ld_pause);

sys/dev/bxe/bxe_elink.c

4367

elink_cl22_read(sc, phy, 0x5, &lp_pause);

sys/dev/bxe/bxe_elink.c

4370

uint8_t lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

4372

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

4379

elink_cl45_read(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

4381

elink_cl45_read(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

4384

elink_cl45_read(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

4386

elink_cl45_read(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

4396

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

4399

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

4408

elink_pause_resolve(phy, params, vars, pause_result);

sys/dev/bxe/bxe_elink.c

4412

static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4418

if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {

sys/dev/bxe/bxe_elink.c

4420

if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)

sys/dev/bxe/bxe_elink.c

4421

elink_ext_phy_update_adv_fc(phy, params, vars);

sys/dev/bxe/bxe_elink.c

4423

vars->flow_ctrl = phy->req_flow_ctrl;

sys/dev/bxe/bxe_elink.c

4424

} else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)

sys/dev/bxe/bxe_elink.c

4428

elink_ext_phy_update_adv_fc(phy, params, vars);

sys/dev/bxe/bxe_elink.c

4461

static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4488

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4492

elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,

sys/dev/bxe/bxe_elink.c

4502

struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

4527

elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,

sys/dev/bxe/bxe_elink.c

4535

static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4541

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4543

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4547

static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4552

uint16_t lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

4553

CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,

sys/dev/bxe/bxe_elink.c

4555

elink_cl45_write(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

4559

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

4562

static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4581

elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,

sys/dev/bxe/bxe_elink.c

4584

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4588

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4593

(phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||

sys/dev/bxe/bxe_elink.c

4599

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);

sys/dev/bxe/bxe_elink.c

4603

(phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||

sys/dev/bxe/bxe_elink.c

4608

CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,

sys/dev/bxe/bxe_elink.c

4611

elink_cl45_write(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

4613

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

4618

lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

4619

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4623

if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)

sys/dev/bxe/bxe_elink.c

4624

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4627

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4630

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4635

elink_cl45_write(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

4639

elink_cl45_write(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

4649

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4656

elink_ext_phy_set_pause(params, phy, vars);

sys/dev/bxe/bxe_elink.c

4658

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4662

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4665

if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&

sys/dev/bxe/bxe_elink.c

4666

(phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||

sys/dev/bxe/bxe_elink.c

4667

(phy->req_line_speed == ELINK_SPEED_20000)) {

sys/dev/bxe/bxe_elink.c

4669

CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,

sys/dev/bxe/bxe_elink.c

4672

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4676

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4678

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

4680

elink_warpcore_enable_AN_KR2(phy, params, vars);

sys/dev/bxe/bxe_elink.c

4683

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4688

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4703

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4707

elink_disable_kr2(params, vars, phy);

sys/dev/bxe/bxe_elink.c

4711

elink_warpcore_restart_AN_KR(phy, params);

sys/dev/bxe/bxe_elink.c

4714

static void elink_warpcore_set_10G_KR(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4734

elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,

sys/dev/bxe/bxe_elink.c

4737

lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

4739

CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,

sys/dev/bxe/bxe_elink.c

4742

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4745

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4748

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4751

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4754

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

4756

elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,

sys/dev/bxe/bxe_elink.c

4759

elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,

sys/dev/bxe/bxe_elink.c

4763

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4767

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4771

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4775

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4777

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4782

static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4791

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4795

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4799

elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);

sys/dev/bxe/bxe_elink.c

4802

elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4806

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4810

elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4814

elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4819

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4821

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4826

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4882

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4886

lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

4887

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4890

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4895

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4899

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4902

elink_warpcore_set_lpi_passthrough(phy, params);

sys/dev/bxe/bxe_elink.c

4905

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4909

elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4913

elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4917

static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4923

CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,

sys/dev/bxe/bxe_elink.c

4927

elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4930

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

4932

elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,

sys/dev/bxe/bxe_elink.c

4934

elink_cl45_write(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

4937

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4941

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4945

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4948

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4951

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4955

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4957

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4961

CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,

sys/dev/bxe/bxe_elink.c

4964

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4967

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

4971

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

4975

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4979

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4982

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4985

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4988

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4991

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4994

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

4997

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5000

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5003

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5007

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5011

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5015

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5019

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5024

static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5033

elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5036

elink_warpcore_set_lpi_passthrough(phy, params);

sys/dev/bxe/bxe_elink.c

5038

if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {

sys/dev/bxe/bxe_elink.c

5040

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5045

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5048

switch (phy->req_line_speed) {

sys/dev/bxe/bxe_elink.c

5059

"Speed not supported: 0x%x\n", phy->req_line_speed);

sys/dev/bxe/bxe_elink.c

5063

if (phy->req_duplex == DUPLEX_FULL)

sys/dev/bxe/bxe_elink.c

5066

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5070

phy->req_line_speed);

sys/dev/bxe/bxe_elink.c

5071

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5077

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5084

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5089

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5091

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5096

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5101

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5108

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5113

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5119

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5121

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5126

static void elink_warpcore_clear_regs(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5149

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5153

elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,

sys/dev/bxe/bxe_elink.c

5156

lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

5157

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5201

static int elink_is_sfp_module_plugged(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5219

static int elink_warpcore_get_sigdet(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5225

lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

5227

elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,

sys/dev/bxe/bxe_elink.c

5233

static void elink_warpcore_config_runtime(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5247

uint16_t lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

5256

elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,

sys/dev/bxe/bxe_elink.c

5266

elink_warpcore_reset_lane(sc, phy, 1);

sys/dev/bxe/bxe_elink.c

5267

elink_warpcore_reset_lane(sc, phy, 0);

sys/dev/bxe/bxe_elink.c

5270

elink_cl45_write(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

5286

static void elink_warpcore_config_sfi(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5289

uint16_t lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

5291

elink_warpcore_clear_regs(phy, params, lane);

sys/dev/bxe/bxe_elink.c

5294

(phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {

sys/dev/bxe/bxe_elink.c

5296

elink_warpcore_set_10G_XFI(phy, params, 0);

sys/dev/bxe/bxe_elink.c

5299

elink_warpcore_set_sgmii_speed(phy, params, 1, 0);

sys/dev/bxe/bxe_elink.c

5304

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5320

if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)

sys/dev/bxe/bxe_elink.c

5324

static void elink_warpcore_config_init(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5331

uint16_t lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

5339

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

5340

elink_warpcore_reset_lane(sc, phy, 1);

sys/dev/bxe/bxe_elink.c

5343

(phy->req_line_speed &&

sys/dev/bxe/bxe_elink.c

5344

((phy->req_line_speed == ELINK_SPEED_100) ||

sys/dev/bxe/bxe_elink.c

5345

(phy->req_line_speed == ELINK_SPEED_10)))) {

sys/dev/bxe/bxe_elink.c

5348

elink_warpcore_clear_regs(phy, params, lane);

sys/dev/bxe/bxe_elink.c

5349

elink_warpcore_set_sgmii_speed(phy, params, 0, 1);

sys/dev/bxe/bxe_elink.c

5355

elink_warpcore_enable_AN_KR(phy, params, vars);

sys/dev/bxe/bxe_elink.c

5358

elink_warpcore_set_10G_KR(phy, params, vars);

sys/dev/bxe/bxe_elink.c

5363

elink_warpcore_clear_regs(phy, params, lane);

sys/dev/bxe/bxe_elink.c

5366

elink_warpcore_set_10G_XFI(phy, params, 1);

sys/dev/bxe/bxe_elink.c

5375

elink_warpcore_set_sgmii_speed(phy,

sys/dev/bxe/bxe_elink.c

5390

if (elink_is_sfp_module_plugged(phy, params))

sys/dev/bxe/bxe_elink.c

5391

elink_sfp_module_detection(phy, params);

sys/dev/bxe/bxe_elink.c

5394

phy, 1);

sys/dev/bxe/bxe_elink.c

5397

elink_warpcore_config_sfi(phy, params);

sys/dev/bxe/bxe_elink.c

5406

elink_warpcore_set_20G_DXGXS(sc, phy, lane);

sys/dev/bxe/bxe_elink.c

5409

elink_sfp_module_detection(phy, params);

sys/dev/bxe/bxe_elink.c

5413

elink_warpcore_enable_AN_KR(phy, params, vars);

sys/dev/bxe/bxe_elink.c

5416

elink_warpcore_set_20G_force_KR2(phy, params);

sys/dev/bxe/bxe_elink.c

5428

elink_warpcore_reset_lane(sc, phy, 0);

sys/dev/bxe/bxe_elink.c

5432

static void elink_warpcore_link_reset(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5437

elink_sfp_e3_set_transmitter(params, phy, 0);

sys/dev/bxe/bxe_elink.c

5439

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

5441

elink_warpcore_reset_lane(sc, phy, 1);

sys/dev/bxe/bxe_elink.c

5445

elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5448

elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5452

CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,

sys/dev/bxe/bxe_elink.c

5455

elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5459

elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5461

lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

5463

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5466

if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)

sys/dev/bxe/bxe_elink.c

5468

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5471

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5475

if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {

sys/dev/bxe/bxe_elink.c

5480

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5483

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

5487

static void elink_set_warpcore_loopback(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5494

params->loopback_mode, phy->req_line_speed);

sys/dev/bxe/bxe_elink.c

5496

if (phy->req_line_speed < ELINK_SPEED_10000 ||

sys/dev/bxe/bxe_elink.c

5497

phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {

sys/dev/bxe/bxe_elink.c

5501

CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,

sys/dev/bxe/bxe_elink.c

5504

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5508

lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

5509

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5512

if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)

sys/dev/bxe/bxe_elink.c

5514

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5519

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

5522

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5525

elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

5670

params->phy[ELINK_INT_PHY].media_type =

sys/dev/bxe/bxe_elink.c

5673

params->phy[ELINK_EXT_PHY1].media_type =

sys/dev/bxe/bxe_elink.c

5676

params->phy[ELINK_EXT_PHY2].media_type =

sys/dev/bxe/bxe_elink.c

5707

struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

5716

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5721

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5728

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5734

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5739

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5752

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5772

struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

5788

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5795

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5801

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5807

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5813

static void elink_set_parallel_detection(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5818

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5822

if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)

sys/dev/bxe/bxe_elink.c

5827

phy->speed_cap_mask, control2);

sys/dev/bxe/bxe_elink.c

5828

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5833

if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&

sys/dev/bxe/bxe_elink.c

5834

(phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

5838

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5843

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5852

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5858

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5866

static void elink_set_autoneg(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5875

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5886

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5892

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5903

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5908

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5921

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5928

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5934

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5942

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5946

if (phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

5949

if (phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

5953

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5964

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5970

static void elink_program_serdes(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

5978

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5984

if (phy->req_duplex == DUPLEX_FULL)

sys/dev/bxe/bxe_elink.c

5986

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

5993

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6013

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6019

static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6026

if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)

sys/dev/bxe/bxe_elink.c

6028

if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)

sys/dev/bxe/bxe_elink.c

6030

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6034

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6039

static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6047

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6050

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6055

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6060

static void elink_restart_autoneg(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6071

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6076

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6084

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6091

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6100

static void elink_initialize_sgmii_process(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6109

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6118

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6128

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6156

if (phy->req_duplex == DUPLEX_FULL)

sys/dev/bxe/bxe_elink.c

6159

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6166

elink_restart_autoneg(phy, params, 0);

sys/dev/bxe/bxe_elink.c

6172

static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6177

if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)

sys/dev/bxe/bxe_elink.c

6179

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6183

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6193

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6206

static void elink_update_adv_fc(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6221

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6225

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6235

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6239

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6249

elink_pause_resolve(phy, params, vars, pause_result);

sys/dev/bxe/bxe_elink.c

6253

static void elink_flow_ctrl_resolve(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6262

if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {

sys/dev/bxe/bxe_elink.c

6264

if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)

sys/dev/bxe/bxe_elink.c

6265

elink_update_adv_fc(phy, params, vars, gp_status);

sys/dev/bxe/bxe_elink.c

6267

vars->flow_ctrl = phy->req_flow_ctrl;

sys/dev/bxe/bxe_elink.c

6268

} else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)

sys/dev/bxe/bxe_elink.c

6272

if (elink_direct_parallel_detect_used(phy, params)) {

sys/dev/bxe/bxe_elink.c

6276

elink_update_adv_fc(phy, params, vars, gp_status);

sys/dev/bxe/bxe_elink.c

6281

static void elink_check_fallback_to_cl37(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6288

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6296

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6303

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6319

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6340

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6345

elink_restart_autoneg(phy, params, 0);

sys/dev/bxe/bxe_elink.c

6349

static void elink_xgxs_an_resolve(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6358

if (elink_direct_parallel_detect_used(phy, params))

sys/dev/bxe/bxe_elink.c

6362

static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6370

if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)

sys/dev/bxe/bxe_elink.c

6455

static elink_status_t elink_link_settings_status(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6465

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6484

rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,

sys/dev/bxe/bxe_elink.c

6492

elink_flow_ctrl_resolve(phy, params, vars, gp_status);

sys/dev/bxe/bxe_elink.c

6493

if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)

sys/dev/bxe/bxe_elink.c

6494

elink_xgxs_an_resolve(phy, params, vars,

sys/dev/bxe/bxe_elink.c

6498

if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&

sys/dev/bxe/bxe_elink.c

6501

elink_check_fallback_to_cl37(phy, params);

sys/dev/bxe/bxe_elink.c

6510

CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,

sys/dev/bxe/bxe_elink.c

6521

CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,

sys/dev/bxe/bxe_elink.c

6537

static elink_status_t elink_warpcore_read_status(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6545

lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

6548

(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {

sys/dev/bxe/bxe_elink.c

6549

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

6551

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

6556

} else if ((phy->req_line_speed > ELINK_SPEED_10000) &&

sys/dev/bxe/bxe_elink.c

6557

(phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {

sys/dev/bxe/bxe_elink.c

6559

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

6561

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

6567

elink_ext_phy_resolve_fc(phy, params, vars);

sys/dev/bxe/bxe_elink.c

6569

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

6578

if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {

sys/dev/bxe/bxe_elink.c

6580

elink_cl45_read(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

6582

elink_cl45_read(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

6590

if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {

sys/dev/bxe/bxe_elink.c

6592

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

6600

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

6609

elink_ext_phy_resolve_fc(phy, params, vars);

sys/dev/bxe/bxe_elink.c

6621

elink_cl45_read(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

6633

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

6649

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

6652

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

6663

rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,

sys/dev/bxe/bxe_elink.c

6667

if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&

sys/dev/bxe/bxe_elink.c

6668

(!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))

sys/dev/bxe/bxe_elink.c

6678

struct elink_phy *phy = &params->phy[ELINK_INT_PHY];

sys/dev/bxe/bxe_elink.c

6684

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6698

CL22_RD_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6707

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6761

static void elink_set_preemphasis(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6770

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6773

phy->rx_preemphasis[i]);

sys/dev/bxe/bxe_elink.c

6778

CL22_WR_OVER_CL45(sc, phy,

sys/dev/bxe/bxe_elink.c

6781

phy->tx_preemphasis[i]);

sys/dev/bxe/bxe_elink.c

6785

static void elink_xgxs_config_init(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6796

elink_set_preemphasis(phy, params);

sys/dev/bxe/bxe_elink.c

6805

elink_set_autoneg(phy, params, vars, 0);

sys/dev/bxe/bxe_elink.c

6808

elink_program_serdes(phy, params, vars);

sys/dev/bxe/bxe_elink.c

6814

elink_set_brcm_cl37_advertisement(phy, params);

sys/dev/bxe/bxe_elink.c

6817

elink_set_ieee_aneg_advertisement(phy, params,

sys/dev/bxe/bxe_elink.c

6821

elink_set_autoneg(phy, params, vars, enable_cl73);

sys/dev/bxe/bxe_elink.c

6824

elink_restart_autoneg(phy, params, enable_cl73);

sys/dev/bxe/bxe_elink.c

6830

elink_initialize_sgmii_process(phy, params, vars);

sys/dev/bxe/bxe_elink.c

6834

static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6840

if ((phy->req_line_speed &&

sys/dev/bxe/bxe_elink.c

6841

((phy->req_line_speed == ELINK_SPEED_100) ||

sys/dev/bxe/bxe_elink.c

6842

(phy->req_line_speed == ELINK_SPEED_10))) ||

sys/dev/bxe/bxe_elink.c

6843

(!phy->req_line_speed &&

sys/dev/bxe/bxe_elink.c

6844

(phy->speed_cap_mask >=

sys/dev/bxe/bxe_elink.c

6846

(phy->speed_cap_mask <

sys/dev/bxe/bxe_elink.c

6848

(phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))

sys/dev/bxe/bxe_elink.c

6853

elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);

sys/dev/bxe/bxe_elink.c

6854

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

6855

if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)

sys/dev/bxe/bxe_elink.c

6856

elink_set_master_ln(params, phy);

sys/dev/bxe/bxe_elink.c

6858

rc = elink_reset_unicore(params, phy, 0);

sys/dev/bxe/bxe_elink.c

6863

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

6865

if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {

sys/dev/bxe/bxe_elink.c

6866

elink_set_master_ln(params, phy);

sys/dev/bxe/bxe_elink.c

6867

elink_set_swap_lanes(params, phy);

sys/dev/bxe/bxe_elink.c

6874

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

6880

if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)

sys/dev/bxe/bxe_elink.c

6881

elink_cl22_read(sc, phy,

sys/dev/bxe/bxe_elink.c

6884

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

6916

params->phy[ELINK_INT_PHY].type !=

sys/dev/bxe/bxe_elink.c

6926

params->phy[ELINK_INT_PHY].type !=

sys/dev/bxe/bxe_elink.c

7082

spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);

sys/dev/bxe/bxe_elink.c

7084

if (params->phy[ELINK_EXT_PHY1].format_fw_ver) {

sys/dev/bxe/bxe_elink.c

7085

status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver,

sys/dev/bxe/bxe_elink.c

7091

(params->phy[ELINK_EXT_PHY2].ver_addr != 0)) {

sys/dev/bxe/bxe_elink.c

7092

spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);

sys/dev/bxe/bxe_elink.c

7093

if (params->phy[ELINK_EXT_PHY2].format_fw_ver) {

sys/dev/bxe/bxe_elink.c

7097

status |= params->phy[ELINK_EXT_PHY2].format_fw_ver(

sys/dev/bxe/bxe_elink.c

7108

static void elink_set_xgxs_loopback(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

7114

if (phy->req_line_speed != ELINK_SPEED_1000) {

sys/dev/bxe/bxe_elink.c

7128

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

7134

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

7141

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

7151

elink_cl45_read(sc, phy, 5,

sys/dev/bxe/bxe_elink.c

7155

elink_cl45_write(sc, phy, 5,

sys/dev/bxe/bxe_elink.c

7178

if (params->phy[phy_idx].set_link_led) {

sys/dev/bxe/bxe_elink.c

7179

params->phy[phy_idx].set_link_led(

sys/dev/bxe/bxe_elink.c

7180

&params->phy[phy_idx], params, mode);

sys/dev/bxe/bxe_elink.c

7197

if (params->phy[ELINK_EXT_PHY1].type ==

sys/dev/bxe/bxe_elink.c

7215

if (((params->phy[ELINK_EXT_PHY1].type ==

sys/dev/bxe/bxe_elink.c

7217

(params->phy[ELINK_EXT_PHY1].type ==

sys/dev/bxe/bxe_elink.c

7253

} else if ((params->phy[ELINK_EXT_PHY1].type ==

sys/dev/bxe/bxe_elink.c

7323

struct elink_phy *int_phy = &params->phy[ELINK_INT_PHY];

sys/dev/bxe/bxe_elink.c

7373

ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status(

sys/dev/bxe/bxe_elink.c

7374

&params->phy[ELINK_EXT_PHY1],

sys/dev/bxe/bxe_elink.c

7380

serdes_phy_type = ((params->phy[phy_index].media_type ==

sys/dev/bxe/bxe_elink.c

7382

(params->phy[phy_index].media_type ==

sys/dev/bxe/bxe_elink.c

7384

(params->phy[phy_index].media_type ==

sys/dev/bxe/bxe_elink.c

7386

(params->phy[phy_index].media_type ==

sys/dev/bxe/bxe_elink.c

7391

if (params->phy[phy_index].read_status) {

sys/dev/bxe/bxe_elink.c

7393

params->phy[phy_index].read_status(

sys/dev/bxe/bxe_elink.c

7394

&params->phy[phy_index],

sys/dev/bxe/bxe_elink.c

7415

vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;

sys/dev/bxe/bxe_elink.c

7422

elink_prepare_xgxs(&params->phy[ELINK_INT_PHY], params, vars);

sys/dev/bxe/bxe_elink.c

7428

(params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||

sys/dev/bxe/bxe_elink.c

7430

struct elink_phy *phy = &params->phy[ELINK_INT_PHY];

sys/dev/bxe/bxe_elink.c

7434

elink_set_parallel_detection(phy, params);

sys/dev/bxe/bxe_elink.c

7435

if (params->phy[ELINK_INT_PHY].config_init)

sys/dev/bxe/bxe_elink.c

7436

params->phy[ELINK_INT_PHY].config_init(phy, params, vars);

sys/dev/bxe/bxe_elink.c

7442

vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;

sys/dev/bxe/bxe_elink.c

7446

if (params->phy[ELINK_INT_PHY].supported &

sys/dev/bxe/bxe_elink.c

7457

if (params->phy[phy_index].supported &

sys/dev/bxe/bxe_elink.c

7468

params->phy[phy_index].config_init(

sys/dev/bxe/bxe_elink.c

7469

&params->phy[phy_index],

sys/dev/bxe/bxe_elink.c

7483

static void elink_int_link_reset(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

7491

static void elink_common_ext_link_reset(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

757

typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

7639

if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {

sys/dev/bxe/bxe_elink.c

7705

elink_set_aer_mmd(params, &params->phy[ELINK_INT_PHY]);

sys/dev/bxe/bxe_elink.c

7733

struct elink_phy *phy = &params->phy[phy_index];

sys/dev/bxe/bxe_elink.c

7734

if (!phy->read_status)

sys/dev/bxe/bxe_elink.c

7737

cur_link_up = phy->read_status(phy, params,

sys/dev/bxe/bxe_elink.c

7791

if (params->phy[ELINK_INT_PHY].read_status)

sys/dev/bxe/bxe_elink.c

7792

params->phy[ELINK_INT_PHY].read_status(

sys/dev/bxe/bxe_elink.c

7793

&params->phy[ELINK_INT_PHY],

sys/dev/bxe/bxe_elink.c

7813

if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {

sys/dev/bxe/bxe_elink.c

7816

params->phy[ELINK_EXT_PHY2].phy_specific_func(

sys/dev/bxe/bxe_elink.c

7817

&params->phy[ELINK_EXT_PHY2],

sys/dev/bxe/bxe_elink.c

7824

if (params->phy[active_external_phy].supported &

sys/dev/bxe/bxe_elink.c

7851

if (params->phy[phy_index].flags &

sys/dev/bxe/bxe_elink.c

7899

params->phy[ELINK_EXT_PHY1].flags &

sys/dev/bxe/bxe_elink.c

7901

if (!(params->phy[ELINK_EXT_PHY1].flags &

sys/dev/bxe/bxe_elink.c

7910

if (params->phy[ELINK_INT_PHY].config_init)

sys/dev/bxe/bxe_elink.c

7911

params->phy[ELINK_INT_PHY].config_init(

sys/dev/bxe/bxe_elink.c

7912

&params->phy[ELINK_INT_PHY], params,

sys/dev/bxe/bxe_elink.c

7974

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

7979

elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,

sys/dev/bxe/bxe_elink.c

7981

elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,

sys/dev/bxe/bxe_elink.c

7984

phy->ver_addr);

sys/dev/bxe/bxe_elink.c

7988

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

7992

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

7995

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8007

static void elink_8073_resolve_fc(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8012

if (phy->req_line_speed == ELINK_SPEED_10 ||

sys/dev/bxe/bxe_elink.c

8013

phy->req_line_speed == ELINK_SPEED_100) {

sys/dev/bxe/bxe_elink.c

8014

vars->flow_ctrl = phy->req_flow_ctrl;

sys/dev/bxe/bxe_elink.c

8018

if (elink_ext_phy_resolve_fc(phy, params, vars) &&

sys/dev/bxe/bxe_elink.c

8023

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8027

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8035

elink_pause_resolve(phy, params, vars, pause_result);

sys/dev/bxe/bxe_elink.c

8041

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8050

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8056

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8061

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8066

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8072

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8092

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8095

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8101

((fw_msgout & 0xff) != 0x03 && (phy->type ==

sys/dev/bxe/bxe_elink.c

8105

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8108

elink_save_bcm_spirom_ver(sc, phy, port);

sys/dev/bxe/bxe_elink.c

8121

static elink_status_t elink_8073_is_snr_needed(struct bxe_softc *sc, struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

8127

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8136

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8147

static elink_status_t elink_8073_xaui_wa(struct bxe_softc *sc, struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

8151

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8166

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8185

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8203

static void elink_807x_force_10G(struct bxe_softc *sc, struct elink_phy *phy)

sys/dev/bxe/bxe_elink.c

8206

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8208

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8210

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8212

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8217

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8222

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8227

elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);

sys/dev/bxe/bxe_elink.c

8246

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8251

static void elink_8073_specific_func(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8259

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8261

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8267

static elink_status_t elink_8073_config_init(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8287

elink_8073_specific_func(phy, params, ELINK_PHY_INIT);

sys/dev/bxe/bxe_elink.c

8288

elink_8073_set_pause_cl37(params, phy, vars);

sys/dev/bxe/bxe_elink.c

8290

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8293

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8303

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8306

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8319

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8322

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8328

elink_807x_force_10G(sc, phy);

sys/dev/bxe/bxe_elink.c

8332

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8335

if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {

sys/dev/bxe/bxe_elink.c

8336

if (phy->req_line_speed == ELINK_SPEED_10000) {

sys/dev/bxe/bxe_elink.c

8338

} else if (phy->req_line_speed == ELINK_SPEED_2500) {

sys/dev/bxe/bxe_elink.c

8347

if (phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

8352

if (phy->speed_cap_mask &

sys/dev/bxe/bxe_elink.c

8359

elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);

sys/dev/bxe/bxe_elink.c

8360

elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);

sys/dev/bxe/bxe_elink.c

8362

if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&

sys/dev/bxe/bxe_elink.c

8363

(phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||

sys/dev/bxe/bxe_elink.c

8364

(phy->req_line_speed == ELINK_SPEED_2500)) {

sys/dev/bxe/bxe_elink.c

8367

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8380

elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);

sys/dev/bxe/bxe_elink.c

8383

elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);

sys/dev/bxe/bxe_elink.c

8384

elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,

sys/dev/bxe/bxe_elink.c

8385

(tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?

sys/dev/bxe/bxe_elink.c

8389

elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);

sys/dev/bxe/bxe_elink.c

8395

if (elink_8073_is_snr_needed(sc, phy))

sys/dev/bxe/bxe_elink.c

8396

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8401

elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);

sys/dev/bxe/bxe_elink.c

8403

elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);

sys/dev/bxe/bxe_elink.c

8405

elink_ext_phy_set_pause(params, phy, vars);

sys/dev/bxe/bxe_elink.c

8409

elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);

sys/dev/bxe/bxe_elink.c

8415

static uint8_t elink_8073_read_status(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8425

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8431

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8433

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8437

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8441

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8447

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8451

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8453

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8459

((phy->req_line_speed != ELINK_SPEED_10000))) {

sys/dev/bxe/bxe_elink.c

8460

if (elink_8073_xaui_wa(sc, phy) != 0)

sys/dev/bxe/bxe_elink.c

8463

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8465

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8469

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8471

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8477

if (link_up && elink_8073_is_snr_needed(sc, phy)) {

sys/dev/bxe/bxe_elink.c

8482

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8487

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8491

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8522

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8535

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8540

elink_ext_phy_10G_an_resolve(sc, phy, vars);

sys/dev/bxe/bxe_elink.c

8541

elink_8073_resolve_fc(phy, params, vars);

sys/dev/bxe/bxe_elink.c

8546

elink_cl45_read(sc, phy, MDIO_AN_DEVAD,

sys/dev/bxe/bxe_elink.c

8560

static void elink_8073_link_reset(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8579

static elink_status_t elink_8705_config_init(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8590

elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);

sys/dev/bxe/bxe_elink.c

8591

elink_wait_reset_complete(sc, phy, params);

sys/dev/bxe/bxe_elink.c

8593

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8595

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8597

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8599

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8606

static uint8_t elink_8705_read_status(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8614

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8618

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8622

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8625

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8627

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8634

elink_ext_phy_resolve_fc(phy, params, vars);

sys/dev/bxe/bxe_elink.c

8643

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8660

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8680

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8698

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8708

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8737

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8743

elink_sfp_e3_set_transmitter(params, phy, tx_en);

sys/dev/bxe/bxe_elink.c

8745

elink_sfp_e1e2_set_transmitter(params, phy, tx_en);

sys/dev/bxe/bxe_elink.c

8748

static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8762

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8767

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8772

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8778

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8797

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8804

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8836

static elink_status_t elink_warpcore_read_sfp_module_eeprom(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8879

static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8897

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8903

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8909

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8915

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8920

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8926

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

8937

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8956

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8963

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

8974

elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

8988

switch (phy->type) {

sys/dev/bxe/bxe_elink.c

9006

rc = read_func(phy, params, dev_addr, addr, xfer_size,

sys/dev/bxe/bxe_elink.c

9015

static elink_status_t elink_get_edc_mode(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9023

phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;

sys/dev/bxe/bxe_elink.c

9025

if (elink_read_sfp_module_eeprom(phy,

sys/dev/bxe/bxe_elink.c

9042

phy->media_type = ELINK_ETH_PHY_DA_TWINAX;

sys/dev/bxe/bxe_elink.c

9050

if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)

sys/dev/bxe/bxe_elink.c

9084

phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;

sys/dev/bxe/bxe_elink.c

9085

if (phy->req_line_speed != ELINK_SPEED_1000) {

sys/dev/bxe/bxe_elink.c

9087

phy->req_line_speed = ELINK_SPEED_1000;

sys/dev/bxe/bxe_elink.c

9103

elink_sfp_set_transmitter(params, phy, 0);

sys/dev/bxe/bxe_elink.c

9105

elink_sfp_set_transmitter(params, phy, 1);

sys/dev/bxe/bxe_elink.c

9111

if (params->phy[idx].type == phy->type) {

sys/dev/bxe/bxe_elink.c

9116

phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;

sys/dev/bxe/bxe_elink.c

9117

phy->req_line_speed = params->req_line_speed[cfg_idx];

sys/dev/bxe/bxe_elink.c

9131

if (&(params->phy[phy_idx]) == phy) {

sys/dev/bxe/bxe_elink.c

9134

media_types |= ((phy->media_type &

sys/dev/bxe/bxe_elink.c

9143

if (elink_read_sfp_module_eeprom(phy,

sys/dev/bxe/bxe_elink.c

9164

static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9172

phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;

sys/dev/bxe/bxe_elink.c

9202

fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);

sys/dev/bxe/bxe_elink.c

9210

if (elink_read_sfp_module_eeprom(phy,

sys/dev/bxe/bxe_elink.c

9219

if (elink_read_sfp_module_eeprom(phy,

sys/dev/bxe/bxe_elink.c

9234

phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;

sys/dev/bxe/bxe_elink.c

9238

static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9251

if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)

sys/dev/bxe/bxe_elink.c

9253

phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val,

sys/dev/bxe/bxe_elink.c

9256

rc = elink_read_sfp_module_eeprom(phy, params,

sys/dev/bxe/bxe_elink.c

9267

rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,

sys/dev/bxe/bxe_elink.c

9273

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9288

if (phy->flags & ELINK_FLAGS_NOC)

sys/dev/bxe/bxe_elink.c

9298

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9305

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9310

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9319

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9333

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9337

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9341

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9345

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9354

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9359

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9364

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9369

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9374

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9379

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9387

static void elink_8727_specific_func(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9395

elink_sfp_set_transmitter(params, phy, 0);

sys/dev/bxe/bxe_elink.c

9398

if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))

sys/dev/bxe/bxe_elink.c

9399

elink_sfp_set_transmitter(params, phy, 1);

sys/dev/bxe/bxe_elink.c

9402

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9405

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9408

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9411

elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,

sys/dev/bxe/bxe_elink.c

9415

if (phy->flags & ELINK_FLAGS_NOC)

sys/dev/bxe/bxe_elink.c

9420

if (!(phy->flags & ELINK_FLAGS_NOC))

sys/dev/bxe/bxe_elink.c

9422

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

948

static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9495

static void elink_warpcore_hw_reset(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9510

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9516

switch (phy->type) {

sys/dev/bxe/bxe_elink.c

9519

elink_8727_power_module(params->sc, phy, power);

sys/dev/bxe/bxe_elink.c

9529

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9536

uint8_t lane = elink_get_warpcore_lane(phy, params);

sys/dev/bxe/bxe_elink.c

9538

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

9556

elink_cl45_write(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

9559

elink_cl45_read(sc, phy, MDIO_WC_DEVAD,

sys/dev/bxe/bxe_elink.c

9563

elink_warpcore_reset_lane(sc, phy, 1);

sys/dev/bxe/bxe_elink.c

9564

elink_warpcore_reset_lane(sc, phy, 0);

sys/dev/bxe/bxe_elink.c

9569

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9572

switch (phy->type) {

sys/dev/bxe/bxe_elink.c

9574

elink_8726_set_limiting_mode(params->sc, phy, edc_mode);

sys/dev/bxe/bxe_elink.c

9578

elink_8727_set_limiting_mode(params->sc, phy, edc_mode);

sys/dev/bxe/bxe_elink.c

9581

elink_warpcore_set_limiting_mode(params, phy, edc_mode);

sys/dev/bxe/bxe_elink.c

9586

elink_status_t elink_sfp_module_detection(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9597

elink_sfp_set_transmitter(params, phy, 1);

sys/dev/bxe/bxe_elink.c

9601

elink_power_sfp_module(params, phy, 1);

sys/dev/bxe/bxe_elink.c

9602

if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {

sys/dev/bxe/bxe_elink.c

9605

} else if (elink_verify_sfp_module(phy, params) != 0) {

sys/dev/bxe/bxe_elink.c

9617

elink_power_sfp_module(params, phy, 0);

sys/dev/bxe/bxe_elink.c

9628

elink_set_limiting_mode(params, phy, edc_mode);

sys/dev/bxe/bxe_elink.c

9636

elink_sfp_set_transmitter(params, phy, 0);

sys/dev/bxe/bxe_elink.c

9644

struct elink_phy *phy;

sys/dev/bxe/bxe_elink.c

9648

phy = &params->phy[ELINK_INT_PHY];

sys/dev/bxe/bxe_elink.c

9650

elink_sfp_set_transmitter(params, phy, 1);

sys/dev/bxe/bxe_elink.c

9652

phy = &params->phy[ELINK_EXT_PHY1];

sys/dev/bxe/bxe_elink.c

9670

elink_set_aer_mmd(params, phy);

sys/dev/bxe/bxe_elink.c

9672

elink_power_sfp_module(params, phy, 1);

sys/dev/bxe/bxe_elink.c

9676

if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {

sys/dev/bxe/bxe_elink.c

9677

elink_sfp_module_detection(phy, params);

sys/dev/bxe/bxe_elink.c

9684

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9691

elink_warpcore_reset_lane(sc, phy, 1);

sys/dev/bxe/bxe_elink.c

9692

elink_warpcore_config_sfi(phy, params);

sys/dev/bxe/bxe_elink.c

9693

elink_warpcore_reset_lane(sc, phy, 0);

sys/dev/bxe/bxe_elink.c

9706

phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;

sys/dev/bxe/bxe_elink.c

9714

struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9719

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9722

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9726

elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);

sys/dev/bxe/bxe_elink.c

9731

elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);

sys/dev/bxe/bxe_elink.c

9736

static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9745

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9748

elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,

sys/dev/bxe/bxe_elink.c

9752

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9754

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9758

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9760

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9762

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9764

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9778

elink_ext_phy_resolve_fc(phy, params, vars);

sys/dev/bxe/bxe_elink.c

9784

elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,

sys/dev/bxe/bxe_elink.c

9786

elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,

sys/dev/bxe/bxe_elink.c

9798

static uint8_t elink_8706_config_init(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9810

elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);

sys/dev/bxe/bxe_elink.c

9811

elink_wait_reset_complete(sc, phy, params);

sys/dev/bxe/bxe_elink.c

9815

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9830

elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);

sys/dev/bxe/bxe_elink.c

9834

val |= (phy->rx_preemphasis[i] & 0x7);

sys/dev/bxe/bxe_elink.c

9837

elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);

sys/dev/bxe/bxe_elink.c

9841

if (phy->req_line_speed == ELINK_SPEED_10000) {

sys/dev/bxe/bxe_elink.c

9844

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9847

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9851

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9858

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9862

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9865

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9868

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9872

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9874

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9877

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9881

elink_save_bcm_spirom_ver(sc, phy, params->port);

sys/dev/bxe/bxe_elink.c

9894

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9897

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9904

static elink_status_t elink_8706_read_status(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9908

return elink_8706_8726_read_status(phy, params, vars);

sys/dev/bxe/bxe_elink.c

9914

static void elink_8726_config_loopback(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9919

elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);

sys/dev/bxe/bxe_elink.c

9922

static void elink_8726_external_rom_boot(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9930

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9934

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9939

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9943

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9952

elink_cl45_write(sc, phy,

sys/dev/bxe/bxe_elink.c

9957

elink_save_bcm_spirom_ver(sc, phy, params->port);

sys/dev/bxe/bxe_elink.c

9960

static uint8_t elink_8726_read_status(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9966

uint8_t link_up = elink_8706_8726_read_status(phy, params, vars);

sys/dev/bxe/bxe_elink.c

9968

elink_cl45_read(sc, phy,

sys/dev/bxe/bxe_elink.c

9981

static elink_status_t elink_8726_config_init(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.c

9988

elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);

sys/dev/bxe/bxe_elink.c

9989

elink_wait_reset_complete(sc, phy, params);

sys/dev/bxe/bxe_elink.c

9991

elink_8726_external_rom_boot(phy, params);

sys/dev/bxe/bxe_elink.c

9998

elink_sfp_module_detection(phy, params);

sys/dev/bxe/bxe_elink.h

242

typedef uint8_t (*config_init_t)(struct elink_phy *phy, struct elink_params *params,

sys/dev/bxe/bxe_elink.h

244

typedef uint8_t (*read_status_t)(struct elink_phy *phy, struct elink_params *params,

sys/dev/bxe/bxe_elink.h

246

typedef void (*link_reset_t)(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.h

248

typedef void (*config_loopback_t)(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.h

251

typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params);

sys/dev/bxe/bxe_elink.h

252

typedef void (*set_link_led_t)(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.h

254

typedef void (*phy_specific_func_t)(struct elink_phy *phy,

sys/dev/bxe/bxe_elink.h

424

struct elink_phy phy[ELINK_MAX_PHYS];

sys/dev/bxe/bxe_elink.h

573

void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy);

sys/dev/bxe/bxe_elink.h

576

elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,

sys/dev/cadence/if_cgem.c

1373

cgem_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/cadence/if_cgem.c

1380

(phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) |

sys/dev/cadence/if_cgem.c

1406

cgem_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/cadence/if_cgem.c

1413

(phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) |

sys/dev/cas/if_cas.c

148

static int cas_mii_readreg(device_t dev, int phy, int reg);

sys/dev/cas/if_cas.c

150

static int cas_mii_writereg(device_t dev, int phy, int reg, int val);

sys/dev/cas/if_cas.c

2135

cas_mii_readreg(device_t dev, int phy, int reg)

sys/dev/cas/if_cas.c

2142

printf("%s: phy %d reg %d\n", __func__, phy, reg);

sys/dev/cas/if_cas.c

2175

(phy << CAS_MIF_FRAME_PHY_SHFT) |

sys/dev/cas/if_cas.c

2193

cas_mii_writereg(device_t dev, int phy, int reg, int val)

sys/dev/cas/if_cas.c

2200

printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__);

sys/dev/cas/if_cas.c

2253

(phy << CAS_MIF_FRAME_PHY_SHFT) |

sys/dev/cas/if_cas.c

2643

u_int j, k, lma, pcs[4], phy;

sys/dev/cas/if_cas.c

2734

lma = phy = 0;

sys/dev/cas/if_cas.c

2802

if (lma == 4 && phy == 4)

sys/dev/cas/if_cas.c

2826

pcs[phy] = 1;

sys/dev/cas/if_cas.c

2827

phy++;

sys/dev/cas/if_cas.c

2828

if (lma == 4 && phy == 4)

sys/dev/cas/if_cas.c

2850

if (phy == 0) {

sys/dev/cas/if_cas.c

2855

if (phy > 1 && pci_get_slot(dev) < nitems(pcs))

sys/dev/cxgb/common/cxgb_ael1002.c

105

err = mdio_write(phy, rv->mmd_addr, rv->reg_addr,

sys/dev/cxgb/common/cxgb_ael1002.c

108

err = t3_mdio_change_bits(phy, rv->mmd_addr,

sys/dev/cxgb/common/cxgb_ael1002.c

115

static void ael100x_txon(struct cphy *phy)

sys/dev/cxgb/common/cxgb_ael1002.c

117

int tx_on_gpio = phy->addr == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL;

sys/dev/cxgb/common/cxgb_ael1002.c

120

t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio);

sys/dev/cxgb/common/cxgb_ael1002.c

1202

err = set_phy_regs(phy, regs);

sys/dev/cxgb/common/cxgb_ael1002.c

1204

err = set_phy_regs(phy, preemphasis);

sys/dev/cxgb/common/cxgb_ael1002.c

1211

err = mdio_write(phy, MDIO_DEV_PMA_PMD, twinax_edc[i],

sys/dev/cxgb/common/cxgb_ael1002.c

1214

phy->priv = edc_twinax;

sys/dev/cxgb/common/cxgb_ael1002.c

1218

static int ael2005_get_module_type(struct cphy *phy, int delay_ms)

sys/dev/cxgb/common/cxgb_ael1002.c

1223

v = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, &stat);

sys/dev/cxgb/common/cxgb_ael1002.c

1230

return ael2xxx_get_module_type(phy, delay_ms);

sys/dev/cxgb/common/cxgb_ael1002.c

1233

static int ael2005_intr_enable(struct cphy *phy)

sys/dev/cxgb/common/cxgb_ael1002.c

1235

int err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, 0x200);

sys/dev/cxgb/common/cxgb_ael1002.c

1236

return err ? err : t3_phy_lasi_intr_enable(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

1239

static int ael2005_intr_disable(struct cphy *phy)

sys/dev/cxgb/common/cxgb_ael1002.c

1241

int err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, 0x100);

sys/dev/cxgb/common/cxgb_ael1002.c

1242

return err ? err : t3_phy_lasi_intr_disable(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

1245

static int ael2005_intr_clear(struct cphy *phy)

sys/dev/cxgb/common/cxgb_ael1002.c

1247

int err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, 0xd00);

sys/dev/cxgb/common/cxgb_ael1002.c

1248

return err ? err : t3_phy_lasi_intr_clear(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

1251

static int ael2005_reset(struct cphy *phy, int wait)

sys/dev/cxgb/common/cxgb_ael1002.c

127

static int ael_i2c_rd(struct cphy *phy, int dev_addr, int word_addr)

sys/dev/cxgb/common/cxgb_ael1002.c

1272

err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, &lasi_ctrl);

sys/dev/cxgb/common/cxgb_ael1002.c

1276

err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, 0);

sys/dev/cxgb/common/cxgb_ael1002.c

1281

phy->priv = edc_none;

sys/dev/cxgb/common/cxgb_ael1002.c

1282

err = set_phy_regs(phy, regs0);

sys/dev/cxgb/common/cxgb_ael1002.c

1288

err = ael2005_get_module_type(phy, 0);

sys/dev/cxgb/common/cxgb_ael1002.c

1291

phy->modtype = (u8)err;

sys/dev/cxgb/common/cxgb_ael1002.c

1296

err = ael2005_setup_twinax_edc(phy, err);

sys/dev/cxgb/common/cxgb_ael1002.c

1298

err = ael2005_setup_sr_edc(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

1302

err = set_phy_regs(phy, regs1);

sys/dev/cxgb/common/cxgb_ael1002.c

1308

err = ael2005_intr_enable(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

1312

static int ael2005_intr_handler(struct cphy *phy)

sys/dev/cxgb/common/cxgb_ael1002.c

1317

ret = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_STAT, &stat);

sys/dev/cxgb/common/cxgb_ael1002.c

132

err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_CTRL,

sys/dev/cxgb/common/cxgb_ael1002.c

1322

ret = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL,

sys/dev/cxgb/common/cxgb_ael1002.c

1328

ret = ael2005_get_module_type(phy, 300);

sys/dev/cxgb/common/cxgb_ael1002.c

1332

phy->modtype = (u8)ret;

sys/dev/cxgb/common/cxgb_ael1002.c

1334

edc_needed = phy->priv; /* on unplug retain EDC */

sys/dev/cxgb/common/cxgb_ael1002.c

1341

if (edc_needed != phy->priv) {

sys/dev/cxgb/common/cxgb_ael1002.c

1342

ret = ael2005_reset(phy, 0);

sys/dev/cxgb/common/cxgb_ael1002.c

1348

ret = t3_phy_lasi_intr_handler(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

1387

struct cphy *phy = &pinfo->phy;

sys/dev/cxgb/common/cxgb_ael1002.c

1389

cphy_init(phy, pinfo->adapter, pinfo, phy_addr, &ael2005_ops, mdio_ops,

sys/dev/cxgb/common/cxgb_ael1002.c

139

err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_STAT, &stat);

sys/dev/cxgb/common/cxgb_ael1002.c

1393

ael_laser_down(phy, 0);

sys/dev/cxgb/common/cxgb_ael1002.c

1395

err = ael2005_get_module_type(phy, 0);

sys/dev/cxgb/common/cxgb_ael1002.c

1397

phy->modtype = err;

sys/dev/cxgb/common/cxgb_ael1002.c

1399

return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, AEL_OPT_SETTINGS, 0,

sys/dev/cxgb/common/cxgb_ael1002.c

1406

static int ael2020_setup_sr_edc(struct cphy *phy)

sys/dev/cxgb/common/cxgb_ael1002.c

1420

err = set_phy_regs(phy, regs);

sys/dev/cxgb/common/cxgb_ael1002.c

1425

phy->priv = edc_sr;

sys/dev/cxgb/common/cxgb_ael1002.c

143

err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_DATA,

sys/dev/cxgb/common/cxgb_ael1002.c

1432

static int ael2020_setup_twinax_edc(struct cphy *phy, int modtype)

sys/dev/cxgb/common/cxgb_ael1002.c

150

CH_WARN(phy->adapter, "PHY %u i2c read of dev.addr %x.%x timed out\n",

sys/dev/cxgb/common/cxgb_ael1002.c

151

phy->addr, dev_addr, word_addr);

sys/dev/cxgb/common/cxgb_ael1002.c

158

static int ael_i2c_wr(struct cphy *phy, int dev_addr, int word_addr, int data)

sys/dev/cxgb/common/cxgb_ael1002.c

163

err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_DATA, data);

sys/dev/cxgb/common/cxgb_ael1002.c

167

err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_CTRL,

sys/dev/cxgb/common/cxgb_ael1002.c

174

err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_STAT, &stat);

sys/dev/cxgb/common/cxgb_ael1002.c

180

CH_WARN(phy->adapter, "PHY %u i2c Write of dev.addr %x.%x = %#x timed out\n",

sys/dev/cxgb/common/cxgb_ael1002.c

181

phy->addr, dev_addr, word_addr, data);

sys/dev/cxgb/common/cxgb_ael1002.c

185

static int get_phytrans_type(struct cphy *phy)

sys/dev/cxgb/common/cxgb_ael1002.c

189

v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0);

sys/dev/cxgb/common/cxgb_ael1002.c

1895

err = set_phy_regs(phy, uCclock40MHz);

sys/dev/cxgb/common/cxgb_ael1002.c

1899

err = set_phy_regs(phy, uCclockActivate);

sys/dev/cxgb/common/cxgb_ael1002.c

1905

err = mdio_write(phy, MDIO_DEV_PMA_PMD, twinax_edc[i],

sys/dev/cxgb/common/cxgb_ael1002.c

1908

err = set_phy_regs(phy, uCactivate);

sys/dev/cxgb/common/cxgb_ael1002.c

1910

phy->priv = edc_twinax;

sys/dev/cxgb/common/cxgb_ael1002.c

1917

static int ael2020_get_module_type(struct cphy *phy, int delay_ms)

sys/dev/cxgb/common/cxgb_ael1002.c

1922

v = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2020_GPIO_STAT, &stat);

sys/dev/cxgb/common/cxgb_ael1002.c

1931

return ael2xxx_get_module_type(phy, delay_ms);

sys/dev/cxgb/common/cxgb_ael1002.c

1938

static int ael2020_intr_enable(struct cphy *phy)

sys/dev/cxgb/common/cxgb_ael1002.c

1954

err = set_phy_regs(phy, regs);

sys/dev/cxgb/common/cxgb_ael1002.c

1959

err = t3_phy_lasi_intr_enable(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

196

static int ael_laser_down(struct cphy *phy, int enable)

sys/dev/cxgb/common/cxgb_ael1002.c

1969

static int ael2020_intr_disable(struct cphy *phy)

sys/dev/cxgb/common/cxgb_ael1002.c

1983

err = set_phy_regs(phy, regs);

sys/dev/cxgb/common/cxgb_ael1002.c

1988

return t3_phy_lasi_intr_disable(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

1994

static int ael2020_intr_clear(struct cphy *phy)

sys/dev/cxgb/common/cxgb_ael1002.c

1997

int err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2020_GPIO_INTR, &stat);

sys/dev/cxgb/common/cxgb_ael1002.c

1998

return err ? err : t3_phy_lasi_intr_clear(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

200

v = get_phytrans_type(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

2024

static int ael2020_reset(struct cphy *phy, int wait)

sys/dev/cxgb/common/cxgb_ael1002.c

2030

err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, &lasi_ctrl);

sys/dev/cxgb/common/cxgb_ael1002.c

2034

err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, 125);

sys/dev/cxgb/common/cxgb_ael1002.c

2040

phy->priv = edc_none;

sys/dev/cxgb/common/cxgb_ael1002.c

2041

err = set_phy_regs(phy, ael2020_reset_regs);

sys/dev/cxgb/common/cxgb_ael1002.c

2047

err = ael2020_get_module_type(phy, 0);

sys/dev/cxgb/common/cxgb_ael1002.c

2050

phy->modtype = (u8)err;

sys/dev/cxgb/common/cxgb_ael1002.c

2054

err = ael2020_setup_twinax_edc(phy, err);

sys/dev/cxgb/common/cxgb_ael1002.c

2056

err = ael2020_setup_sr_edc(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

206

v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 93);

sys/dev/cxgb/common/cxgb_ael1002.c

2062

err = ael2020_intr_enable(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

2069

static int ael2020_intr_handler(struct cphy *phy)

sys/dev/cxgb/common/cxgb_ael1002.c

2074

ret = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2020_GPIO_INTR, &stat);

sys/dev/cxgb/common/cxgb_ael1002.c

2080

ret = ael2020_get_module_type(phy, 300);

sys/dev/cxgb/common/cxgb_ael1002.c

2084

phy->modtype = (u8)ret;

sys/dev/cxgb/common/cxgb_ael1002.c

2086

edc_needed = phy->priv; /* on unplug retain EDC */

sys/dev/cxgb/common/cxgb_ael1002.c

2093

if (edc_needed != phy->priv) {

sys/dev/cxgb/common/cxgb_ael1002.c

2094

ret = ael2020_reset(phy, 0);

sys/dev/cxgb/common/cxgb_ael1002.c

2100

ret = t3_phy_lasi_intr_handler(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

2139

struct cphy *phy = &pinfo->phy;

sys/dev/cxgb/common/cxgb_ael1002.c

2141

cphy_init(phy, pinfo->adapter, pinfo, phy_addr, &ael2020_ops, mdio_ops,

sys/dev/cxgb/common/cxgb_ael1002.c

2146

err = set_phy_regs(phy, ael2020_reset_regs);

sys/dev/cxgb/common/cxgb_ael1002.c

2151

err = ael2020_get_module_type(phy, 0);

sys/dev/cxgb/common/cxgb_ael1002.c

2153

phy->modtype = err;

sys/dev/cxgb/common/cxgb_ael1002.c

2155

ael_laser_down(phy, 0);

sys/dev/cxgb/common/cxgb_ael1002.c

2162

static int get_link_status_x(struct cphy *phy, int *link_state, int *speed,

sys/dev/cxgb/common/cxgb_ael1002.c

2167

int err = mdio_read(phy, MDIO_DEV_PMA_PMD, PMD_RSD, &stat0);

sys/dev/cxgb/common/cxgb_ael1002.c

2170

err = mdio_read(phy, MDIO_DEV_PCS, PCS_STAT1_X, &stat1);

sys/dev/cxgb/common/cxgb_ael1002.c

2172

err = mdio_read(phy, MDIO_DEV_XGXS, XS_LN_STAT, &stat2);

sys/dev/cxgb/common/cxgb_ael1002.c

220

v = ael_i2c_rd(phy, dev_addr, 110);

sys/dev/cxgb/common/cxgb_ael1002.c

2218

struct cphy *phy = &pinfo->phy;

sys/dev/cxgb/common/cxgb_ael1002.c

2220

cphy_init(phy, pinfo->adapter, pinfo, phy_addr, &qt2045_ops, mdio_ops,

sys/dev/cxgb/common/cxgb_ael1002.c

2228

if (!phy_addr && !mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR, &stat) &&

sys/dev/cxgb/common/cxgb_ael1002.c

2230

phy->addr = 1;

sys/dev/cxgb/common/cxgb_ael1002.c

2234

static int xaui_direct_reset(struct cphy *phy, int wait)

sys/dev/cxgb/common/cxgb_ael1002.c

2239

static int xaui_direct_get_link_status(struct cphy *phy, int *link_state,

sys/dev/cxgb/common/cxgb_ael1002.c

2244

adapter_t *adapter = phy->adapter;

sys/dev/cxgb/common/cxgb_ael1002.c

2247

XGM_REG(A_XGM_SERDES_STAT0, phy->addr)) |

sys/dev/cxgb/common/cxgb_ael1002.c

2249

XGM_REG(A_XGM_SERDES_STAT1, phy->addr)) |

sys/dev/cxgb/common/cxgb_ael1002.c

2251

XGM_REG(A_XGM_SERDES_STAT2, phy->addr)) |

sys/dev/cxgb/common/cxgb_ael1002.c

2253

XGM_REG(A_XGM_SERDES_STAT3, phy->addr));

sys/dev/cxgb/common/cxgb_ael1002.c

2263

static int xaui_direct_power_down(struct cphy *phy, int enable)

sys/dev/cxgb/common/cxgb_ael1002.c

229

v = ael_i2c_wr(phy, dev_addr, 110, v);

sys/dev/cxgb/common/cxgb_ael1002.c

2298

cphy_init(&pinfo->phy, pinfo->adapter, pinfo, phy_addr, &xaui_direct_ops, mdio_ops,

sys/dev/cxgb/common/cxgb_ael1002.c

234

static int ael1002_power_down(struct cphy *phy, int enable)

sys/dev/cxgb/common/cxgb_ael1002.c

238

err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_DISABLE, !!enable);

sys/dev/cxgb/common/cxgb_ael1002.c

240

err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,

sys/dev/cxgb/common/cxgb_ael1002.c

245

static int ael1002_get_module_type(struct cphy *phy, int delay_ms)

sys/dev/cxgb/common/cxgb_ael1002.c

252

v = ael2xxx_get_module_type(phy, delay_ms);

sys/dev/cxgb/common/cxgb_ael1002.c

257

static int ael1002_reset(struct cphy *phy, int wait)

sys/dev/cxgb/common/cxgb_ael1002.c

261

if ((err = ael1002_power_down(phy, 0)) ||

sys/dev/cxgb/common/cxgb_ael1002.c

262

(err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_CONFIG1, 1)) ||

sys/dev/cxgb/common/cxgb_ael1002.c

263

(err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_HI, 0)) ||

sys/dev/cxgb/common/cxgb_ael1002.c

264

(err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_LO, 0)) ||

sys/dev/cxgb/common/cxgb_ael1002.c

265

(err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_XFI_EQL, 0x18)) ||

sys/dev/cxgb/common/cxgb_ael1002.c

266

(err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, AEL1002_LB_EN,

sys/dev/cxgb/common/cxgb_ael1002.c

270

err = ael1002_get_module_type(phy, 300);

sys/dev/cxgb/common/cxgb_ael1002.c

272

phy->modtype = err;

sys/dev/cxgb/common/cxgb_ael1002.c

277

static int ael1002_intr_noop(struct cphy *phy)

sys/dev/cxgb/common/cxgb_ael1002.c

285

static int get_link_status_r(struct cphy *phy, int *link_state, int *speed,

sys/dev/cxgb/common/cxgb_ael1002.c

290

int err = mdio_read(phy, MDIO_DEV_PMA_PMD, PMD_RSD, &stat0);

sys/dev/cxgb/common/cxgb_ael1002.c

293

err = mdio_read(phy, MDIO_DEV_PCS, PCS_STAT1_R, &stat1);

sys/dev/cxgb/common/cxgb_ael1002.c

295

err = mdio_read(phy, MDIO_DEV_XGXS, XS_LN_STAT, &stat2);

sys/dev/cxgb/common/cxgb_ael1002.c

347

struct cphy *phy = &pinfo->phy;

sys/dev/cxgb/common/cxgb_ael1002.c

349

cphy_init(phy, pinfo->adapter, pinfo, phy_addr, &ael1002_ops, mdio_ops,

sys/dev/cxgb/common/cxgb_ael1002.c

352

ael100x_txon(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

353

ael_laser_down(phy, 0);

sys/dev/cxgb/common/cxgb_ael1002.c

355

err = ael1002_get_module_type(phy, 0);

sys/dev/cxgb/common/cxgb_ael1002.c

357

phy->modtype = err;

sys/dev/cxgb/common/cxgb_ael1002.c

362

static int ael1006_reset(struct cphy *phy, int wait)

sys/dev/cxgb/common/cxgb_ael1002.c

366

err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);

sys/dev/cxgb/common/cxgb_ael1002.c

370

t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN,

sys/dev/cxgb/common/cxgb_ael1002.c

375

t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN,

sys/dev/cxgb/common/cxgb_ael1002.c

380

err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);

sys/dev/cxgb/common/cxgb_ael1002.c

386

err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, 1, 1);

sys/dev/cxgb/common/cxgb_ael1002.c

392

err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, 1, 0);

sys/dev/cxgb/common/cxgb_ael1002.c

428

struct cphy *phy = &pinfo->phy;

sys/dev/cxgb/common/cxgb_ael1002.c

430

cphy_init(phy, pinfo->adapter, pinfo, phy_addr, &ael1006_ops, mdio_ops,

sys/dev/cxgb/common/cxgb_ael1002.c

433

phy->modtype = phy_modtype_sr;

sys/dev/cxgb/common/cxgb_ael1002.c

434

ael100x_txon(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

441

static int ael2xxx_get_module_type(struct cphy *phy, int delay_ms)

sys/dev/cxgb/common/cxgb_ael1002.c

448

v = get_phytrans_type(phy);

sys/dev/cxgb/common/cxgb_ael1002.c

452

v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 3);

sys/dev/cxgb/common/cxgb_ael1002.c

465

v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 8);

sys/dev/cxgb/common/cxgb_ael1002.c

469

v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 60);

sys/dev/cxgb/common/cxgb_ael1002.c

476

v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 6);

sys/dev/cxgb/common/cxgb_ael1002.c

482

v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 10);

sys/dev/cxgb/common/cxgb_ael1002.c

488

v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0x12);

sys/dev/cxgb/common/cxgb_ael1002.c

497

v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 127);

sys/dev/cxgb/common/cxgb_ael1002.c

506

v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 131);

sys/dev/cxgb/common/cxgb_ael1002.c

524

static int ael2005_setup_sr_edc(struct cphy *phy)

sys/dev/cxgb/common/cxgb_ael1002.c

807

err = set_phy_regs(phy, regs);

sys/dev/cxgb/common/cxgb_ael1002.c

814

err = mdio_write(phy, MDIO_DEV_PMA_PMD, sr_edc[i],

sys/dev/cxgb/common/cxgb_ael1002.c

817

phy->priv = edc_sr;

sys/dev/cxgb/common/cxgb_ael1002.c

821

static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype)

sys/dev/cxgb/common/cxgb_ael1002.c

97

static int ael2xxx_get_module_type(struct cphy *phy, int delay_ms);

sys/dev/cxgb/common/cxgb_ael1002.c

99

static int set_phy_regs(struct cphy *phy, const struct reg_val *rv)

sys/dev/cxgb/common/cxgb_aq100x.c

100

return mdio_write(phy, MDIO_DEV_VEND1, AQ_THERMAL_THR, 0x6c00);

sys/dev/cxgb/common/cxgb_aq100x.c

104

aq100x_reset(struct cphy *phy, int wait)

sys/dev/cxgb/common/cxgb_aq100x.c

107

err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);

sys/dev/cxgb/common/cxgb_aq100x.c

109

err = aq100x_set_defaults(phy);

sys/dev/cxgb/common/cxgb_aq100x.c

114

aq100x_intr_enable(struct cphy *phy)

sys/dev/cxgb/common/cxgb_aq100x.c

126

AQ_WRITE_REGS(phy, imasks);

sys/dev/cxgb/common/cxgb_aq100x.c

132

aq100x_intr_disable(struct cphy *phy)

sys/dev/cxgb/common/cxgb_aq100x.c

144

AQ_WRITE_REGS(phy, imasks);

sys/dev/cxgb/common/cxgb_aq100x.c

150

aq100x_intr_clear(struct cphy *phy)

sys/dev/cxgb/common/cxgb_aq100x.c

160

AQ_READ_REGS(phy, iclr);

sys/dev/cxgb/common/cxgb_aq100x.c

166

aq100x_vendor_intr(struct cphy *phy, int *rc)

sys/dev/cxgb/common/cxgb_aq100x.c

171

err = mdio_read(phy, MDIO_DEV_VEND1, 0xfc01, &cause);

sys/dev/cxgb/common/cxgb_aq100x.c

176

err = mdio_read(phy, MDIO_DEV_VEND1, 0xcc00, &v);

sys/dev/cxgb/common/cxgb_aq100x.c

181

CH_WARN(phy->adapter, "PHY%d: temperature is now %dC\n",

sys/dev/cxgb/common/cxgb_aq100x.c

182

phy->addr, aq100x_temperature(phy));

sys/dev/cxgb/common/cxgb_aq100x.c

184

t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN,

sys/dev/cxgb/common/cxgb_aq100x.c

185

phy->addr ? F_GPIO10_OUT_VAL : F_GPIO6_OUT_VAL, 0);

sys/dev/cxgb/common/cxgb_aq100x.c

194

CH_WARN(phy->adapter, "PHY%d: unhandled vendor interrupt"

sys/dev/cxgb/common/cxgb_aq100x.c

195

" (0x%x)\n", phy->addr, cause);

sys/dev/cxgb/common/cxgb_aq100x.c

202

aq100x_intr_handler(struct cphy *phy)

sys/dev/cxgb/common/cxgb_aq100x.c

207

err = mdio_read(phy, MDIO_DEV_VEND1, AQ_IFLAG_GLOBAL, &cause);

sys/dev/cxgb/common/cxgb_aq100x.c

212

err = aq100x_vendor_intr(phy, &rc);

sys/dev/cxgb/common/cxgb_aq100x.c

219

CH_WARN(phy->adapter, "PHY%d: unhandled interrupt (0x%x)\n",

sys/dev/cxgb/common/cxgb_aq100x.c

220

phy->addr, cause);

sys/dev/cxgb/common/cxgb_aq100x.c

226

aq100x_power_down(struct cphy *phy, int off)

sys/dev/cxgb/common/cxgb_aq100x.c

231

err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, BMCR_PDOWN,

sys/dev/cxgb/common/cxgb_aq100x.c

238

err = mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMCR, &v);

sys/dev/cxgb/common/cxgb_aq100x.c

246

CH_WARN(phy->adapter, "PHY%d: power-up timed out (0x%x).\n",

sys/dev/cxgb/common/cxgb_aq100x.c

247

phy->addr, v);

sys/dev/cxgb/common/cxgb_aq100x.c

255

aq100x_autoneg_enable(struct cphy *phy)

sys/dev/cxgb/common/cxgb_aq100x.c

259

err = aq100x_power_down(phy, 0);

sys/dev/cxgb/common/cxgb_aq100x.c

261

err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, MII_BMCR,

sys/dev/cxgb/common/cxgb_aq100x.c

268

aq100x_autoneg_restart(struct cphy *phy)

sys/dev/cxgb/common/cxgb_aq100x.c

270

return aq100x_autoneg_enable(phy);

sys/dev/cxgb/common/cxgb_aq100x.c

274

aq100x_advertise(struct cphy *phy, unsigned int advertise_map)

sys/dev/cxgb/common/cxgb_aq100x.c

283

err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, AQ_10G_CTRL,

sys/dev/cxgb/common/cxgb_aq100x.c

294

err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, AQ_1G_CTRL,

sys/dev/cxgb/common/cxgb_aq100x.c

309

err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, AQ_100M_CTRL, 0xfe0, adv);

sys/dev/cxgb/common/cxgb_aq100x.c

315

aq100x_set_loopback(struct cphy *phy, int mmd, int dir, int enable)

sys/dev/cxgb/common/cxgb_aq100x.c

317

return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,

sys/dev/cxgb/common/cxgb_aq100x.c

322

aq100x_set_speed_duplex(struct cphy *phy, int speed, int duplex)

sys/dev/cxgb/common/cxgb_aq100x.c

338

err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, MII_BMCR,

sys/dev/cxgb/common/cxgb_aq100x.c

343

err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,

sys/dev/cxgb/common/cxgb_aq100x.c

352

aq100x_get_link_status(struct cphy *phy, int *link_state, int *speed, int *duplex,

sys/dev/cxgb/common/cxgb_aq100x.c

358

err = mdio_read(phy, MDIO_DEV_PMA_PMD, AQ_LINK_STAT, &v);

sys/dev/cxgb/common/cxgb_aq100x.c

364

err = mdio_read(phy, MDIO_DEV_ANEG, MII_BMCR, &v);

sys/dev/cxgb/common/cxgb_aq100x.c

371

err = mdio_read(phy, MDIO_DEV_ANEG, 1, &v);

sys/dev/cxgb/common/cxgb_aq100x.c

377

err = mdio_read(phy, MDIO_DEV_ANEG, AQ_ANEG_STAT, &v);

sys/dev/cxgb/common/cxgb_aq100x.c

399

err = mdio_read(phy, MDIO_DEV_ANEG, 0x13, &lpa);

sys/dev/cxgb/common/cxgb_aq100x.c

401

err = mdio_read(phy, MDIO_DEV_ANEG,

sys/dev/cxgb/common/cxgb_aq100x.c

420

err = mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMCR, &v);

sys/dev/cxgb/common/cxgb_aq100x.c

466

struct cphy *phy = &pinfo->phy;

sys/dev/cxgb/common/cxgb_aq100x.c

471

cphy_init(&pinfo->phy, adapter, pinfo, phy_addr, &aq100x_ops, mdio_ops,

sys/dev/cxgb/common/cxgb_aq100x.c

490

err = mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMCR, &v);

sys/dev/cxgb/common/cxgb_aq100x.c

512

(void) mdio_read(phy, MDIO_DEV_VEND1, AQ_FW_VERSION, &v);

sys/dev/cxgb/common/cxgb_aq100x.c

518

(void) mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMCR, &v);

sys/dev/cxgb/common/cxgb_aq100x.c

527

(void) mdio_read(phy, MDIO_DEV_XGXS, AQ_XAUI_RX_CFG, &v);

sys/dev/cxgb/common/cxgb_aq100x.c

528

(void) mdio_read(phy, MDIO_DEV_XGXS, AQ_XAUI_TX_CFG, &v2);

sys/dev/cxgb/common/cxgb_aq100x.c

533

(void) mdio_read(phy, MDIO_DEV_XGXS, AQ_XAUI_KX_CFG, &v);

sys/dev/cxgb/common/cxgb_aq100x.c

538

(void) aq100x_set_defaults(phy);

sys/dev/cxgb/common/cxgb_aq100x.c

66

#define AQ_WRITE_REGS(phy, regs) do { \

sys/dev/cxgb/common/cxgb_aq100x.c

69

(void) mdio_write(phy, regs[i].mmd, regs[i].reg, regs[i].val); \

sys/dev/cxgb/common/cxgb_aq100x.c

72

#define AQ_READ_REGS(phy, regs) do { \

sys/dev/cxgb/common/cxgb_aq100x.c

75

(void) mdio_read(phy, regs[i].mmd, regs[i].reg, &v); \

sys/dev/cxgb/common/cxgb_aq100x.c

83

aq100x_temperature(struct cphy *phy)

sys/dev/cxgb/common/cxgb_aq100x.c

87

if (mdio_read(phy, MDIO_DEV_VEND1, AQ_THERMAL2, &v) ||

sys/dev/cxgb/common/cxgb_aq100x.c

91

if (mdio_read(phy, MDIO_DEV_VEND1, AQ_THERMAL1, &v))

sys/dev/cxgb/common/cxgb_aq100x.c

98

aq100x_set_defaults(struct cphy *phy)

sys/dev/cxgb/common/cxgb_common.h

553

int (*reset)(struct cphy *phy, int wait);

sys/dev/cxgb/common/cxgb_common.h

555

int (*intr_enable)(struct cphy *phy);

sys/dev/cxgb/common/cxgb_common.h

556

int (*intr_disable)(struct cphy *phy);

sys/dev/cxgb/common/cxgb_common.h

557

int (*intr_clear)(struct cphy *phy);

sys/dev/cxgb/common/cxgb_common.h

558

int (*intr_handler)(struct cphy *phy);

sys/dev/cxgb/common/cxgb_common.h

560

int (*autoneg_enable)(struct cphy *phy);

sys/dev/cxgb/common/cxgb_common.h

561

int (*autoneg_restart)(struct cphy *phy);

sys/dev/cxgb/common/cxgb_common.h

563

int (*advertise)(struct cphy *phy, unsigned int advertise_map);

sys/dev/cxgb/common/cxgb_common.h

564

int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);

sys/dev/cxgb/common/cxgb_common.h

565

int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);

sys/dev/cxgb/common/cxgb_common.h

566

int (*get_link_status)(struct cphy *phy, int *link_state, int *speed,

sys/dev/cxgb/common/cxgb_common.h

568

int (*power_down)(struct cphy *phy, int enable);

sys/dev/cxgb/common/cxgb_common.h

590

static inline int mdio_read(struct cphy *phy, int mmd, int reg,

sys/dev/cxgb/common/cxgb_common.h

593

return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);

sys/dev/cxgb/common/cxgb_common.h

596

static inline int mdio_write(struct cphy *phy, int mmd, int reg,

sys/dev/cxgb/common/cxgb_common.h

599

return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);

sys/dev/cxgb/common/cxgb_common.h

603

static inline void cphy_init(struct cphy *phy, adapter_t *adapter, pinfo_t *pinfo,

sys/dev/cxgb/common/cxgb_common.h

608

phy->addr = (u8)phy_addr;

sys/dev/cxgb/common/cxgb_common.h

609

phy->caps = caps;

sys/dev/cxgb/common/cxgb_common.h

610

phy->adapter = adapter;

sys/dev/cxgb/common/cxgb_common.h

611

phy->pinfo = pinfo;

sys/dev/cxgb/common/cxgb_common.h

612

phy->desc = desc;

sys/dev/cxgb/common/cxgb_common.h

613

phy->ops = phy_ops;

sys/dev/cxgb/common/cxgb_common.h

615

phy->mdio_read = mdio_ops->read;

sys/dev/cxgb/common/cxgb_common.h

616

phy->mdio_write = mdio_ops->write;

sys/dev/cxgb/common/cxgb_common.h

689

int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,

sys/dev/cxgb/common/cxgb_common.h

691

int t3_phy_reset(struct cphy *phy, int mmd, int wait);

sys/dev/cxgb/common/cxgb_common.h

692

int t3_phy_advertise(struct cphy *phy, unsigned int advert);

sys/dev/cxgb/common/cxgb_common.h

693

int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert);

sys/dev/cxgb/common/cxgb_common.h

694

int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);

sys/dev/cxgb/common/cxgb_common.h

695

int t3_phy_lasi_intr_enable(struct cphy *phy);

sys/dev/cxgb/common/cxgb_common.h

696

int t3_phy_lasi_intr_disable(struct cphy *phy);

sys/dev/cxgb/common/cxgb_common.h

697

int t3_phy_lasi_intr_clear(struct cphy *phy);

sys/dev/cxgb/common/cxgb_common.h

698

int t3_phy_lasi_intr_handler(struct cphy *phy);

sys/dev/cxgb/common/cxgb_common.h

711

int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);

sys/dev/cxgb/common/cxgb_mv88e1xxx.c

220

static int mv88e1xxx_set_speed_duplex(struct cphy *phy, int speed, int duplex)

sys/dev/cxgb/common/cxgb_mv88e1xxx.c

222

int err = t3_set_phy_speed_duplex(phy, speed, duplex);

sys/dev/cxgb/common/cxgb_mv88e1xxx.c

226

err = mv88e1xxx_reset(phy, 0);

sys/dev/cxgb/common/cxgb_mv88e1xxx.c

300

struct cphy *phy = &pinfo->phy;

sys/dev/cxgb/common/cxgb_mv88e1xxx.c

303

cphy_init(phy, pinfo->adapter, pinfo, phy_addr, &mv88e1xxx_ops, mdio_ops,

sys/dev/cxgb/common/cxgb_mv88e1xxx.c

309

err = mdio_write(phy, 0, MV88E1XXX_EXTENDED_ADDR, 0xb);

sys/dev/cxgb/common/cxgb_mv88e1xxx.c

311

err = mdio_write(phy, 0, MV88E1XXX_EXTENDED_DATA, 0x8004);

sys/dev/cxgb/common/cxgb_mv88e1xxx.c

314

err = mv88e1xxx_downshift_set(phy, 1); /* Enable downshift */

sys/dev/cxgb/common/cxgb_t3_hw.c

1523

struct cphy *phy = &pi->phy;

sys/dev/cxgb/common/cxgb_t3_hw.c

1533

phy->ops->get_link_status(phy, &link_state, &speed, &duplex, &fc);

sys/dev/cxgb/common/cxgb_t3_hw.c

1536

phy->rst = 0;

sys/dev/cxgb/common/cxgb_t3_hw.c

1537

else if (++phy->rst == 3) {

sys/dev/cxgb/common/cxgb_t3_hw.c

1538

phy->ops->reset(phy, 0);

sys/dev/cxgb/common/cxgb_t3_hw.c

1539

phy->rst = 0;

sys/dev/cxgb/common/cxgb_t3_hw.c

1671

int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)

sys/dev/cxgb/common/cxgb_t3_hw.c

1684

phy->ops->advertise(phy, lc->advertising);

sys/dev/cxgb/common/cxgb_t3_hw.c

1693

phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);

sys/dev/cxgb/common/cxgb_t3_hw.c

1695

if (!is_10G(phy->adapter))

sys/dev/cxgb/common/cxgb_t3_hw.c

1696

phy->ops->power_down(phy, 0);

sys/dev/cxgb/common/cxgb_t3_hw.c

1698

phy->ops->autoneg_enable(phy);

sys/dev/cxgb/common/cxgb_t3_hw.c

1702

phy->ops->reset(phy, 0);

sys/dev/cxgb/common/cxgb_t3_hw.c

2215

if (!(p->phy.caps & SUPPORTED_IRQ))

sys/dev/cxgb/common/cxgb_t3_hw.c

2219

int phy_cause = p->phy.ops->intr_handler(&p->phy);

sys/dev/cxgb/common/cxgb_t3_hw.c

2224

p->phy.fifo_errors++;

sys/dev/cxgb/common/cxgb_t3_hw.c

2303

if ((adap2pinfo(adap, i)->phy.caps & SUPPORTED_IRQ) &&

sys/dev/cxgb/common/cxgb_t3_hw.c

2445

pi->phy.ops->intr_enable(&pi->phy);

sys/dev/cxgb/common/cxgb_t3_hw.c

2461

pi->phy.ops->intr_disable(&pi->phy);

sys/dev/cxgb/common/cxgb_t3_hw.c

2477

pi->phy.ops->intr_clear(&pi->phy);

sys/dev/cxgb/common/cxgb_t3_hw.c

369

int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,

sys/dev/cxgb/common/cxgb_t3_hw.c

375

ret = mdio_read(phy, mmd, reg, &val);

sys/dev/cxgb/common/cxgb_t3_hw.c

378

ret = mdio_write(phy, mmd, reg, val | set);

sys/dev/cxgb/common/cxgb_t3_hw.c

393

int t3_phy_reset(struct cphy *phy, int mmd, int wait)

sys/dev/cxgb/common/cxgb_t3_hw.c

398

err = t3_mdio_change_bits(phy, mmd, MII_BMCR, BMCR_PDOWN, BMCR_RESET);

sys/dev/cxgb/common/cxgb_t3_hw.c

403

err = mdio_read(phy, mmd, MII_BMCR, &ctl);

sys/dev/cxgb/common/cxgb_t3_hw.c

422

int t3_phy_advertise(struct cphy *phy, unsigned int advert)

sys/dev/cxgb/common/cxgb_t3_hw.c

427

err = mdio_read(phy, 0, MII_CTRL1000, &val);

sys/dev/cxgb/common/cxgb_t3_hw.c

437

err = mdio_write(phy, 0, MII_CTRL1000, val);

sys/dev/cxgb/common/cxgb_t3_hw.c

454

return mdio_write(phy, 0, MII_ADVERTISE, val);

sys/dev/cxgb/common/cxgb_t3_hw.c

4580

init_link_config(&p->link_config, p->phy.caps);

sys/dev/cxgb/common/cxgb_t3_hw.c

4581

p->phy.ops->power_down(&p->phy, 1);

sys/dev/cxgb/common/cxgb_t3_hw.c

4588

if (!(p->phy.caps & SUPPORTED_IRQ) &&

sys/dev/cxgb/common/cxgb_t3_hw.c

4636

ret = pti->phy_prep(p, p->phy.addr, NULL);

sys/dev/cxgb/common/cxgb_t3_hw.c

4639

p->phy.ops->power_down(&p->phy, 1);

sys/dev/cxgb/common/cxgb_t3_hw.c

465

int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert)

sys/dev/cxgb/common/cxgb_t3_hw.c

477

return mdio_write(phy, 0, MII_ADVERTISE, val);

sys/dev/cxgb/common/cxgb_t3_hw.c

489

int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex)

sys/dev/cxgb/common/cxgb_t3_hw.c

494

err = mdio_read(phy, 0, MII_BMCR, &ctl);

sys/dev/cxgb/common/cxgb_t3_hw.c

512

return mdio_write(phy, 0, MII_BMCR, ctl);

sys/dev/cxgb/common/cxgb_t3_hw.c

515

int t3_phy_lasi_intr_enable(struct cphy *phy)

sys/dev/cxgb/common/cxgb_t3_hw.c

517

return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 1);

sys/dev/cxgb/common/cxgb_t3_hw.c

520

int t3_phy_lasi_intr_disable(struct cphy *phy)

sys/dev/cxgb/common/cxgb_t3_hw.c

522

return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 0);

sys/dev/cxgb/common/cxgb_t3_hw.c

525

int t3_phy_lasi_intr_clear(struct cphy *phy)

sys/dev/cxgb/common/cxgb_t3_hw.c

529

return mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &val);

sys/dev/cxgb/common/cxgb_t3_hw.c

532

int t3_phy_lasi_intr_handler(struct cphy *phy)

sys/dev/cxgb/common/cxgb_t3_hw.c

535

int err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &status);

sys/dev/cxgb/common/cxgb_tn1010.c

103

err = tn1010_power_down(phy, 0);

sys/dev/cxgb/common/cxgb_tn1010.c

105

err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, MII_BMCR, 0,

sys/dev/cxgb/common/cxgb_tn1010.c

110

static int tn1010_advertise(struct cphy *phy, unsigned int advert)

sys/dev/cxgb/common/cxgb_tn1010.c

122

err = mdio_write(phy, MDIO_DEV_ANEG, ANEG_ADVER, val);

sys/dev/cxgb/common/cxgb_tn1010.c

127

return mdio_write(phy, MDIO_DEV_ANEG, ANEG_10G_CTRL, val |

sys/dev/cxgb/common/cxgb_tn1010.c

131

static int tn1010_get_link_status(struct cphy *phy, int *link_state,

sys/dev/cxgb/common/cxgb_tn1010.c

137

err = mdio_read(phy, MDIO_DEV_VEND1, TN1010_VEND1_STAT, &status);

sys/dev/cxgb/common/cxgb_tn1010.c

149

err = mdio_read(phy, MDIO_DEV_ANEG, ANEG_LPA, &lpa);

sys/dev/cxgb/common/cxgb_tn1010.c

151

err = mdio_read(phy, MDIO_DEV_ANEG, ANEG_ADVER,

sys/dev/cxgb/common/cxgb_tn1010.c

176

static int tn1010_set_speed_duplex(struct cphy *phy, int speed, int duplex)

sys/dev/cxgb/common/cxgb_tn1010.c

215

cphy_init(&pinfo->phy, pinfo->adapter, pinfo, phy_addr, &tn1010_ops, mdio_ops,

sys/dev/cxgb/common/cxgb_tn1010.c

75

static int tn1010_reset(struct cphy *phy, int wait)

sys/dev/cxgb/common/cxgb_tn1010.c

77

int err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);

sys/dev/cxgb/common/cxgb_tn1010.c

82

static int tn1010_power_down(struct cphy *phy, int enable)

sys/dev/cxgb/common/cxgb_tn1010.c

84

return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,

sys/dev/cxgb/common/cxgb_tn1010.c

88

static int tn1010_autoneg_enable(struct cphy *phy)

sys/dev/cxgb/common/cxgb_tn1010.c

92

err = tn1010_power_down(phy, 0);

sys/dev/cxgb/common/cxgb_tn1010.c

94

err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, MII_BMCR, 0,

sys/dev/cxgb/common/cxgb_tn1010.c

99

static int tn1010_autoneg_restart(struct cphy *phy)

sys/dev/cxgb/common/cxgb_vsc8211.c

274

static int vsc8211_set_automdi(struct cphy *phy, int enable)

sys/dev/cxgb/common/cxgb_vsc8211.c

278

if ((err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0x52b5)) != 0 ||

sys/dev/cxgb/common/cxgb_vsc8211.c

279

(err = mdio_write(phy, 0, 18, 0x12)) != 0 ||

sys/dev/cxgb/common/cxgb_vsc8211.c

280

(err = mdio_write(phy, 0, 17, enable ? 0x2803 : 0x3003)) != 0 ||

sys/dev/cxgb/common/cxgb_vsc8211.c

281

(err = mdio_write(phy, 0, 16, 0x87fa)) != 0 ||

sys/dev/cxgb/common/cxgb_vsc8211.c

282

(err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0)) != 0)

sys/dev/cxgb/common/cxgb_vsc8211.c

287

static int vsc8211_set_speed_duplex(struct cphy *phy, int speed, int duplex)

sys/dev/cxgb/common/cxgb_vsc8211.c

291

err = t3_set_phy_speed_duplex(phy, speed, duplex);

sys/dev/cxgb/common/cxgb_vsc8211.c

293

err = vsc8211_set_automdi(phy, 1);

sys/dev/cxgb/common/cxgb_vsc8211.c

404

struct cphy *phy = &portinfo->phy;

sys/dev/cxgb/common/cxgb_vsc8211.c

407

err = mdio_read(phy, 0, VSC8211_PHY_CTRL, &currentregval);

sys/dev/cxgb/common/cxgb_vsc8211.c

425

return mdio_write(phy, 0, VSC8211_PHY_CTRL, regval);

sys/dev/cxgb/common/cxgb_vsc8211.c

431

struct cphy *phy = &pinfo->phy;

sys/dev/cxgb/common/cxgb_vsc8211.c

435

cphy_init(&pinfo->phy, pinfo->adapter, pinfo, phy_addr, &vsc8211_ops, mdio_ops,

sys/dev/cxgb/common/cxgb_vsc8211.c

441

err = mdio_read(phy, 0, VSC8211_EXT_CTRL, &val);

sys/dev/cxgb/common/cxgb_vsc8211.c

446

return mdio_write(phy, 0, VSC8211_LED_CTRL, 0x100);

sys/dev/cxgb/common/cxgb_vsc8211.c

449

phy->caps = SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |

sys/dev/cxgb/common/cxgb_vsc8211.c

451

phy->desc = "1000BASE-X";

sys/dev/cxgb/common/cxgb_vsc8211.c

452

phy->ops = &vsc8211_fiber_ops;

sys/dev/cxgb/common/cxgb_vsc8211.c

454

if ((err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 1)) != 0 ||

sys/dev/cxgb/common/cxgb_vsc8211.c

455

(err = mdio_write(phy, 0, VSC8211_SIGDET_CTRL, 1)) != 0 ||

sys/dev/cxgb/common/cxgb_vsc8211.c

456

(err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0)) != 0 ||

sys/dev/cxgb/common/cxgb_vsc8211.c

457

(err = mdio_write(phy, 0, VSC8211_EXT_CTRL,

sys/dev/cxgb/common/cxgb_vsc8211.c

459

(err = vsc8211_reset(phy, 0)) != 0)

sys/dev/cxgb/cxgb_adapter.h

95

struct cphy phy;

sys/dev/cxgb/cxgb_main.c

1211

int mod = pi->phy.modtype;

sys/dev/cxgb/cxgb_main.c

1676

t3_link_start(&p->phy, mac, &p->link_config);

sys/dev/cxgb/cxgb_main.c

1692

p->phy.caps & SUPPORTED_LINK_IRQ ? hz * 3 : hz / 4,

sys/dev/cxgb/cxgb_main.c

1792

pi->phy.ops->power_down(&pi->phy, 1);

sys/dev/cxgb/cxgb_main.c

2048

struct cphy *phy = &p->phy;

sys/dev/cxgb/cxgb_main.c

2050

int mod = phy->modtype;

sys/dev/cxgb/cxgb_main.c

2056

if (phy->caps & SUPPORTED_TP && phy->caps & SUPPORTED_Autoneg) {

sys/dev/cxgb/cxgb_main.c

2059

if (phy->caps & SUPPORTED_10000baseT_Full)

sys/dev/cxgb/cxgb_main.c

2062

if (phy->caps & SUPPORTED_1000baseT_Full)

sys/dev/cxgb/cxgb_main.c

2065

if (phy->caps & SUPPORTED_100baseT_Full)

sys/dev/cxgb/cxgb_main.c

2068

if (phy->caps & SUPPORTED_10baseT_Full)

sys/dev/cxgb/cxgb_main.c

2074

} else if (phy->caps & SUPPORTED_TP) {

sys/dev/cxgb/cxgb_main.c

2077

KASSERT(phy->caps & SUPPORTED_10000baseT_Full,

sys/dev/cxgb/cxgb_main.c

2078

("%s: unexpected cap 0x%x", __func__, phy->caps));

sys/dev/cxgb/cxgb_main.c

2083

} else if (phy->caps & SUPPORTED_FIBRE &&

sys/dev/cxgb/cxgb_main.c

2084

phy->caps & SUPPORTED_10000baseT_Full) {

sys/dev/cxgb/cxgb_main.c

2094

} else if (phy->caps & SUPPORTED_FIBRE &&

sys/dev/cxgb/cxgb_main.c

2095

phy->caps & SUPPORTED_1000baseT_Full) {

sys/dev/cxgb/cxgb_main.c

2104

phy->caps));

sys/dev/cxgb/cxgb_main.c

2117

if (cur->ifm_data != p->phy.modtype) {

sys/dev/cxgb/cxgb_main.c

2134

KASSERT(p->phy.caps & SUPPORTED_TP && p->phy.caps & SUPPORTED_Autoneg,

sys/dev/cxgb/cxgb_main.c

2135

("%s: unexpected PHY caps 0x%x", __func__, p->phy.caps));

sys/dev/cxgb/cxgb_main.c

2249

if (pi->link_fault || !(pi->phy.caps & SUPPORTED_LINK_IRQ) ||

sys/dev/cxgb/cxgb_main.c

2296

t3_link_start(&p->phy, mac, &p->link_config);

sys/dev/cxgb/cxgb_main.c

2503

struct cphy *phy = &pi->phy;

sys/dev/cxgb/cxgb_main.c

2506

if (!phy->mdio_read)

sys/dev/cxgb/cxgb_main.c

2515

error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd,

sys/dev/cxgb/cxgb_main.c

2518

error = phy->mdio_read(sc, mid->phy_id & 0x1f, 0,

sys/dev/cxgb/cxgb_main.c

2525

struct cphy *phy = &pi->phy;

sys/dev/cxgb/cxgb_main.c

2528

if (!phy->mdio_write)

sys/dev/cxgb/cxgb_main.c

2537

error = phy->mdio_write(sc, mid->phy_id & 0x1f,

sys/dev/cxgb/cxgb_main.c

2540

error = phy->mdio_write(sc, mid->phy_id & 0x1f, 0,

sys/dev/cxgb/cxgb_main.c

967

desc = p->phy.desc;

sys/dev/dc/if_dc.c

2033

int error, mac_offset, n, phy, rid, tmp;

sys/dev/dc/if_dc.c

2420

phy = MII_PHY_ANY;

sys/dev/dc/if_dc.c

2430

phy = DC_ADMTEK_PHYADDR;

sys/dev/dc/if_dc.c

2438

phy = DC_CONEXANT_PHYADDR;

sys/dev/dc/if_dc.c

2441

dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);

sys/dev/dc/if_dc.c

652

dc_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/dc/if_dc.c

660

if (phy == (MII_NPHY - 1)) {

sys/dev/dc/if_dc.c

685

(phy << 23) | (reg << 18));

sys/dev/dc/if_dc.c

699

((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |

sys/dev/dc/if_dc.c

753

rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg);

sys/dev/dc/if_dc.c

761

dc_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/dc/if_dc.c

770

(phy << 23) | (reg << 10) | data);

sys/dev/dc/if_dc.c

780

((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |

sys/dev/dc/if_dc.c

826

mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data);

sys/dev/dpaa/fman_mdio.c

149

pqmdio_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/dpaa/fman_mdio.c

158

MDIO_WRITE4(sc, MDIO_MIIMADD, (phy << 8) | reg);

sys/dev/dpaa/fman_mdio.c

176

pqmdio_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/dpaa/fman_mdio.c

187

MDIO_WRITE4(sc, MDIO_MIIMADD, (phy << 8) | reg);

sys/dev/dpaa/fman_mdio.c

72

static int pqmdio_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/dpaa/fman_mdio.c

73

static int pqmdio_miibus_writereg(device_t dev, int phy, int reg, int value);

sys/dev/dpaa/fman_xmdio.c

184

xmdio_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/dpaa/fman_xmdio.c

195

ctl = (phy << 5) | reg;

sys/dev/dpaa/fman_xmdio.c

212

xmdio_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/dpaa/fman_xmdio.c

221

MDIO_WRITE4(sc, MDIO_CTL, (phy << 5) | reg);

sys/dev/dpaa/fman_xmdio.c

233

xmdio_mdio_readextreg(device_t dev, int phy, int devad, int reg)

sys/dev/dpaa/fman_xmdio.c

244

ctl = (phy << 5) | devad;

sys/dev/dpaa/fman_xmdio.c

265

xmdio_mdio_writeextreg(device_t dev, int phy, int devad, int reg, int val)

sys/dev/dpaa/fman_xmdio.c

274

MDIO_WRITE4(sc, MDIO_CTL, (phy << 5) | devad);

sys/dev/dpaa/fman_xmdio.c

54

static int xmdio_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/dpaa/fman_xmdio.c

55

static int xmdio_miibus_writereg(device_t dev, int phy, int reg, int value);

sys/dev/dpaa/fman_xmdio.c

56

static int xmdio_mdio_readextreg(device_t dev, int phy, int devad, int reg);

sys/dev/dpaa/fman_xmdio.c

57

static int xmdio_mdio_writeextreg(device_t dev, int phy, int devad, int reg,

sys/dev/dpaa/if_dtsec.c

604

dtsec_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/dpaa/if_dtsec.c

610

return (MIIBUS_READREG(sc->sc_base.sc_mdio, phy, reg));

sys/dev/dpaa/if_dtsec.c

614

dtsec_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/dpaa/if_dtsec.c

621

return (MIIBUS_WRITEREG(sc->sc_base.sc_mdio, phy, reg, value));

sys/dev/dpaa/if_dtsec.h

64

int dtsec_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/dpaa/if_dtsec.h

65

int dtsec_miibus_writereg(device_t dev, int phy, int reg,

sys/dev/dpaa/if_memac.c

753

memac_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/dpaa/if_memac.c

759

return (MIIBUS_READREG(sc->sc_base.sc_mdio, phy, reg));

sys/dev/dpaa/if_memac.c

763

memac_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/dpaa/if_memac.c

770

return (MIIBUS_WRITEREG(sc->sc_base.sc_mdio, phy, reg, value));

sys/dev/dpaa/if_memac.h

44

int memac_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/dpaa/if_memac.h

45

int memac_miibus_writereg(device_t dev, int phy, int reg,

sys/dev/dpaa2/dpaa2_mc_fdt.c

77

phy-connection-type = "10gbase-r";

sys/dev/dpaa2/dpaa2_mc_fdt.c

84

phy-handle = <0x18>;

sys/dev/dpaa2/dpaa2_mc_fdt.c

85

phy-connection-type = "qsgmii";

sys/dev/dpaa2/dpaa2_rc.c

2296

uint8_t phy, uint16_t reg, uint16_t *val)

sys/dev/dpaa2/dpaa2_rc.c

2300

uint8_t phy;

sys/dev/dpaa2/dpaa2_rc.c

2312

args->phy = phy;

sys/dev/dpaa2/dpaa2_rc.c

2325

uint8_t phy, uint16_t reg, uint16_t val)

sys/dev/dpaa2/dpaa2_rc.c

2329

uint8_t phy;

sys/dev/dpaa2/dpaa2_rc.c

2341

args->phy = phy;

sys/dev/dpaa2/memac_mdio.h

36

int phy;

sys/dev/dpaa2/memac_mdio_acpi.c

119

sc->scc.phy = sc->phy_channel;

sys/dev/dpaa2/memac_mdio_acpi.c

121

sc->scc.phy = -1;

sys/dev/dpaa2/memac_mdio_acpi.c

128

sc->compatible[0] != '\0' ? sc->compatible : "", sc->scc.phy);

sys/dev/dpaa2/memac_mdio_acpi.c

130

if (sc->scc.phy == -1)

sys/dev/dpaa2/memac_mdio_acpi.c

168

memac_acpi_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/dpaa2/memac_mdio_acpi.c

173

return (memac_miibus_readreg(&sc->scc, phy, reg));

sys/dev/dpaa2/memac_mdio_acpi.c

177

memac_acpi_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/dpaa2/memac_mdio_acpi.c

182

return (memac_miibus_writereg(&sc->scc, phy, reg, data));

sys/dev/dpaa2/memac_mdio_common.c

102

if (sc->phy == -1) {

sys/dev/dpaa2/memac_mdio_common.c

106

*phy_loc = sc->phy;

sys/dev/dpaa2/memac_mdio_common.c

190

memac_miibus_readreg(struct memac_mdio_softc_common *sc, int phy, int reg)

sys/dev/dpaa2/memac_mdio_common.c

205

ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(reg);

sys/dev/dpaa2/memac_mdio_common.c

221

device_printf(sc->dev, "phy read %d:%d = %#06x\n", phy, reg, val);

sys/dev/dpaa2/memac_mdio_common.c

228

memac_miibus_writereg(struct memac_mdio_softc_common *sc, int phy, int reg, int data)

sys/dev/dpaa2/memac_mdio_common.c

233

device_printf(sc->dev, "phy write %d:%d\n", phy, reg);

sys/dev/dpaa2/memac_mdio_common.c

247

ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(reg);

sys/dev/dpaa2/memac_mdio_common.c

53

memacphy_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/dpaa2/memac_mdio_common.c

56

return (MIIBUS_READREG(device_get_parent(dev), phy, reg));

sys/dev/dpaa2/memac_mdio_common.c

60

memacphy_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/dpaa2/memac_mdio_common.c

63

return (MIIBUS_WRITEREG(device_get_parent(dev), phy, reg, data));

sys/dev/dpaa2/memac_mdio_fdt.c

117

sc->scc.phy = sc->reg;

sys/dev/dpaa2/memac_mdio_fdt.c

119

sc->scc.phy = -1;

sys/dev/dpaa2/memac_mdio_fdt.c

128

node, ofw_bus_get_name(dev), sc->reg, sc->xref, sc->scc.phy);

sys/dev/dpaa2/memac_mdio_fdt.c

130

if (sc->scc.phy == -1)

sys/dev/dpaa2/memac_mdio_fdt.c

173

memac_fdt_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/dpaa2/memac_mdio_fdt.c

178

return (memac_miibus_readreg(&sc->scc, phy, reg));

sys/dev/dpaa2/memac_mdio_fdt.c

182

memac_fdt_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/dpaa2/memac_mdio_fdt.c

187

return (memac_miibus_writereg(&sc->scc, phy, reg, data));

sys/dev/dwc/dwc1000_core.c

117

dwc1000_miibus_write_reg(device_t dev, int phy, int reg, int val)

sys/dev/dwc/dwc1000_core.c

125

mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)

sys/dev/dwc/dwc1000_core.c

89

dwc1000_miibus_read_reg(device_t dev, int phy, int reg)

sys/dev/dwc/dwc1000_core.c

98

mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)

sys/dev/dwc/dwc1000_core.h

33

int dwc1000_miibus_read_reg(device_t dev, int phy, int reg);

sys/dev/dwc/dwc1000_core.h

34

int dwc1000_miibus_write_reg(device_t dev, int phy, int reg, int val);

sys/dev/e1000/e1000_80003es2lan.c

1002

switch (phy->mdix) {

sys/dev/e1000/e1000_80003es2lan.c

102

phy->addr = 1;

sys/dev/e1000/e1000_80003es2lan.c

1022

if (phy->disable_polarity_correction)

sys/dev/e1000/e1000_80003es2lan.c

1025

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);

sys/dev/e1000/e1000_80003es2lan.c

103

phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

sys/dev/e1000/e1000_80003es2lan.c

1030

ret_val = hw->phy.ops.commit(hw);

sys/dev/e1000/e1000_80003es2lan.c

104

phy->reset_delay_us = 100;

sys/dev/e1000/e1000_80003es2lan.c

105

phy->type = e1000_phy_gg82563;

sys/dev/e1000/e1000_80003es2lan.c

1053

ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);

sys/dev/e1000/e1000_80003es2lan.c

1058

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);

sys/dev/e1000/e1000_80003es2lan.c

1066

ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);

sys/dev/e1000/e1000_80003es2lan.c

107

phy->ops.acquire = e1000_acquire_phy_80003es2lan;

sys/dev/e1000/e1000_80003es2lan.c

1077

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,

sys/dev/e1000/e1000_80003es2lan.c

108

phy->ops.check_polarity = e1000_check_polarity_m88;

sys/dev/e1000/e1000_80003es2lan.c

1082

ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,

sys/dev/e1000/e1000_80003es2lan.c

1088

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,

sys/dev/e1000/e1000_80003es2lan.c

109

phy->ops.check_reset_block = e1000_check_reset_block_generic;

sys/dev/e1000/e1000_80003es2lan.c

1097

ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);

sys/dev/e1000/e1000_80003es2lan.c

110

phy->ops.commit = e1000_phy_sw_reset_generic;

sys/dev/e1000/e1000_80003es2lan.c

1102

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);

sys/dev/e1000/e1000_80003es2lan.c

111

phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;

sys/dev/e1000/e1000_80003es2lan.c

112

phy->ops.get_info = e1000_get_phy_info_m88;

sys/dev/e1000/e1000_80003es2lan.c

113

phy->ops.release = e1000_release_phy_80003es2lan;

sys/dev/e1000/e1000_80003es2lan.c

114

phy->ops.reset = e1000_phy_hw_reset_generic;

sys/dev/e1000/e1000_80003es2lan.c

115

phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;

sys/dev/e1000/e1000_80003es2lan.c

117

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;

sys/dev/e1000/e1000_80003es2lan.c

118

phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;

sys/dev/e1000/e1000_80003es2lan.c

1182

if (hw->phy.media_type == e1000_media_type_copper) {

sys/dev/e1000/e1000_80003es2lan.c

119

phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;

sys/dev/e1000/e1000_80003es2lan.c

120

phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;

sys/dev/e1000/e1000_80003es2lan.c

122

phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;

sys/dev/e1000/e1000_80003es2lan.c

1229

ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,

sys/dev/e1000/e1000_80003es2lan.c

1234

ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,

sys/dev/e1000/e1000_80003es2lan.c

1246

return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);

sys/dev/e1000/e1000_80003es2lan.c

128

if (phy->id != GG82563_E_PHY_ID)

sys/dev/e1000/e1000_80003es2lan.c

1280

ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,

sys/dev/e1000/e1000_80003es2lan.c

1285

ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,

sys/dev/e1000/e1000_80003es2lan.c

1294

return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);

sys/dev/e1000/e1000_80003es2lan.c

1400

hw->phy.ops.check_reset_block(hw)))

sys/dev/e1000/e1000_80003es2lan.c

203

hw->phy.media_type = e1000_media_type_internal_serdes;

sys/dev/e1000/e1000_80003es2lan.c

209

hw->phy.media_type = e1000_media_type_copper;

sys/dev/e1000/e1000_80003es2lan.c

284

hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;

sys/dev/e1000/e1000_80003es2lan.c

597

if (!(hw->phy.ops.read_reg))

sys/dev/e1000/e1000_80003es2lan.c

603

ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

sys/dev/e1000/e1000_80003es2lan.c

608

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);

sys/dev/e1000/e1000_80003es2lan.c

614

ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);

sys/dev/e1000/e1000_80003es2lan.c

623

ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);

sys/dev/e1000/e1000_80003es2lan.c

629

if (hw->phy.autoneg_wait_to_complete) {

sys/dev/e1000/e1000_80003es2lan.c

653

ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,

sys/dev/e1000/e1000_80003es2lan.c

671

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,

sys/dev/e1000/e1000_80003es2lan.c

686

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_80003es2lan.c

692

if (!(hw->phy.ops.read_reg))

sys/dev/e1000/e1000_80003es2lan.c

695

ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);

sys/dev/e1000/e1000_80003es2lan.c

704

phy->min_cable_length = e1000_gg82563_cable_length_table[index];

sys/dev/e1000/e1000_80003es2lan.c

705

phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];

sys/dev/e1000/e1000_80003es2lan.c

707

phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;

sys/dev/e1000/e1000_80003es2lan.c

727

if (hw->phy.media_type == e1000_media_type_copper) {

sys/dev/e1000/e1000_80003es2lan.c

730

hw->phy.ops.cfg_on_link_up(hw);

sys/dev/e1000/e1000_80003es2lan.c

89

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_80003es2lan.c

94

if (hw->phy.media_type != e1000_media_type_copper) {

sys/dev/e1000/e1000_80003es2lan.c

940

if (hw->phy.media_type != e1000_media_type_copper)

sys/dev/e1000/e1000_80003es2lan.c

95

phy->type = e1000_phy_none;

sys/dev/e1000/e1000_80003es2lan.c

970

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_80003es2lan.c

977

ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);

sys/dev/e1000/e1000_80003es2lan.c

98

phy->ops.power_up = e1000_power_up_phy_copper;

sys/dev/e1000/e1000_80003es2lan.c

985

ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);

sys/dev/e1000/e1000_80003es2lan.c

99

phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;

sys/dev/e1000/e1000_80003es2lan.c

996

ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);

sys/dev/e1000/e1000_82540.c

100

if (phy->id == M88E1011_I_PHY_ID)

sys/dev/e1000/e1000_82540.c

171

hw->phy.media_type = e1000_media_type_fiber;

sys/dev/e1000/e1000_82540.c

175

hw->phy.media_type = e1000_media_type_internal_serdes;

sys/dev/e1000/e1000_82540.c

178

hw->phy.media_type = e1000_media_type_copper;

sys/dev/e1000/e1000_82540.c

201

(hw->phy.media_type == e1000_media_type_copper)

sys/dev/e1000/e1000_82540.c

205

switch (hw->phy.media_type) {

sys/dev/e1000/e1000_82540.c

222

(hw->phy.media_type == e1000_media_type_copper)

sys/dev/e1000/e1000_82540.c

261

hw->phy.ops.init_params = e1000_init_phy_params_82540;

sys/dev/e1000/e1000_82540.c

430

ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,

sys/dev/e1000/e1000_82540.c

435

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,

sys/dev/e1000/e1000_82540.c

470

if (hw->phy.media_type == e1000_media_type_internal_serdes) {

sys/dev/e1000/e1000_82540.c

513

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL,

sys/dev/e1000/e1000_82540.c

539

ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT,

sys/dev/e1000/e1000_82540.c

544

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);

sys/dev/e1000/e1000_82540.c

548

ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);

sys/dev/e1000/e1000_82540.c

553

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);

sys/dev/e1000/e1000_82540.c

559

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);

sys/dev/e1000/e1000_82540.c

563

ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);

sys/dev/e1000/e1000_82540.c

568

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);

sys/dev/e1000/e1000_82540.c

572

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,

sys/dev/e1000/e1000_82540.c

605

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,

sys/dev/e1000/e1000_82540.c

611

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL,

sys/dev/e1000/e1000_82540.c

68

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82540.c

71

phy->addr = 1;

sys/dev/e1000/e1000_82540.c

72

phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

sys/dev/e1000/e1000_82540.c

73

phy->reset_delay_us = 10000;

sys/dev/e1000/e1000_82540.c

74

phy->type = e1000_phy_m88;

sys/dev/e1000/e1000_82540.c

77

phy->ops.check_polarity = e1000_check_polarity_m88;

sys/dev/e1000/e1000_82540.c

78

phy->ops.commit = e1000_phy_sw_reset_generic;

sys/dev/e1000/e1000_82540.c

79

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;

sys/dev/e1000/e1000_82540.c

80

phy->ops.get_cable_length = e1000_get_cable_length_m88;

sys/dev/e1000/e1000_82540.c

81

phy->ops.get_cfg_done = e1000_get_cfg_done_generic;

sys/dev/e1000/e1000_82540.c

82

phy->ops.read_reg = e1000_read_phy_reg_m88;

sys/dev/e1000/e1000_82540.c

83

phy->ops.reset = e1000_phy_hw_reset_generic;

sys/dev/e1000/e1000_82540.c

84

phy->ops.write_reg = e1000_write_phy_reg_m88;

sys/dev/e1000/e1000_82540.c

85

phy->ops.get_info = e1000_get_phy_info_m88;

sys/dev/e1000/e1000_82540.c

86

phy->ops.power_up = e1000_power_up_phy_copper;

sys/dev/e1000/e1000_82540.c

87

phy->ops.power_down = e1000_power_down_phy_copper_82540;

sys/dev/e1000/e1000_82541.c

100

phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;

sys/dev/e1000/e1000_82541.c

1000

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_82541.c

1006

} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||

sys/dev/e1000/e1000_82541.c

1007

(phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||

sys/dev/e1000/e1000_82541.c

1008

(phy->autoneg_advertised == E1000_ALL_10_SPEED)) {

sys/dev/e1000/e1000_82541.c

101

phy->ops.get_cfg_done = e1000_get_cfg_done_generic;

sys/dev/e1000/e1000_82541.c

1010

ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);

sys/dev/e1000/e1000_82541.c

1015

ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,

sys/dev/e1000/e1000_82541.c

102

phy->ops.get_info = e1000_get_phy_info_igp;

sys/dev/e1000/e1000_82541.c

1021

ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,

sys/dev/e1000/e1000_82541.c

103

phy->ops.read_reg = e1000_read_phy_reg_igp;

sys/dev/e1000/e1000_82541.c

104

phy->ops.reset = e1000_phy_hw_reset_82541;

sys/dev/e1000/e1000_82541.c

1043

ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,

sys/dev/e1000/e1000_82541.c

1048

ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,

sys/dev/e1000/e1000_82541.c

105

phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;

sys/dev/e1000/e1000_82541.c

106

phy->ops.write_reg = e1000_write_phy_reg_igp;

sys/dev/e1000/e1000_82541.c

107

phy->ops.power_up = e1000_power_up_phy_copper;

sys/dev/e1000/e1000_82541.c

1074

ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,

sys/dev/e1000/e1000_82541.c

108

phy->ops.power_down = e1000_power_down_phy_copper_82541;

sys/dev/e1000/e1000_82541.c

1111

ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);

sys/dev/e1000/e1000_82541.c

1114

hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);

sys/dev/e1000/e1000_82541.c

1118

hw->phy.ops.write_reg(hw, 0x0000, 0x0140);

sys/dev/e1000/e1000_82541.c

1125

hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);

sys/dev/e1000/e1000_82541.c

1127

hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);

sys/dev/e1000/e1000_82541.c

1129

hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);

sys/dev/e1000/e1000_82541.c

1131

hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);

sys/dev/e1000/e1000_82541.c

1133

hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);

sys/dev/e1000/e1000_82541.c

1135

hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);

sys/dev/e1000/e1000_82541.c

1137

hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);

sys/dev/e1000/e1000_82541.c

1139

hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);

sys/dev/e1000/e1000_82541.c

1141

hw->phy.ops.write_reg(hw, 0x2010, 0x0008);

sys/dev/e1000/e1000_82541.c

1145

hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);

sys/dev/e1000/e1000_82541.c

115

if (phy->id != IGP01E1000_I_PHY_ID) {

sys/dev/e1000/e1000_82541.c

1151

hw->phy.ops.write_reg(hw, 0x0000, 0x3300);

sys/dev/e1000/e1000_82541.c

1156

hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);

sys/dev/e1000/e1000_82541.c

1162

hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS,

sys/dev/e1000/e1000_82541.c

1166

hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS,

sys/dev/e1000/e1000_82541.c

1183

hw->phy.ops.write_reg(hw,

sys/dev/e1000/e1000_82541.c

1186

hw->phy.ops.write_reg(hw,

sys/dev/e1000/e1000_82541.c

1210

if (hw->phy.type != e1000_phy_igp) {

sys/dev/e1000/e1000_82541.c

226

hw->phy.media_type = e1000_media_type_copper;

sys/dev/e1000/e1000_82541.c

287

hw->phy.ops.init_params = e1000_init_phy_params_82541;

sys/dev/e1000/e1000_82541.c

391

ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,

sys/dev/e1000/e1000_82541.c

447

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82541.c

457

if (!phy->speed_downgraded)

sys/dev/e1000/e1000_82541.c

466

ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);

sys/dev/e1000/e1000_82541.c

473

ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);

sys/dev/e1000/e1000_82541.c

535

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82541.c

551

phy->mdix = 1;

sys/dev/e1000/e1000_82541.c

671

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82541.c

697

ret_val = phy->ops.get_cable_length(hw);

sys/dev/e1000/e1000_82541.c

702

phy->min_cable_length >= 50) {

sys/dev/e1000/e1000_82541.c

705

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_82541.c

713

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_82541.c

723

(phy->min_cable_length >= 50)) {

sys/dev/e1000/e1000_82541.c

729

ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);

sys/dev/e1000/e1000_82541.c

735

ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS,

sys/dev/e1000/e1000_82541.c

744

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_82541.c

762

ret_val = phy->ops.read_reg(hw, 0x2F5B,

sys/dev/e1000/e1000_82541.c

768

ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);

sys/dev/e1000/e1000_82541.c

774

ret_val = phy->ops.write_reg(hw, 0x0000,

sys/dev/e1000/e1000_82541.c

779

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_82541.c

788

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_82541.c

795

ret_val = phy->ops.write_reg(hw, 0x0000,

sys/dev/e1000/e1000_82541.c

803

ret_val = phy->ops.write_reg(hw, 0x2F5B,

sys/dev/e1000/e1000_82541.c

820

ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);

sys/dev/e1000/e1000_82541.c

825

ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);

sys/dev/e1000/e1000_82541.c

831

ret_val = phy->ops.write_reg(hw, 0x0000,

sys/dev/e1000/e1000_82541.c

836

ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_DSP_FFE,

sys/dev/e1000/e1000_82541.c

841

ret_val = phy->ops.write_reg(hw, 0x0000,

sys/dev/e1000/e1000_82541.c

849

ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);

sys/dev/e1000/e1000_82541.c

87

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82541.c

874

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82541.c

888

ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);

sys/dev/e1000/e1000_82541.c

917

phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >

sys/dev/e1000/e1000_82541.c

92

phy->addr = 1;

sys/dev/e1000/e1000_82541.c

922

phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +

sys/dev/e1000/e1000_82541.c

925

phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;

sys/dev/e1000/e1000_82541.c

93

phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

sys/dev/e1000/e1000_82541.c

94

phy->reset_delay_us = 10000;

sys/dev/e1000/e1000_82541.c

947

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82541.c

95

phy->type = e1000_phy_igp;

sys/dev/e1000/e1000_82541.c

963

ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);

sys/dev/e1000/e1000_82541.c

969

ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);

sys/dev/e1000/e1000_82541.c

979

if (phy->smart_speed == e1000_smart_speed_on) {

sys/dev/e1000/e1000_82541.c

98

phy->ops.check_polarity = e1000_check_polarity_igp;

sys/dev/e1000/e1000_82541.c

980

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_82541.c

987

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_82541.c

99

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;

sys/dev/e1000/e1000_82541.c

992

} else if (phy->smart_speed == e1000_smart_speed_off) {

sys/dev/e1000/e1000_82541.c

993

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_82542.c

107

hw->phy.media_type = e1000_media_type_fiber;

sys/dev/e1000/e1000_82542.c

165

hw->phy.ops.init_params = e1000_init_phy_params_82542;

sys/dev/e1000/e1000_82542.c

60

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82542.c

65

phy->type = e1000_phy_none;

sys/dev/e1000/e1000_82543.c

100

phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

sys/dev/e1000/e1000_82543.c

101

phy->reset_delay_us = 10000;

sys/dev/e1000/e1000_82543.c

102

phy->type = e1000_phy_m88;

sys/dev/e1000/e1000_82543.c

105

phy->ops.check_polarity = e1000_check_polarity_m88;

sys/dev/e1000/e1000_82543.c

106

phy->ops.commit = e1000_phy_sw_reset_generic;

sys/dev/e1000/e1000_82543.c

107

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;

sys/dev/e1000/e1000_82543.c

1078

ret_val = hw->phy.ops.reset(hw);

sys/dev/e1000/e1000_82543.c

108

phy->ops.get_cable_length = e1000_get_cable_length_m88;

sys/dev/e1000/e1000_82543.c

109

phy->ops.get_cfg_done = e1000_get_cfg_done_generic;

sys/dev/e1000/e1000_82543.c

110

phy->ops.read_reg = (hw->mac.type == e1000_82543)

sys/dev/e1000/e1000_82543.c

113

phy->ops.reset = (hw->mac.type == e1000_82543)

sys/dev/e1000/e1000_82543.c

116

phy->ops.write_reg = (hw->mac.type == e1000_82543)

sys/dev/e1000/e1000_82543.c

119

phy->ops.get_info = e1000_get_phy_info_m88;

sys/dev/e1000/e1000_82543.c

127

ret_val = phy->ops.reset(hw);

sys/dev/e1000/e1000_82543.c

1411

if (!(hw->phy.ops.read_reg))

sys/dev/e1000/e1000_82543.c

142

if (phy->id != M88E1000_E_PHY_ID) {

sys/dev/e1000/e1000_82543.c

1423

ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);

sys/dev/e1000/e1000_82543.c

148

if (phy->id != M88E1000_I_PHY_ID) {

sys/dev/e1000/e1000_82543.c

1487

hw->phy.media_type == e1000_media_type_copper) {

sys/dev/e1000/e1000_82543.c

1514

hw->phy.media_type == e1000_media_type_copper) {

sys/dev/e1000/e1000_82543.c

203

hw->phy.media_type = e1000_media_type_fiber;

sys/dev/e1000/e1000_82543.c

206

hw->phy.media_type = e1000_media_type_copper;

sys/dev/e1000/e1000_82543.c

229

(hw->phy.media_type == e1000_media_type_copper)

sys/dev/e1000/e1000_82543.c

233

(hw->phy.media_type == e1000_media_type_copper)

sys/dev/e1000/e1000_82543.c

238

(hw->phy.media_type == e1000_media_type_copper)

sys/dev/e1000/e1000_82543.c

257

(hw->phy.media_type == e1000_media_type_fiber))

sys/dev/e1000/e1000_82543.c

275

hw->phy.ops.init_params = e1000_init_phy_params_82543;

sys/dev/e1000/e1000_82543.c

519

mdic = (offset | (hw->phy.addr << 5) |

sys/dev/e1000/e1000_82543.c

571

mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |

sys/dev/e1000/e1000_82543.c

774

if (!(hw->phy.ops.write_reg))

sys/dev/e1000/e1000_82543.c

781

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);

sys/dev/e1000/e1000_82543.c

784

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);

sys/dev/e1000/e1000_82543.c

788

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);

sys/dev/e1000/e1000_82543.c

802

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);

sys/dev/e1000/e1000_82543.c

806

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);

sys/dev/e1000/e1000_82543.c

820

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);

sys/dev/e1000/e1000_82543.c

824

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);

sys/dev/e1000/e1000_82543.c

828

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);

sys/dev/e1000/e1000_82543.c

832

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);

sys/dev/e1000/e1000_82543.c

836

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);

sys/dev/e1000/e1000_82543.c

86

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82543.c

887

if (!(hw->phy.ops.get_cfg_done))

sys/dev/e1000/e1000_82543.c

890

ret_val = hw->phy.ops.get_cfg_done(hw);

sys/dev/e1000/e1000_82543.c

91

if (hw->phy.media_type != e1000_media_type_copper) {

sys/dev/e1000/e1000_82543.c

92

phy->type = e1000_phy_none;

sys/dev/e1000/e1000_82543.c

95

phy->ops.power_up = e1000_power_up_phy_copper;

sys/dev/e1000/e1000_82543.c

96

phy->ops.power_down = e1000_power_down_phy_copper;

sys/dev/e1000/e1000_82543.c

99

phy->addr = 1;

sys/dev/e1000/e1000_82571.c

103

phy->addr = 1;

sys/dev/e1000/e1000_82571.c

104

phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

sys/dev/e1000/e1000_82571.c

105

phy->reset_delay_us = 100;

sys/dev/e1000/e1000_82571.c

1057

if (hw->phy.media_type == e1000_media_type_internal_serdes)

sys/dev/e1000/e1000_82571.c

107

phy->ops.check_reset_block = e1000_check_reset_block_generic;

sys/dev/e1000/e1000_82571.c

108

phy->ops.reset = e1000_phy_hw_reset_generic;

sys/dev/e1000/e1000_82571.c

109

phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;

sys/dev/e1000/e1000_82571.c

110

phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;

sys/dev/e1000/e1000_82571.c

111

phy->ops.power_up = e1000_power_up_phy_copper;

sys/dev/e1000/e1000_82571.c

112

phy->ops.power_down = e1000_power_down_phy_copper_82571;

sys/dev/e1000/e1000_82571.c

117

phy->type = e1000_phy_igp_2;

sys/dev/e1000/e1000_82571.c

118

phy->ops.get_cfg_done = e1000_get_cfg_done_82571;

sys/dev/e1000/e1000_82571.c

119

phy->ops.get_info = e1000_get_phy_info_igp;

sys/dev/e1000/e1000_82571.c

120

phy->ops.check_polarity = e1000_check_polarity_igp;

sys/dev/e1000/e1000_82571.c

121

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;

sys/dev/e1000/e1000_82571.c

122

phy->ops.get_cable_length = e1000_get_cable_length_igp_2;

sys/dev/e1000/e1000_82571.c

123

phy->ops.read_reg = e1000_read_phy_reg_igp;

sys/dev/e1000/e1000_82571.c

124

phy->ops.write_reg = e1000_write_phy_reg_igp;

sys/dev/e1000/e1000_82571.c

125

phy->ops.acquire = e1000_get_hw_semaphore;

sys/dev/e1000/e1000_82571.c

126

phy->ops.release = e1000_put_hw_semaphore;

sys/dev/e1000/e1000_82571.c

129

phy->type = e1000_phy_m88;

sys/dev/e1000/e1000_82571.c

130

phy->ops.get_cfg_done = e1000_get_cfg_done_generic;

sys/dev/e1000/e1000_82571.c

131

phy->ops.get_info = e1000_get_phy_info_m88;

sys/dev/e1000/e1000_82571.c

132

phy->ops.check_polarity = e1000_check_polarity_m88;

sys/dev/e1000/e1000_82571.c

133

phy->ops.commit = e1000_phy_sw_reset_generic;

sys/dev/e1000/e1000_82571.c

134

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;

sys/dev/e1000/e1000_82571.c

135

phy->ops.get_cable_length = e1000_get_cable_length_m88;

sys/dev/e1000/e1000_82571.c

136

phy->ops.read_reg = e1000_read_phy_reg_m88;

sys/dev/e1000/e1000_82571.c

137

phy->ops.write_reg = e1000_write_phy_reg_m88;

sys/dev/e1000/e1000_82571.c

138

phy->ops.acquire = e1000_get_hw_semaphore;

sys/dev/e1000/e1000_82571.c

139

phy->ops.release = e1000_put_hw_semaphore;

sys/dev/e1000/e1000_82571.c

1392

ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,

sys/dev/e1000/e1000_82571.c

1397

ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,

sys/dev/e1000/e1000_82571.c

144

phy->type = e1000_phy_bm;

sys/dev/e1000/e1000_82571.c

145

phy->ops.get_cfg_done = e1000_get_cfg_done_generic;

sys/dev/e1000/e1000_82571.c

146

phy->ops.get_info = e1000_get_phy_info_m88;

sys/dev/e1000/e1000_82571.c

1462

switch (hw->phy.type) {

sys/dev/e1000/e1000_82571.c

147

phy->ops.check_polarity = e1000_check_polarity_m88;

sys/dev/e1000/e1000_82571.c

148

phy->ops.commit = e1000_phy_sw_reset_generic;

sys/dev/e1000/e1000_82571.c

149

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;

sys/dev/e1000/e1000_82571.c

150

phy->ops.get_cable_length = e1000_get_cable_length_m88;

sys/dev/e1000/e1000_82571.c

151

phy->ops.read_reg = e1000_read_phy_reg_bm2;

sys/dev/e1000/e1000_82571.c

152

phy->ops.write_reg = e1000_write_phy_reg_bm2;

sys/dev/e1000/e1000_82571.c

153

phy->ops.acquire = e1000_get_hw_semaphore_82574;

sys/dev/e1000/e1000_82571.c

154

phy->ops.release = e1000_put_hw_semaphore_82574;

sys/dev/e1000/e1000_82571.c

155

phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;

sys/dev/e1000/e1000_82571.c

156

phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;

sys/dev/e1000/e1000_82571.c

174

if (phy->id != IGP01E1000_I_PHY_ID)

sys/dev/e1000/e1000_82571.c

178

if (phy->id != M88E1111_I_PHY_ID)

sys/dev/e1000/e1000_82571.c

183

if (phy->id != BME1000_E_PHY_ID_R2)

sys/dev/e1000/e1000_82571.c

1852

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82571.c

1855

if (!phy->ops.check_reset_block)

sys/dev/e1000/e1000_82571.c

1859

if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))

sys/dev/e1000/e1000_82571.c

192

DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);

sys/dev/e1000/e1000_82571.c

296

hw->phy.media_type = e1000_media_type_fiber;

sys/dev/e1000/e1000_82571.c

307

hw->phy.media_type = e1000_media_type_internal_serdes;

sys/dev/e1000/e1000_82571.c

315

hw->phy.media_type = e1000_media_type_copper;

sys/dev/e1000/e1000_82571.c

450

hw->phy.ops.init_params = e1000_init_phy_params_82571;

sys/dev/e1000/e1000_82571.c

462

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82571.c

476

phy->id = IGP01E1000_I_PHY_ID;

sys/dev/e1000/e1000_82571.c

483

ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);

sys/dev/e1000/e1000_82571.c

487

phy->id = (u32)(phy_id << 16);

sys/dev/e1000/e1000_82571.c

489

ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);

sys/dev/e1000/e1000_82571.c

493

phy->id |= (u32)(phy_id);

sys/dev/e1000/e1000_82571.c

494

phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

sys/dev/e1000/e1000_82571.c

608

} else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||

sys/dev/e1000/e1000_82571.c

609

(hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||

sys/dev/e1000/e1000_82571.c

610

(hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {

sys/dev/e1000/e1000_82571.c

872

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82571.c

878

if (!(phy->ops.read_reg))

sys/dev/e1000/e1000_82571.c

881

ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);

sys/dev/e1000/e1000_82571.c

887

ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,

sys/dev/e1000/e1000_82571.c

893

ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,

sys/dev/e1000/e1000_82571.c

898

ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,

sys/dev/e1000/e1000_82571.c

904

ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,

sys/dev/e1000/e1000_82571.c

911

if (phy->smart_speed == e1000_smart_speed_on) {

sys/dev/e1000/e1000_82571.c

912

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_82571.c

919

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_82571.c

924

} else if (phy->smart_speed == e1000_smart_speed_off) {

sys/dev/e1000/e1000_82571.c

925

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_82571.c

93

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82571.c

932

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_82571.c

98

if (hw->phy.media_type != e1000_media_type_copper) {

sys/dev/e1000/e1000_82571.c

99

phy->type = e1000_phy_none;

sys/dev/e1000/e1000_82575.c

1026

(hw->phy.type == e1000_phy_igp_3))

sys/dev/e1000/e1000_82575.c

1049

if (hw->phy.media_type != e1000_media_type_copper)

sys/dev/e1000/e1000_82575.c

1073

if (hw->phy.media_type != e1000_media_type_copper) {

sys/dev/e1000/e1000_82575.c

1107

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82575.c

1115

ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);

sys/dev/e1000/e1000_82575.c

1119

ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);

sys/dev/e1000/e1000_82575.c

1127

ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);

sys/dev/e1000/e1000_82575.c

1131

ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);

sys/dev/e1000/e1000_82575.c

1146

ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);

sys/dev/e1000/e1000_82575.c

1153

ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);

sys/dev/e1000/e1000_82575.c

1171

if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&

sys/dev/e1000/e1000_82575.c

1269

if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&

sys/dev/e1000/e1000_82575.c

1437

ret_val = hw->phy.ops.reset(hw);

sys/dev/e1000/e1000_82575.c

1443

switch (hw->phy.type) {

sys/dev/e1000/e1000_82575.c

1447

switch (hw->phy.id) {

sys/dev/e1000/e1000_82575.c

1503

if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&

sys/dev/e1000/e1000_82575.c

160

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82575.c

1656

hw->phy.media_type = e1000_media_type_internal_serdes;

sys/dev/e1000/e1000_82575.c

1659

hw->phy.media_type = e1000_media_type_copper;

sys/dev/e1000/e1000_82575.c

166

phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;

sys/dev/e1000/e1000_82575.c

1664

hw->phy.media_type = e1000_media_type_copper;

sys/dev/e1000/e1000_82575.c

167

phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;

sys/dev/e1000/e1000_82575.c

1674

(hw->phy.media_type == e1000_media_type_unknown)) {

sys/dev/e1000/e1000_82575.c

1679

hw->phy.media_type = e1000_media_type_internal_serdes;

sys/dev/e1000/e1000_82575.c

1682

hw->phy.media_type = e1000_media_type_copper;

sys/dev/e1000/e1000_82575.c

169

if (hw->phy.media_type != e1000_media_type_copper) {

sys/dev/e1000/e1000_82575.c

170

phy->type = e1000_phy_none;

sys/dev/e1000/e1000_82575.c

174

phy->ops.power_up = e1000_power_up_phy_copper;

sys/dev/e1000/e1000_82575.c

175

phy->ops.power_down = e1000_power_down_phy_copper_base;

sys/dev/e1000/e1000_82575.c

1758

hw->phy.media_type = e1000_media_type_internal_serdes;

sys/dev/e1000/e1000_82575.c

1762

hw->phy.media_type = e1000_media_type_internal_serdes;

sys/dev/e1000/e1000_82575.c

1766

hw->phy.media_type = e1000_media_type_copper;

sys/dev/e1000/e1000_82575.c

1769

hw->phy.media_type = e1000_media_type_unknown;

sys/dev/e1000/e1000_82575.c

177

phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

sys/dev/e1000/e1000_82575.c

178

phy->reset_delay_us = 100;

sys/dev/e1000/e1000_82575.c

180

phy->ops.acquire = e1000_acquire_phy_base;

sys/dev/e1000/e1000_82575.c

1801

switch (hw->phy.media_type) {

sys/dev/e1000/e1000_82575.c

181

phy->ops.check_reset_block = e1000_check_reset_block_generic;

sys/dev/e1000/e1000_82575.c

182

phy->ops.commit = e1000_phy_sw_reset_generic;

sys/dev/e1000/e1000_82575.c

183

phy->ops.get_cfg_done = e1000_get_cfg_done_82575;

sys/dev/e1000/e1000_82575.c

184

phy->ops.release = e1000_release_phy_base;

sys/dev/e1000/e1000_82575.c

189

phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;

sys/dev/e1000/e1000_82575.c

192

phy->ops.reset = e1000_phy_hw_reset_generic;

sys/dev/e1000/e1000_82575.c

1974

if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||

sys/dev/e1000/e1000_82575.c

200

phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;

sys/dev/e1000/e1000_82575.c

201

phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;

sys/dev/e1000/e1000_82575.c

207

phy->ops.read_reg = e1000_read_phy_reg_82580;

sys/dev/e1000/e1000_82575.c

208

phy->ops.write_reg = e1000_write_phy_reg_82580;

sys/dev/e1000/e1000_82575.c

212

phy->ops.read_reg = e1000_read_phy_reg_gs40g;

sys/dev/e1000/e1000_82575.c

213

phy->ops.write_reg = e1000_write_phy_reg_gs40g;

sys/dev/e1000/e1000_82575.c

2140

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_82575.c

2146

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_82575.c

216

phy->ops.read_reg = e1000_read_phy_reg_igp;

sys/dev/e1000/e1000_82575.c

2166

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_82575.c

217

phy->ops.write_reg = e1000_write_phy_reg_igp;

sys/dev/e1000/e1000_82575.c

2172

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_82575.c

225

switch (phy->id) {

sys/dev/e1000/e1000_82575.c

231

phy->type = e1000_phy_m88;

sys/dev/e1000/e1000_82575.c

232

phy->ops.check_polarity = e1000_check_polarity_m88;

sys/dev/e1000/e1000_82575.c

233

phy->ops.get_info = e1000_get_phy_info_m88;

sys/dev/e1000/e1000_82575.c

234

phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;

sys/dev/e1000/e1000_82575.c

235

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;

sys/dev/e1000/e1000_82575.c

238

phy->type = e1000_phy_m88;

sys/dev/e1000/e1000_82575.c

239

phy->ops.check_polarity = e1000_check_polarity_m88;

sys/dev/e1000/e1000_82575.c

240

phy->ops.get_info = e1000_get_phy_info_m88;

sys/dev/e1000/e1000_82575.c

241

phy->ops.get_cable_length = e1000_get_cable_length_m88;

sys/dev/e1000/e1000_82575.c

242

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;

sys/dev/e1000/e1000_82575.c

246

phy->type = e1000_phy_igp_3;

sys/dev/e1000/e1000_82575.c

247

phy->ops.check_polarity = e1000_check_polarity_igp;

sys/dev/e1000/e1000_82575.c

248

phy->ops.get_info = e1000_get_phy_info_igp;

sys/dev/e1000/e1000_82575.c

249

phy->ops.get_cable_length = e1000_get_cable_length_igp_2;

sys/dev/e1000/e1000_82575.c

250

phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;

sys/dev/e1000/e1000_82575.c

251

phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;

sys/dev/e1000/e1000_82575.c

252

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;

sys/dev/e1000/e1000_82575.c

256

phy->type = e1000_phy_82580;

sys/dev/e1000/e1000_82575.c

2560

ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);

sys/dev/e1000/e1000_82575.c

2565

ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);

sys/dev/e1000/e1000_82575.c

2567

ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);

sys/dev/e1000/e1000_82575.c

257

phy->ops.check_polarity = e1000_check_polarity_82577;

sys/dev/e1000/e1000_82575.c

258

phy->ops.get_info = e1000_get_phy_info_82577;

sys/dev/e1000/e1000_82575.c

259

phy->ops.get_cable_length = e1000_get_cable_length_82577;

sys/dev/e1000/e1000_82575.c

2593

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82575.c

2599

if (phy->id != M88E1512_E_PHY_ID)

sys/dev/e1000/e1000_82575.c

260

phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;

sys/dev/e1000/e1000_82575.c

2603

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);

sys/dev/e1000/e1000_82575.c

2607

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);

sys/dev/e1000/e1000_82575.c

261

phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;

sys/dev/e1000/e1000_82575.c

2611

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);

sys/dev/e1000/e1000_82575.c

2615

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);

sys/dev/e1000/e1000_82575.c

2619

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);

sys/dev/e1000/e1000_82575.c

262

phy->ops.force_speed_duplex =

sys/dev/e1000/e1000_82575.c

2623

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);

sys/dev/e1000/e1000_82575.c

2627

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);

sys/dev/e1000/e1000_82575.c

2631

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);

sys/dev/e1000/e1000_82575.c

2635

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);

sys/dev/e1000/e1000_82575.c

2640

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);

sys/dev/e1000/e1000_82575.c

2644

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);

sys/dev/e1000/e1000_82575.c

2649

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);

sys/dev/e1000/e1000_82575.c

2654

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);

sys/dev/e1000/e1000_82575.c

2659

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);

sys/dev/e1000/e1000_82575.c

266

phy->type = e1000_phy_i210;

sys/dev/e1000/e1000_82575.c

2663

ret_val = phy->ops.commit(hw);

sys/dev/e1000/e1000_82575.c

267

phy->ops.check_polarity = e1000_check_polarity_m88;

sys/dev/e1000/e1000_82575.c

268

phy->ops.get_info = e1000_get_phy_info_m88;

sys/dev/e1000/e1000_82575.c

2682

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82575.c

2688

if (phy->id != M88E1543_E_PHY_ID)

sys/dev/e1000/e1000_82575.c

269

phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;

sys/dev/e1000/e1000_82575.c

2692

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);

sys/dev/e1000/e1000_82575.c

2696

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);

sys/dev/e1000/e1000_82575.c

270

phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;

sys/dev/e1000/e1000_82575.c

2700

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);

sys/dev/e1000/e1000_82575.c

2704

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);

sys/dev/e1000/e1000_82575.c

2708

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);

sys/dev/e1000/e1000_82575.c

271

phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;

sys/dev/e1000/e1000_82575.c

2712

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);

sys/dev/e1000/e1000_82575.c

2716

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);

sys/dev/e1000/e1000_82575.c

272

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;

sys/dev/e1000/e1000_82575.c

2720

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);

sys/dev/e1000/e1000_82575.c

2724

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);

sys/dev/e1000/e1000_82575.c

2729

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);

sys/dev/e1000/e1000_82575.c

2733

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);

sys/dev/e1000/e1000_82575.c

2738

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);

sys/dev/e1000/e1000_82575.c

2743

ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);

sys/dev/e1000/e1000_82575.c

2748

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);

sys/dev/e1000/e1000_82575.c

2753

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);

sys/dev/e1000/e1000_82575.c

2758

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);

sys/dev/e1000/e1000_82575.c

2762

ret_val = phy->ops.commit(hw);

sys/dev/e1000/e1000_82575.c

2789

(hw->phy.media_type != e1000_media_type_copper))

sys/dev/e1000/e1000_82575.c

280

switch (phy->id) {

sys/dev/e1000/e1000_82575.c

2839

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82575.c

2845

if ((hw->phy.media_type != e1000_media_type_copper) ||

sys/dev/e1000/e1000_82575.c

2846

((phy->id != M88E1543_E_PHY_ID) &&

sys/dev/e1000/e1000_82575.c

2847

(phy->id != M88E1512_E_PHY_ID)))

sys/dev/e1000/e1000_82575.c

285

ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2);

sys/dev/e1000/e1000_82575.c

2852

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);

sys/dev/e1000/e1000_82575.c

2856

ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,

sys/dev/e1000/e1000_82575.c

2862

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,

sys/dev/e1000/e1000_82575.c

2868

ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);

sys/dev/e1000/e1000_82575.c

288

ret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1,

sys/dev/e1000/e1000_82575.c

2921

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82575.c

2928

if ((hw->phy.media_type != e1000_media_type_copper) ||

sys/dev/e1000/e1000_82575.c

2929

((phy->id != M88E1543_E_PHY_ID) &&

sys/dev/e1000/e1000_82575.c

2930

(phy->id != M88E1512_E_PHY_ID)))

sys/dev/e1000/e1000_82575.c

382

(hw->phy.media_type == e1000_media_type_copper)

sys/dev/e1000/e1000_82575.c

531

hw->phy.ops.init_params = e1000_init_phy_params_82575;

sys/dev/e1000/e1000_82575.c

556

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_82575.c

562

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_82575.c

589

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_82575.c

595

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_82575.c

610

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82575.c

630

phy->addr = 1;

sys/dev/e1000/e1000_82575.c

641

phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;

sys/dev/e1000/e1000_82575.c

650

phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;

sys/dev/e1000/e1000_82575.c

672

for (phy->addr = 1; phy->addr < 8; phy->addr++) {

sys/dev/e1000/e1000_82575.c

676

phy_id, phy->addr);

sys/dev/e1000/e1000_82575.c

685

phy->addr);

sys/dev/e1000/e1000_82575.c

690

if (phy->addr == 8) {

sys/dev/e1000/e1000_82575.c

691

phy->addr = 0;

sys/dev/e1000/e1000_82575.c

713

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82575.c

724

if (!(hw->phy.ops.write_reg))

sys/dev/e1000/e1000_82575.c

731

ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);

sys/dev/e1000/e1000_82575.c

735

ret_val = hw->phy.ops.commit(hw);

sys/dev/e1000/e1000_82575.c

739

if (phy->id == M88E1512_E_PHY_ID)

sys/dev/e1000/e1000_82575.c

760

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82575.c

766

if (!(hw->phy.ops.read_reg))

sys/dev/e1000/e1000_82575.c

769

ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);

sys/dev/e1000/e1000_82575.c

775

ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,

sys/dev/e1000/e1000_82575.c

781

ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,

sys/dev/e1000/e1000_82575.c

784

ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,

sys/dev/e1000/e1000_82575.c

790

ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,

sys/dev/e1000/e1000_82575.c

798

if (phy->smart_speed == e1000_smart_speed_on) {

sys/dev/e1000/e1000_82575.c

799

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_82575.c

806

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_82575.c

811

} else if (phy->smart_speed == e1000_smart_speed_off) {

sys/dev/e1000/e1000_82575.c

812

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_82575.c

819

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_82575.c

846

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82575.c

867

if (phy->smart_speed == e1000_smart_speed_on)

sys/dev/e1000/e1000_82575.c

869

else if (phy->smart_speed == e1000_smart_speed_off)

sys/dev/e1000/e1000_82575.c

893

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_82575.c

908

if (phy->smart_speed == e1000_smart_speed_on)

sys/dev/e1000/e1000_82575.c

910

else if (phy->smart_speed == e1000_smart_speed_off)

sys/dev/e1000/e1000_82575.c

912

} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||

sys/dev/e1000/e1000_82575.c

913

(phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||

sys/dev/e1000/e1000_82575.c

914

(phy->autoneg_advertised == E1000_ALL_10_SPEED)) {

sys/dev/e1000/e1000_api.c

100

if (hw->phy.ops.init_params) {

sys/dev/e1000/e1000_api.c

101

ret_val = hw->phy.ops.init_params(hw);

sys/dev/e1000/e1000_api.c

1027

if (hw->phy.ops.check_reset_block)

sys/dev/e1000/e1000_api.c

1028

return hw->phy.ops.check_reset_block(hw);

sys/dev/e1000/e1000_api.c

1044

if (hw->phy.ops.read_reg)

sys/dev/e1000/e1000_api.c

1045

return hw->phy.ops.read_reg(hw, offset, data);

sys/dev/e1000/e1000_api.c

1061

if (hw->phy.ops.write_reg)

sys/dev/e1000/e1000_api.c

1062

return hw->phy.ops.write_reg(hw, offset, data);

sys/dev/e1000/e1000_api.c

1076

if (hw->phy.ops.release)

sys/dev/e1000/e1000_api.c

1077

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_api.c

1089

if (hw->phy.ops.acquire)

sys/dev/e1000/e1000_api.c

1090

return hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_api.c

1101

if (hw->phy.ops.cfg_on_link_up)

sys/dev/e1000/e1000_api.c

1102

return hw->phy.ops.cfg_on_link_up(hw);

sys/dev/e1000/e1000_api.c

1147

if (hw->phy.ops.get_cable_length)

sys/dev/e1000/e1000_api.c

1148

return hw->phy.ops.get_cable_length(hw);

sys/dev/e1000/e1000_api.c

1163

if (hw->phy.ops.get_info)

sys/dev/e1000/e1000_api.c

1164

return hw->phy.ops.get_info(hw);

sys/dev/e1000/e1000_api.c

1178

if (hw->phy.ops.reset)

sys/dev/e1000/e1000_api.c

1179

return hw->phy.ops.reset(hw);

sys/dev/e1000/e1000_api.c

1193

if (hw->phy.ops.commit)

sys/dev/e1000/e1000_api.c

1194

return hw->phy.ops.commit(hw);

sys/dev/e1000/e1000_api.c

1215

if (hw->phy.ops.set_d0_lplu_state)

sys/dev/e1000/e1000_api.c

1216

return hw->phy.ops.set_d0_lplu_state(hw, active);

sys/dev/e1000/e1000_api.c

1237

if (hw->phy.ops.set_d3_lplu_state)

sys/dev/e1000/e1000_api.c

1238

return hw->phy.ops.set_d3_lplu_state(hw, active);

sys/dev/e1000/e1000_api.c

1409

if (hw->phy.ops.power_up)

sys/dev/e1000/e1000_api.c

1410

hw->phy.ops.power_up(hw);

sys/dev/e1000/e1000_api.c

1424

if (hw->phy.ops.power_down)

sys/dev/e1000/e1000_api.c

1425

hw->phy.ops.power_down(hw);

sys/dev/e1000/e1000_base.c

134

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_base.c

136

if (!(phy->ops.check_reset_block))

sys/dev/e1000/e1000_base.c

140

if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))

sys/dev/e1000/e1000_hw.h

1047

struct e1000_phy_info phy;

sys/dev/e1000/e1000_i210.c

687

switch (hw->phy.media_type) {

sys/dev/e1000/e1000_i210.c

716

hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_i210.c

771

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_i210.c

822

hw->phy.ops.get_cfg_done = e1000_get_cfg_done_i210;

sys/dev/e1000/e1000_ich8lan.c

1003

ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);

sys/dev/e1000/e1000_ich8lan.c

1005

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

1029

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

1057

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

1062

if ((hw->phy.revision > 5) || !link ||

sys/dev/e1000/e1000_ich8lan.c

1067

ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);

sys/dev/e1000/e1000_ich8lan.c

1089

ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);

sys/dev/e1000/e1000_ich8lan.c

1318

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

1337

if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {

sys/dev/e1000/e1000_ich8lan.c

1385

if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&

sys/dev/e1000/e1000_ich8lan.c

1394

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

1472

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

1538

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

1540

hw->phy.ops.reset(hw);

sys/dev/e1000/e1000_ich8lan.c

1619

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

1631

hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,

sys/dev/e1000/e1000_ich8lan.c

1638

hw->phy.ops.write_reg_locked(hw,

sys/dev/e1000/e1000_ich8lan.c

1643

hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,

sys/dev/e1000/e1000_ich8lan.c

1648

hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,

sys/dev/e1000/e1000_ich8lan.c

1652

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

1662

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

1666

ret_val = hw->phy.ops.read_reg_locked(hw,

sys/dev/e1000/e1000_ich8lan.c

1670

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

1679

hw->phy.ops.write_reg_locked(hw,

sys/dev/e1000/e1000_ich8lan.c

1682

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

1686

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

1690

ret_val = hw->phy.ops.write_reg_locked(hw,

sys/dev/e1000/e1000_ich8lan.c

1693

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

1770

if (hw->phy.type == e1000_phy_82578) {

sys/dev/e1000/e1000_ich8lan.c

1781

hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);

sys/dev/e1000/e1000_ich8lan.c

1788

hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);

sys/dev/e1000/e1000_ich8lan.c

1800

if (hw->phy.type > e1000_phy_82579) {

sys/dev/e1000/e1000_ich8lan.c

1846

hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

1857

hw->phy.ops.init_params = e1000_init_phy_params_pchlan;

sys/dev/e1000/e1000_ich8lan.c

210

ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);

sys/dev/e1000/e1000_ich8lan.c

215

ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);

sys/dev/e1000/e1000_ich8lan.c

2183

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

2192

hw->phy.ops.write_reg_page(hw, BM_MTA(i),

sys/dev/e1000/e1000_ich8lan.c

2195

hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),

sys/dev/e1000/e1000_ich8lan.c

2203

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

224

if (hw->phy.id) {

sys/dev/e1000/e1000_ich8lan.c

225

if (hw->phy.id == phy_id)

sys/dev/e1000/e1000_ich8lan.c

2259

if (hw->phy.type == e1000_phy_i217) {

sys/dev/e1000/e1000_ich8lan.c

228

hw->phy.id = phy_id;

sys/dev/e1000/e1000_ich8lan.c

2284

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_ich8lan.c

229

hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);

sys/dev/e1000/e1000_ich8lan.c

2299

if (phy->type != e1000_phy_igp_3)

sys/dev/e1000/e1000_ich8lan.c

2323

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

237

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

2392

ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,

sys/dev/e1000/e1000_ich8lan.c

2399

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

241

hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

2425

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

2431

if (hw->phy.type == e1000_phy_82578) {

sys/dev/e1000/e1000_ich8lan.c

2432

ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,

sys/dev/e1000/e1000_ich8lan.c

2447

if (hw->phy.type == e1000_phy_82577) {

sys/dev/e1000/e1000_ich8lan.c

2448

ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,

sys/dev/e1000/e1000_ich8lan.c

2464

ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),

sys/dev/e1000/e1000_ich8lan.c

2471

ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),

sys/dev/e1000/e1000_ich8lan.c

2480

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

252

hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);

sys/dev/e1000/e1000_ich8lan.c

254

hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);

sys/dev/e1000/e1000_ich8lan.c

2559

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

2575

ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);

sys/dev/e1000/e1000_ich8lan.c

2599

!hw->phy.ops.check_reset_block(hw))

sys/dev/e1000/e1000_ich8lan.c

2602

ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);

sys/dev/e1000/e1000_ich8lan.c

2605

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

2622

ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);

sys/dev/e1000/e1000_ich8lan.c

2628

ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);

sys/dev/e1000/e1000_ich8lan.c

2649

if (hw->phy.type == e1000_phy_82577) {

sys/dev/e1000/e1000_ich8lan.c

2655

if (((hw->phy.type == e1000_phy_82577) &&

sys/dev/e1000/e1000_ich8lan.c

2656

((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||

sys/dev/e1000/e1000_ich8lan.c

2657

((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {

sys/dev/e1000/e1000_ich8lan.c

2659

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);

sys/dev/e1000/e1000_ich8lan.c

2664

ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,

sys/dev/e1000/e1000_ich8lan.c

2670

if (hw->phy.type == e1000_phy_82578) {

sys/dev/e1000/e1000_ich8lan.c

2674

if (hw->phy.revision < 2) {

sys/dev/e1000/e1000_ich8lan.c

2676

ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,

sys/dev/e1000/e1000_ich8lan.c

2684

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

2688

hw->phy.addr = 1;

sys/dev/e1000/e1000_ich8lan.c

2690

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

2702

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

2705

ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

2708

ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,

sys/dev/e1000/e1000_ich8lan.c

2716

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

2733

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

2743

hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),

sys/dev/e1000/e1000_ich8lan.c

2745

hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),

sys/dev/e1000/e1000_ich8lan.c

2749

hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),

sys/dev/e1000/e1000_ich8lan.c

2751

hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),

sys/dev/e1000/e1000_ich8lan.c

2759

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

2799

hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);

sys/dev/e1000/e1000_ich8lan.c

2800

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),

sys/dev/e1000/e1000_ich8lan.c

2865

hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);

sys/dev/e1000/e1000_ich8lan.c

2868

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);

sys/dev/e1000/e1000_ich8lan.c

2871

hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);

sys/dev/e1000/e1000_ich8lan.c

2873

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);

sys/dev/e1000/e1000_ich8lan.c

2876

hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);

sys/dev/e1000/e1000_ich8lan.c

2879

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);

sys/dev/e1000/e1000_ich8lan.c

2882

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);

sys/dev/e1000/e1000_ich8lan.c

2885

hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);

sys/dev/e1000/e1000_ich8lan.c

2886

ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |

sys/dev/e1000/e1000_ich8lan.c

2924

hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);

sys/dev/e1000/e1000_ich8lan.c

2926

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);

sys/dev/e1000/e1000_ich8lan.c

2929

hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);

sys/dev/e1000/e1000_ich8lan.c

2931

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);

sys/dev/e1000/e1000_ich8lan.c

2934

hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);

sys/dev/e1000/e1000_ich8lan.c

2937

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);

sys/dev/e1000/e1000_ich8lan.c

2940

ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);

sys/dev/e1000/e1000_ich8lan.c

2943

hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);

sys/dev/e1000/e1000_ich8lan.c

2944

ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &

sys/dev/e1000/e1000_ich8lan.c

2951

return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &

sys/dev/e1000/e1000_ich8lan.c

2974

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

2984

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

3007

ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);

sys/dev/e1000/e1000_ich8lan.c

3018

ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,

sys/dev/e1000/e1000_ich8lan.c

3023

ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,

sys/dev/e1000/e1000_ich8lan.c

3110

if (hw->phy.ops.check_reset_block(hw))

sys/dev/e1000/e1000_ich8lan.c

3134

hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);

sys/dev/e1000/e1000_ich8lan.c

3136

hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);

sys/dev/e1000/e1000_ich8lan.c

3156

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

3162

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

3211

ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);

sys/dev/e1000/e1000_ich8lan.c

3220

if (!hw->phy.ops.check_reset_block(hw))

sys/dev/e1000/e1000_ich8lan.c

3223

return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);

sys/dev/e1000/e1000_ich8lan.c

3241

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_ich8lan.c

3248

if (phy->type == e1000_phy_ife)

sys/dev/e1000/e1000_ich8lan.c

3257

if (phy->type != e1000_phy_igp_3)

sys/dev/e1000/e1000_ich8lan.c

3267

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_ich8lan.c

3273

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_ich8lan.c

3282

if (phy->type != e1000_phy_igp_3)

sys/dev/e1000/e1000_ich8lan.c

3290

if (phy->smart_speed == e1000_smart_speed_on) {

sys/dev/e1000/e1000_ich8lan.c

3291

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_ich8lan.c

3298

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_ich8lan.c

3303

} else if (phy->smart_speed == e1000_smart_speed_off) {

sys/dev/e1000/e1000_ich8lan.c

3304

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_ich8lan.c

3311

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_ich8lan.c

3337

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_ich8lan.c

3350

if (phy->type != e1000_phy_igp_3)

sys/dev/e1000/e1000_ich8lan.c

3358

if (phy->smart_speed == e1000_smart_speed_on) {

sys/dev/e1000/e1000_ich8lan.c

3359

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_ich8lan.c

3366

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_ich8lan.c

337

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

3371

} else if (phy->smart_speed == e1000_smart_speed_off) {

sys/dev/e1000/e1000_ich8lan.c

3372

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_ich8lan.c

3379

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_ich8lan.c

3385

} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||

sys/dev/e1000/e1000_ich8lan.c

3386

(phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||

sys/dev/e1000/e1000_ich8lan.c

3387

(phy->autoneg_advertised == E1000_ALL_10_SPEED)) {

sys/dev/e1000/e1000_ich8lan.c

3391

if (phy->type != e1000_phy_igp_3)

sys/dev/e1000/e1000_ich8lan.c

3401

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_ich8lan.c

3408

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_ich8lan.c

382

if (hw->phy.ops.check_reset_block(hw)) {

sys/dev/e1000/e1000_ich8lan.c

411

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

415

if (hw->phy.ops.check_reset_block(hw)) {

sys/dev/e1000/e1000_ich8lan.c

435

ret_val = hw->phy.ops.check_reset_block(hw);

sys/dev/e1000/e1000_ich8lan.c

459

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_ich8lan.c

464

phy->addr = 1;

sys/dev/e1000/e1000_ich8lan.c

465

phy->reset_delay_us = 100;

sys/dev/e1000/e1000_ich8lan.c

467

phy->ops.acquire = e1000_acquire_swflag_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

468

phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

469

phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

470

phy->ops.set_page = e1000_set_page_igp;

sys/dev/e1000/e1000_ich8lan.c

471

phy->ops.read_reg = e1000_read_phy_reg_hv;

sys/dev/e1000/e1000_ich8lan.c

472

phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;

sys/dev/e1000/e1000_ich8lan.c

473

phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;

sys/dev/e1000/e1000_ich8lan.c

474

phy->ops.release = e1000_release_swflag_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

475

phy->ops.reset = e1000_phy_hw_reset_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

476

phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;

sys/dev/e1000/e1000_ich8lan.c

477

phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;

sys/dev/e1000/e1000_ich8lan.c

478

phy->ops.write_reg = e1000_write_phy_reg_hv;

sys/dev/e1000/e1000_ich8lan.c

479

phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;

sys/dev/e1000/e1000_ich8lan.c

480

phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;

sys/dev/e1000/e1000_ich8lan.c

481

phy->ops.power_up = e1000_power_up_phy_copper;

sys/dev/e1000/e1000_ich8lan.c

482

phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

483

phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

sys/dev/e1000/e1000_ich8lan.c

485

phy->id = e1000_phy_unknown;

sys/dev/e1000/e1000_ich8lan.c

491

if (phy->id == e1000_phy_unknown)

sys/dev/e1000/e1000_ich8lan.c

497

if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))

sys/dev/e1000/e1000_ich8lan.c

5027

if (!hw->phy.ops.check_reset_block(hw)) {

sys/dev/e1000/e1000_ich8lan.c

5074

ret_val = hw->phy.ops.get_cfg_done(hw);

sys/dev/e1000/e1000_ich8lan.c

5141

if (hw->phy.type == e1000_phy_82578) {

sys/dev/e1000/e1000_ich8lan.c

5142

hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);

sys/dev/e1000/e1000_ich8lan.c

5144

hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);

sys/dev/e1000/e1000_ich8lan.c

519

phy->type = e1000_get_phy_type_from_id(phy->id);

sys/dev/e1000/e1000_ich8lan.c

521

switch (phy->type) {

sys/dev/e1000/e1000_ich8lan.c

525

phy->ops.check_polarity = e1000_check_polarity_82577;

sys/dev/e1000/e1000_ich8lan.c

526

phy->ops.force_speed_duplex =

sys/dev/e1000/e1000_ich8lan.c

528

phy->ops.get_cable_length = e1000_get_cable_length_82577;

sys/dev/e1000/e1000_ich8lan.c

529

phy->ops.get_info = e1000_get_phy_info_82577;

sys/dev/e1000/e1000_ich8lan.c

530

phy->ops.commit = e1000_phy_sw_reset_generic;

sys/dev/e1000/e1000_ich8lan.c

5309

if (!hw->phy.ops.check_reset_block(hw)) {

sys/dev/e1000/e1000_ich8lan.c

5317

if ((hw->phy.type == e1000_phy_82578) ||

sys/dev/e1000/e1000_ich8lan.c

5318

(hw->phy.type == e1000_phy_82579) ||

sys/dev/e1000/e1000_ich8lan.c

5319

(hw->phy.type == e1000_phy_i217) ||

sys/dev/e1000/e1000_ich8lan.c

5320

(hw->phy.type == e1000_phy_82577)) {

sys/dev/e1000/e1000_ich8lan.c

5323

ret_val = hw->phy.ops.write_reg(hw,

sys/dev/e1000/e1000_ich8lan.c

533

phy->ops.check_polarity = e1000_check_polarity_m88;

sys/dev/e1000/e1000_ich8lan.c

534

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;

sys/dev/e1000/e1000_ich8lan.c

535

phy->ops.get_cable_length = e1000_get_cable_length_m88;

sys/dev/e1000/e1000_ich8lan.c

536

phy->ops.get_info = e1000_get_phy_info_m88;

sys/dev/e1000/e1000_ich8lan.c

5374

switch (hw->phy.type) {

sys/dev/e1000/e1000_ich8lan.c

5393

ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,

sys/dev/e1000/e1000_ich8lan.c

5400

switch (hw->phy.mdix) {

sys/dev/e1000/e1000_ich8lan.c

5412

ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,

sys/dev/e1000/e1000_ich8lan.c

5473

(hw->phy.type == e1000_phy_igp_3) &&

sys/dev/e1000/e1000_ich8lan.c

5519

ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);

sys/dev/e1000/e1000_ich8lan.c

5523

ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);

sys/dev/e1000/e1000_ich8lan.c

5532

hw->phy.ops.reset(hw);

sys/dev/e1000/e1000_ich8lan.c

554

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_ich8lan.c

5593

if (hw->phy.type != e1000_phy_igp_3)

sys/dev/e1000/e1000_ich8lan.c

560

phy->addr = 1;

sys/dev/e1000/e1000_ich8lan.c

561

phy->reset_delay_us = 100;

sys/dev/e1000/e1000_ich8lan.c

5611

hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);

sys/dev/e1000/e1000_ich8lan.c

5613

hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,

sys/dev/e1000/e1000_ich8lan.c

5617

hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);

sys/dev/e1000/e1000_ich8lan.c

563

phy->ops.acquire = e1000_acquire_swflag_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

564

phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

5647

(hw->phy.type == e1000_phy_ife))

sys/dev/e1000/e1000_ich8lan.c

565

phy->ops.get_cable_length = e1000_get_cable_length_igp_2;

sys/dev/e1000/e1000_ich8lan.c

566

phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

567

phy->ops.read_reg = e1000_read_phy_reg_igp;

sys/dev/e1000/e1000_ich8lan.c

568

phy->ops.release = e1000_release_swflag_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

569

phy->ops.reset = e1000_phy_hw_reset_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

5690

if (hw->phy.type == e1000_phy_i217) {

sys/dev/e1000/e1000_ich8lan.c

570

phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

5704

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

571

phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

572

phy->ops.write_reg = e1000_write_phy_reg_igp;

sys/dev/e1000/e1000_ich8lan.c

5726

(hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {

sys/dev/e1000/e1000_ich8lan.c

573

phy->ops.power_up = e1000_power_up_phy_copper;

sys/dev/e1000/e1000_ich8lan.c

5731

hw->phy.ops.read_reg_locked(hw,

sys/dev/e1000/e1000_ich8lan.c

5735

hw->phy.ops.write_reg_locked(hw,

sys/dev/e1000/e1000_ich8lan.c

574

phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

5751

hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,

sys/dev/e1000/e1000_ich8lan.c

5754

hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,

sys/dev/e1000/e1000_ich8lan.c

5760

hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);

sys/dev/e1000/e1000_ich8lan.c

5762

hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);

sys/dev/e1000/e1000_ich8lan.c

5765

hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);

sys/dev/e1000/e1000_ich8lan.c

5767

hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);

sys/dev/e1000/e1000_ich8lan.c

5773

hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);

sys/dev/e1000/e1000_ich8lan.c

5775

hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);

sys/dev/e1000/e1000_ich8lan.c

5778

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

5793

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

5797

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

581

phy->ops.write_reg = e1000_write_phy_reg_bm;

sys/dev/e1000/e1000_ich8lan.c

582

phy->ops.read_reg = e1000_read_phy_reg_bm;

sys/dev/e1000/e1000_ich8lan.c

5832

if (hw->phy.type == e1000_phy_i217) {

sys/dev/e1000/e1000_ich8lan.c

5835

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

5842

hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);

sys/dev/e1000/e1000_ich8lan.c

5844

hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);

sys/dev/e1000/e1000_ich8lan.c

5851

ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,

sys/dev/e1000/e1000_ich8lan.c

5856

hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);

sys/dev/e1000/e1000_ich8lan.c

5859

hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);

sys/dev/e1000/e1000_ich8lan.c

5862

ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,

sys/dev/e1000/e1000_ich8lan.c

5867

hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);

sys/dev/e1000/e1000_ich8lan.c

5871

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

5887

if (hw->phy.type == e1000_phy_ife)

sys/dev/e1000/e1000_ich8lan.c

5888

return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,

sys/dev/e1000/e1000_ich8lan.c

590

phy->id = 0;

sys/dev/e1000/e1000_ich8lan.c

5905

if (hw->phy.type == e1000_phy_ife)

sys/dev/e1000/e1000_ich8lan.c

5906

return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,

sys/dev/e1000/e1000_ich8lan.c

591

while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&

sys/dev/e1000/e1000_ich8lan.c

5923

if (hw->phy.type == e1000_phy_ife)

sys/dev/e1000/e1000_ich8lan.c

5924

return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,

sys/dev/e1000/e1000_ich8lan.c

5941

return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,

sys/dev/e1000/e1000_ich8lan.c

5955

return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,

sys/dev/e1000/e1000_ich8lan.c

5988

return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);

sys/dev/e1000/e1000_ich8lan.c

600

switch (phy->id) {

sys/dev/e1000/e1000_ich8lan.c

602

phy->type = e1000_phy_igp_3;

sys/dev/e1000/e1000_ich8lan.c

6020

return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);

sys/dev/e1000/e1000_ich8lan.c

603

phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

sys/dev/e1000/e1000_ich8lan.c

604

phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;

sys/dev/e1000/e1000_ich8lan.c

605

phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;

sys/dev/e1000/e1000_ich8lan.c

606

phy->ops.get_info = e1000_get_phy_info_igp;

sys/dev/e1000/e1000_ich8lan.c

607

phy->ops.check_polarity = e1000_check_polarity_igp;

sys/dev/e1000/e1000_ich8lan.c

6070

(hw->phy.type == e1000_phy_igp_3)) {

sys/dev/e1000/e1000_ich8lan.c

608

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;

sys/dev/e1000/e1000_ich8lan.c

6095

hw->phy.ops.check_reset_block(hw)))

sys/dev/e1000/e1000_ich8lan.c

613

phy->type = e1000_phy_ife;

sys/dev/e1000/e1000_ich8lan.c

6132

if ((hw->phy.type == e1000_phy_82578) ||

sys/dev/e1000/e1000_ich8lan.c

6133

(hw->phy.type == e1000_phy_82579) ||

sys/dev/e1000/e1000_ich8lan.c

6134

(hw->phy.type == e1000_phy_i217) ||

sys/dev/e1000/e1000_ich8lan.c

6135

(hw->phy.type == e1000_phy_82577)) {

sys/dev/e1000/e1000_ich8lan.c

6136

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

6139

ret_val = hw->phy.ops.set_page(hw,

sys/dev/e1000/e1000_ich8lan.c

614

phy->autoneg_mask = E1000_ALL_NOT_GIG;

sys/dev/e1000/e1000_ich8lan.c

6143

hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

6144

hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

6145

hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

6146

hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

6147

hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

6148

hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

6149

hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

615

phy->ops.get_info = e1000_get_phy_info_ife;

sys/dev/e1000/e1000_ich8lan.c

6150

hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

6151

hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

6152

hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

6153

hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

6154

hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

6155

hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

6156

hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);

sys/dev/e1000/e1000_ich8lan.c

6158

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_ich8lan.c

616

phy->ops.check_polarity = e1000_check_polarity_ife;

sys/dev/e1000/e1000_ich8lan.c

617

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;

sys/dev/e1000/e1000_ich8lan.c

620

phy->type = e1000_phy_bm;

sys/dev/e1000/e1000_ich8lan.c

621

phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

sys/dev/e1000/e1000_ich8lan.c

622

phy->ops.read_reg = e1000_read_phy_reg_bm;

sys/dev/e1000/e1000_ich8lan.c

623

phy->ops.write_reg = e1000_write_phy_reg_bm;

sys/dev/e1000/e1000_ich8lan.c

624

phy->ops.commit = e1000_phy_sw_reset_generic;

sys/dev/e1000/e1000_ich8lan.c

625

phy->ops.get_info = e1000_get_phy_info_m88;

sys/dev/e1000/e1000_ich8lan.c

626

phy->ops.check_polarity = e1000_check_polarity_m88;

sys/dev/e1000/e1000_ich8lan.c

627

phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;

sys/dev/e1000/e1000_ich8lan.c

741

hw->phy.media_type = e1000_media_type_copper;

sys/dev/e1000/e1000_ich8lan.c

862

ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);

sys/dev/e1000/e1000_ich8lan.c

867

ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,

sys/dev/e1000/e1000_ich8lan.c

870

ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,

sys/dev/e1000/e1000_ich8lan.c

928

switch (hw->phy.type) {

sys/dev/e1000/e1000_ich8lan.c

943

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_ich8lan.c

947

ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);

sys/dev/e1000/e1000_ich8lan.c

974

hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);

sys/dev/e1000/e1000_ich8lan.c

987

if (hw->phy.type == e1000_phy_82579) {

sys/dev/e1000/e1000_mac.c

1018

if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))

sys/dev/e1000/e1000_mac.c

1217

if (hw->phy.media_type == e1000_media_type_internal_serdes ||

sys/dev/e1000/e1000_mac.c

1373

if (hw->phy.media_type == e1000_media_type_fiber ||

sys/dev/e1000/e1000_mac.c

1374

hw->phy.media_type == e1000_media_type_internal_serdes)

sys/dev/e1000/e1000_mac.c

1377

if (hw->phy.media_type == e1000_media_type_copper)

sys/dev/e1000/e1000_mac.c

1391

if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {

sys/dev/e1000/e1000_mac.c

1396

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);

sys/dev/e1000/e1000_mac.c

1399

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);

sys/dev/e1000/e1000_mac.c

1414

ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,

sys/dev/e1000/e1000_mac.c

1418

ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,

sys/dev/e1000/e1000_mac.c

1535

if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&

sys/dev/e1000/e1000_mac.c

1851

if (hw->phy.media_type == e1000_media_type_fiber) {

sys/dev/e1000/e1000_mac.c

1860

} else if (hw->phy.media_type == e1000_media_type_copper) {

sys/dev/e1000/e1000_mac.c

1895

if (hw->phy.media_type == e1000_media_type_fiber) {

sys/dev/e1000/e1000_mac.c

1941

switch (hw->phy.media_type) {

sys/dev/e1000/e1000_mac.c

1970

switch (hw->phy.media_type) {

sys/dev/e1000/e1000_mac.c

2132

if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {

sys/dev/e1000/e1000_mac.c

2134

hw->phy.mdix = 1;

sys/dev/e1000/e1000_phy.c

100

phy->ops.cfg_on_link_up = e1000_null_ops_generic;

sys/dev/e1000/e1000_phy.c

1020

ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);

sys/dev/e1000/e1000_phy.c

1025

hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?

sys/dev/e1000/e1000_phy.c

1030

switch (hw->phy.ms_type) {

sys/dev/e1000/e1000_phy.c

1045

return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);

sys/dev/e1000/e1000_phy.c

1061

if (hw->phy.type == e1000_phy_82580) {

sys/dev/e1000/e1000_phy.c

1062

ret_val = hw->phy.ops.reset(hw);

sys/dev/e1000/e1000_phy.c

1070

ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);

sys/dev/e1000/e1000_phy.c

1079

ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);

sys/dev/e1000/e1000_phy.c

1084

ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);

sys/dev/e1000/e1000_phy.c

1093

switch (hw->phy.mdix) {

sys/dev/e1000/e1000_phy.c

1105

ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);

sys/dev/e1000/e1000_phy.c

1121

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

1129

ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

sys/dev/e1000/e1000_phy.c

1134

if (phy->type != e1000_phy_bm)

sys/dev/e1000/e1000_phy.c

1146

switch (phy->mdix) {

sys/dev/e1000/e1000_phy.c

1170

if (phy->disable_polarity_correction)

sys/dev/e1000/e1000_phy.c

1174

if (phy->type == e1000_phy_bm) {

sys/dev/e1000/e1000_phy.c

1176

if (phy->id == BME1000_E_PHY_ID_R2) {

sys/dev/e1000/e1000_phy.c

1178

ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,

sys/dev/e1000/e1000_phy.c

1183

ret_val = phy->ops.commit(hw);

sys/dev/e1000/e1000_phy.c

1193

ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

sys/dev/e1000/e1000_phy.c

1197

if ((phy->type == e1000_phy_m88) &&

sys/dev/e1000/e1000_phy.c

1198

(phy->revision < E1000_REVISION_4) &&

sys/dev/e1000/e1000_phy.c

1199

(phy->id != BME1000_E_PHY_ID_R2)) {

sys/dev/e1000/e1000_phy.c

1203

ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,

sys/dev/e1000/e1000_phy.c

1210

if ((phy->revision == E1000_REVISION_2) &&

sys/dev/e1000/e1000_phy.c

1211

(phy->id == M88E1111_I_PHY_ID)) {

sys/dev/e1000/e1000_phy.c

1222

ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,

sys/dev/e1000/e1000_phy.c

1228

if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {

sys/dev/e1000/e1000_phy.c

1230

ret_val = phy->ops.write_reg(hw, 29, 0x0003);

sys/dev/e1000/e1000_phy.c

1235

ret_val = phy->ops.write_reg(hw, 30, 0x0000);

sys/dev/e1000/e1000_phy.c

1241

ret_val = phy->ops.commit(hw);

sys/dev/e1000/e1000_phy.c

1247

if (phy->type == e1000_phy_82578) {

sys/dev/e1000/e1000_phy.c

1248

ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,

sys/dev/e1000/e1000_phy.c

1256

ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,

sys/dev/e1000/e1000_phy.c

1274

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

1282

ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

sys/dev/e1000/e1000_phy.c

1295

switch (phy->mdix) {

sys/dev/e1000/e1000_phy.c

1304

if (phy->id != M88E1112_E_PHY_ID) {

sys/dev/e1000/e1000_phy.c

1323

if (phy->disable_polarity_correction)

sys/dev/e1000/e1000_phy.c

1327

if (phy->id == M88E1543_E_PHY_ID) {

sys/dev/e1000/e1000_phy.c

1330

phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

sys/dev/e1000/e1000_phy.c

1334

ret_val = phy->ops.commit(hw);

sys/dev/e1000/e1000_phy.c

1345

ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

sys/dev/e1000/e1000_phy.c

1350

ret_val = phy->ops.commit(hw);

sys/dev/e1000/e1000_phy.c

1372

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

1379

ret_val = hw->phy.ops.reset(hw);

sys/dev/e1000/e1000_phy.c

1393

if (phy->type == e1000_phy_igp) {

sys/dev/e1000/e1000_phy.c

1395

ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);

sys/dev/e1000/e1000_phy.c

1403

if (hw->phy.ops.set_d0_lplu_state) {

sys/dev/e1000/e1000_phy.c

1404

ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);

sys/dev/e1000/e1000_phy.c

1411

ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);

sys/dev/e1000/e1000_phy.c

1417

switch (phy->mdix) {

sys/dev/e1000/e1000_phy.c

1430

ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);

sys/dev/e1000/e1000_phy.c

1440

if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {

sys/dev/e1000/e1000_phy.c

1442

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_phy.c

1449

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_phy.c

1456

ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);

sys/dev/e1000/e1000_phy.c

1461

ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);

sys/dev/e1000/e1000_phy.c

1483

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

1490

phy->autoneg_advertised &= phy->autoneg_mask;

sys/dev/e1000/e1000_phy.c

1493

ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);

sys/dev/e1000/e1000_phy.c

1497

if (phy->autoneg_mask & ADVERTISE_1000_FULL) {

sys/dev/e1000/e1000_phy.c

1499

ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,

sys/dev/e1000/e1000_phy.c

1522

DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);

sys/dev/e1000/e1000_phy.c

1525

if (phy->autoneg_advertised & ADVERTISE_10_HALF) {

sys/dev/e1000/e1000_phy.c

1531

if (phy->autoneg_advertised & ADVERTISE_10_FULL) {

sys/dev/e1000/e1000_phy.c

1537

if (phy->autoneg_advertised & ADVERTISE_100_HALF) {

sys/dev/e1000/e1000_phy.c

1543

if (phy->autoneg_advertised & ADVERTISE_100_FULL) {

sys/dev/e1000/e1000_phy.c

1549

if (phy->autoneg_advertised & ADVERTISE_1000_HALF)

sys/dev/e1000/e1000_phy.c

1553

if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {

sys/dev/e1000/e1000_phy.c

1612

ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);

sys/dev/e1000/e1000_phy.c

1618

if (phy->autoneg_mask & ADVERTISE_1000_FULL)

sys/dev/e1000/e1000_phy.c

1619

ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,

sys/dev/e1000/e1000_phy.c

1636

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

1645

phy->autoneg_advertised &= phy->autoneg_mask;

sys/dev/e1000/e1000_phy.c

1650

if (!phy->autoneg_advertised)

sys/dev/e1000/e1000_phy.c

1651

phy->autoneg_advertised = phy->autoneg_mask;

sys/dev/e1000/e1000_phy.c

1664

ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);

sys/dev/e1000/e1000_phy.c

1669

ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);

sys/dev/e1000/e1000_phy.c

1676

if (phy->autoneg_wait_to_complete) {

sys/dev/e1000/e1000_phy.c

1717

ret_val = hw->phy.ops.force_speed_duplex(hw);

sys/dev/e1000/e1000_phy.c

1753

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

1760

ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);

sys/dev/e1000/e1000_phy.c

1766

ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);

sys/dev/e1000/e1000_phy.c

1773

ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);

sys/dev/e1000/e1000_phy.c

1780

ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);

sys/dev/e1000/e1000_phy.c

1788

if (phy->autoneg_wait_to_complete) {

sys/dev/e1000/e1000_phy.c

1819

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

1827

if (phy->type != e1000_phy_i210) {

sys/dev/e1000/e1000_phy.c

1831

ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,

sys/dev/e1000/e1000_phy.c

1837

ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,

sys/dev/e1000/e1000_phy.c

1845

ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);

sys/dev/e1000/e1000_phy.c

1851

ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);

sys/dev/e1000/e1000_phy.c

1856

ret_val = hw->phy.ops.commit(hw);

sys/dev/e1000/e1000_phy.c

1860

if (phy->autoneg_wait_to_complete) {

sys/dev/e1000/e1000_phy.c

1871

switch (hw->phy.id) {

sys/dev/e1000/e1000_phy.c

1881

if (hw->phy.type != e1000_phy_m88)

sys/dev/e1000/e1000_phy.c

1892

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_phy.c

1910

if (hw->phy.type != e1000_phy_m88)

sys/dev/e1000/e1000_phy.c

1913

if (hw->phy.id == I347AT4_E_PHY_ID ||

sys/dev/e1000/e1000_phy.c

1914

hw->phy.id == M88E1340M_E_PHY_ID ||

sys/dev/e1000/e1000_phy.c

1915

hw->phy.id == M88E1112_E_PHY_ID)

sys/dev/e1000/e1000_phy.c

1917

if (hw->phy.id == I210_I_PHY_ID)

sys/dev/e1000/e1000_phy.c

1919

if ((hw->phy.id == M88E1543_E_PHY_ID) ||

sys/dev/e1000/e1000_phy.c

1920

(hw->phy.id == M88E1512_E_PHY_ID))

sys/dev/e1000/e1000_phy.c

1922

ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);

sys/dev/e1000/e1000_phy.c

1931

ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);

sys/dev/e1000/e1000_phy.c

1938

ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

sys/dev/e1000/e1000_phy.c

1943

ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

sys/dev/e1000/e1000_phy.c

1958

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

1965

ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);

sys/dev/e1000/e1000_phy.c

1971

ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);

sys/dev/e1000/e1000_phy.c

1976

ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);

sys/dev/e1000/e1000_phy.c

1983

ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);

sys/dev/e1000/e1000_phy.c

1991

if (phy->autoneg_wait_to_complete) {

sys/dev/e1000/e1000_phy.c

2089

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

2095

if (!hw->phy.ops.read_reg)

sys/dev/e1000/e1000_phy.c

2098

ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);

sys/dev/e1000/e1000_phy.c

2104

ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,

sys/dev/e1000/e1000_phy.c

2113

if (phy->smart_speed == e1000_smart_speed_on) {

sys/dev/e1000/e1000_phy.c

2114

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_phy.c

2121

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_phy.c

2126

} else if (phy->smart_speed == e1000_smart_speed_off) {

sys/dev/e1000/e1000_phy.c

2127

ret_val = phy->ops.read_reg(hw,

sys/dev/e1000/e1000_phy.c

2134

ret_val = phy->ops.write_reg(hw,

sys/dev/e1000/e1000_phy.c

2140

} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||

sys/dev/e1000/e1000_phy.c

2141

(phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||

sys/dev/e1000/e1000_phy.c

2142

(phy->autoneg_advertised == E1000_ALL_10_SPEED)) {

sys/dev/e1000/e1000_phy.c

2144

ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,

sys/dev/e1000/e1000_phy.c

2150

ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,

sys/dev/e1000/e1000_phy.c

2156

ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,

sys/dev/e1000/e1000_phy.c

2173

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

2179

switch (phy->type) {

sys/dev/e1000/e1000_phy.c

2196

phy->speed_downgraded = false;

sys/dev/e1000/e1000_phy.c

2200

ret_val = phy->ops.read_reg(hw, offset, &phy_data);

sys/dev/e1000/e1000_phy.c

2203

phy->speed_downgraded = !!(phy_data & mask);

sys/dev/e1000/e1000_phy.c

2218

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

2224

ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);

sys/dev/e1000/e1000_phy.c

2227

phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)

sys/dev/e1000/e1000_phy.c

2245

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

2254

ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);

sys/dev/e1000/e1000_phy.c

226

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

2270

ret_val = phy->ops.read_reg(hw, offset, &data);

sys/dev/e1000/e1000_phy.c

2273

phy->cable_polarity = ((data & mask)

sys/dev/e1000/e1000_phy.c

2288

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

2296

if (phy->polarity_correction) {

sys/dev/e1000/e1000_phy.c

2304

ret_val = phy->ops.read_reg(hw, offset, &phy_data);

sys/dev/e1000/e1000_phy.c

2307

phy->cable_polarity = ((phy_data & mask)

sys/dev/e1000/e1000_phy.c

2328

if (!hw->phy.ops.read_reg)

sys/dev/e1000/e1000_phy.c

233

if (!phy->ops.read_reg)

sys/dev/e1000/e1000_phy.c

2333

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);

sys/dev/e1000/e1000_phy.c

2336

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);

sys/dev/e1000/e1000_phy.c

2367

if (!hw->phy.ops.read_reg)

sys/dev/e1000/e1000_phy.c

237

ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);

sys/dev/e1000/e1000_phy.c

2375

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);

sys/dev/e1000/e1000_phy.c

2386

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);

sys/dev/e1000/e1000_phy.c

241

phy->id = (u32)(phy_id << 16);

sys/dev/e1000/e1000_phy.c

2419

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

2425

ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);

sys/dev/e1000/e1000_phy.c

243

ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);

sys/dev/e1000/e1000_phy.c

2435

phy->min_cable_length = e1000_m88_cable_length_table[index];

sys/dev/e1000/e1000_phy.c

2436

phy->max_cable_length = e1000_m88_cable_length_table[index + 1];

sys/dev/e1000/e1000_phy.c

2438

phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;

sys/dev/e1000/e1000_phy.c

2445

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

2452

switch (hw->phy.id) {

sys/dev/e1000/e1000_phy.c

2455

ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +

sys/dev/e1000/e1000_phy.c

2456

(I347AT4_PCDL + phy->addr),

sys/dev/e1000/e1000_phy.c

2462

ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +

sys/dev/e1000/e1000_phy.c

247

phy->id |= (u32)(phy_id & PHY_REVISION_MASK);

sys/dev/e1000/e1000_phy.c

2470

phy->min_cable_length = phy_data / (is_cm ? 100 : 1);

sys/dev/e1000/e1000_phy.c

2471

phy->max_cable_length = phy_data / (is_cm ? 100 : 1);

sys/dev/e1000/e1000_phy.c

2472

phy->cable_length = phy_data / (is_cm ? 100 : 1);

sys/dev/e1000/e1000_phy.c

2479

ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,

sys/dev/e1000/e1000_phy.c

248

phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

sys/dev/e1000/e1000_phy.c

2484

ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);

sys/dev/e1000/e1000_phy.c

2489

ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),

sys/dev/e1000/e1000_phy.c

2495

ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);

sys/dev/e1000/e1000_phy.c

250

if (phy->id != 0 && phy->id != PHY_REVISION_MASK)

sys/dev/e1000/e1000_phy.c

2502

phy->min_cable_length = phy_data / (is_cm ? 100 : 1);

sys/dev/e1000/e1000_phy.c

2503

phy->max_cable_length = phy_data / (is_cm ? 100 : 1);

sys/dev/e1000/e1000_phy.c

2504

phy->cable_length = phy_data / (is_cm ? 100 : 1);

sys/dev/e1000/e1000_phy.c

2507

ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,

sys/dev/e1000/e1000_phy.c

2515

ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,

sys/dev/e1000/e1000_phy.c

2520

ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);

sys/dev/e1000/e1000_phy.c

2524

ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,

sys/dev/e1000/e1000_phy.c

2535

phy->min_cable_length = e1000_m88_cable_length_table[index];

sys/dev/e1000/e1000_phy.c

2536

phy->max_cable_length = e1000_m88_cable_length_table[index + 1];

sys/dev/e1000/e1000_phy.c

2538

phy->cable_length = (phy->min_cable_length +

sys/dev/e1000/e1000_phy.c

2539

phy->max_cable_length) / 2;

sys/dev/e1000/e1000_phy.c

2542

ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,

sys/dev/e1000/e1000_phy.c

2568

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

2584

ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);

sys/dev/e1000/e1000_phy.c

2617

phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?

sys/dev/e1000/e1000_phy.c

2619

phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;

sys/dev/e1000/e1000_phy.c

2621

phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;

sys/dev/e1000/e1000_phy.c

2638

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

2645

if (phy->media_type != e1000_media_type_copper) {

sys/dev/e1000/e1000_phy.c

2659

ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

sys/dev/e1000/e1000_phy.c

2663

phy->polarity_correction = !!(phy_data &

sys/dev/e1000/e1000_phy.c

2670

ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);

sys/dev/e1000/e1000_phy.c

2674

phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);

sys/dev/e1000/e1000_phy.c

2677

ret_val = hw->phy.ops.get_cable_length(hw);

sys/dev/e1000/e1000_phy.c

2681

ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);

sys/dev/e1000/e1000_phy.c

2685

phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)

sys/dev/e1000/e1000_phy.c

2689

phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)

sys/dev/e1000/e1000_phy.c

2694

phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;

sys/dev/e1000/e1000_phy.c

2695

phy->local_rx = e1000_1000t_rx_status_undefined;

sys/dev/e1000/e1000_phy.c

2696

phy->remote_rx = e1000_1000t_rx_status_undefined;

sys/dev/e1000/e1000_phy.c

271

if (!hw->phy.ops.write_reg)

sys/dev/e1000/e1000_phy.c

2713

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

2729

phy->polarity_correction = true;

sys/dev/e1000/e1000_phy.c

2735

ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);

sys/dev/e1000/e1000_phy.c

2739

phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);

sys/dev/e1000/e1000_phy.c

274

ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);

sys/dev/e1000/e1000_phy.c

2743

ret_val = phy->ops.get_cable_length(hw);

sys/dev/e1000/e1000_phy.c

2747

ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);

sys/dev/e1000/e1000_phy.c

2751

phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)

sys/dev/e1000/e1000_phy.c

2755

phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)

sys/dev/e1000/e1000_phy.c

2759

phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;

sys/dev/e1000/e1000_phy.c

2760

phy->local_rx = e1000_1000t_rx_status_undefined;

sys/dev/e1000/e1000_phy.c

2761

phy->remote_rx = e1000_1000t_rx_status_undefined;

sys/dev/e1000/e1000_phy.c

2775

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

278

return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);

sys/dev/e1000/e1000_phy.c

2791

ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);

sys/dev/e1000/e1000_phy.c

2794

phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);

sys/dev/e1000/e1000_phy.c

2796

if (phy->polarity_correction) {

sys/dev/e1000/e1000_phy.c

2802

phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)

sys/dev/e1000/e1000_phy.c

2807

ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);

sys/dev/e1000/e1000_phy.c

2811

phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);

sys/dev/e1000/e1000_phy.c

2814

phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;

sys/dev/e1000/e1000_phy.c

2815

phy->local_rx = e1000_1000t_rx_status_undefined;

sys/dev/e1000/e1000_phy.c

2816

phy->remote_rx = e1000_1000t_rx_status_undefined;

sys/dev/e1000/e1000_phy.c

2835

if (!hw->phy.ops.read_reg)

sys/dev/e1000/e1000_phy.c

2838

ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);

sys/dev/e1000/e1000_phy.c

2843

ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);

sys/dev/e1000/e1000_phy.c

2863

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

2869

if (phy->ops.check_reset_block) {

sys/dev/e1000/e1000_phy.c

2870

ret_val = phy->ops.check_reset_block(hw);

sys/dev/e1000/e1000_phy.c

2875

ret_val = phy->ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

2883

usec_delay(phy->reset_delay_us);

sys/dev/e1000/e1000_phy.c

2890

phy->ops.release(hw);

sys/dev/e1000/e1000_phy.c

2892

return phy->ops.get_cfg_done(hw);

sys/dev/e1000/e1000_phy.c

292

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

2923

hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);

sys/dev/e1000/e1000_phy.c

2925

hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);

sys/dev/e1000/e1000_phy.c

2927

hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);

sys/dev/e1000/e1000_phy.c

2929

hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);

sys/dev/e1000/e1000_phy.c

2931

hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);

sys/dev/e1000/e1000_phy.c

2933

hw->phy.ops.write_reg(hw, 0x2011, 0x0000);

sys/dev/e1000/e1000_phy.c

2935

hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);

sys/dev/e1000/e1000_phy.c

2937

hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);

sys/dev/e1000/e1000_phy.c

2939

hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);

sys/dev/e1000/e1000_phy.c

2941

hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);

sys/dev/e1000/e1000_phy.c

2943

hw->phy.ops.write_reg(hw, 0x0000, 0x0140);

sys/dev/e1000/e1000_phy.c

2945

hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);

sys/dev/e1000/e1000_phy.c

2947

hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);

sys/dev/e1000/e1000_phy.c

2949

hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);

sys/dev/e1000/e1000_phy.c

2951

hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);

sys/dev/e1000/e1000_phy.c

2953

hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);

sys/dev/e1000/e1000_phy.c

2955

hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);

sys/dev/e1000/e1000_phy.c

2957

hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);

sys/dev/e1000/e1000_phy.c

2959

hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);

sys/dev/e1000/e1000_phy.c

2961

hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);

sys/dev/e1000/e1000_phy.c

2963

hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);

sys/dev/e1000/e1000_phy.c

2965

hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);

sys/dev/e1000/e1000_phy.c

2967

hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);

sys/dev/e1000/e1000_phy.c

2969

hw->phy.ops.write_reg(hw, 0x1895, 0x0003);

sys/dev/e1000/e1000_phy.c

2971

hw->phy.ops.write_reg(hw, 0x1796, 0x0008);

sys/dev/e1000/e1000_phy.c

2973

hw->phy.ops.write_reg(hw, 0x1798, 0xD008);

sys/dev/e1000/e1000_phy.c

2977

hw->phy.ops.write_reg(hw, 0x1898, 0xD918);

sys/dev/e1000/e1000_phy.c

2979

hw->phy.ops.write_reg(hw, 0x187A, 0x0800);

sys/dev/e1000/e1000_phy.c

2983

hw->phy.ops.write_reg(hw, 0x0019, 0x008D);

sys/dev/e1000/e1000_phy.c

2985

hw->phy.ops.write_reg(hw, 0x001B, 0x2080);

sys/dev/e1000/e1000_phy.c

2987

hw->phy.ops.write_reg(hw, 0x0014, 0x0045);

sys/dev/e1000/e1000_phy.c

2989

hw->phy.ops.write_reg(hw, 0x0000, 0x1340);

sys/dev/e1000/e1000_phy.c

307

(phy->addr << E1000_MDIC_PHY_SHIFT) |

sys/dev/e1000/e1000_phy.c

3073

hw->phy.id = phy_type;

sys/dev/e1000/e1000_phy.c

3076

hw->phy.addr = phy_addr;

sys/dev/e1000/e1000_phy.c

3081

phy_type = e1000_get_phy_type_from_id(hw->phy.id);

sys/dev/e1000/e1000_phy.c

3130

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

3141

hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);

sys/dev/e1000/e1000_phy.c

3150

if (hw->phy.addr == 1) {

sys/dev/e1000/e1000_phy.c

3169

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_phy.c

3190

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

3201

hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);

sys/dev/e1000/e1000_phy.c

3210

if (hw->phy.addr == 1) {

sys/dev/e1000/e1000_phy.c

3228

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_phy.c

3249

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

3260

hw->phy.addr = 1;

sys/dev/e1000/e1000_phy.c

3274

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_phy.c

3294

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

3305

hw->phy.addr = 1;

sys/dev/e1000/e1000_phy.c

3320

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_phy.c

3343

hw->phy.addr = 1;

sys/dev/e1000/e1000_phy.c

3508

hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);

sys/dev/e1000/e1000_phy.c

3510

hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);

sys/dev/e1000/e1000_phy.c

3526

hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);

sys/dev/e1000/e1000_phy.c

3528

hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);

sys/dev/e1000/e1000_phy.c

3550

u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);

sys/dev/e1000/e1000_phy.c

3555

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

357

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

3581

hw->phy.addr = phy_addr;

sys/dev/e1000/e1000_phy.c

3595

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_phy.c

3660

u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);

sys/dev/e1000/e1000_phy.c

3665

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

3689

if ((hw->phy.type == e1000_phy_82578) &&

sys/dev/e1000/e1000_phy.c

3690

(hw->phy.revision >= 1) &&

sys/dev/e1000/e1000_phy.c

3691

(hw->phy.addr == 2) &&

sys/dev/e1000/e1000_phy.c

3707

hw->phy.addr = phy_addr;

sys/dev/e1000/e1000_phy.c

3722

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_phy.c

373

(phy->addr << E1000_MDIC_PHY_SHIFT) |

sys/dev/e1000/e1000_phy.c

3805

addr_reg = ((hw->phy.type == e1000_phy_82578) ?

sys/dev/e1000/e1000_phy.c

3810

hw->phy.addr = 2;

sys/dev/e1000/e1000_phy.c

3849

if (hw->phy.type != e1000_phy_82578)

sys/dev/e1000/e1000_phy.c

3853

hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);

sys/dev/e1000/e1000_phy.c

3858

ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);

sys/dev/e1000/e1000_phy.c

3872

ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,

sys/dev/e1000/e1000_phy.c

3878

return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,

sys/dev/e1000/e1000_phy.c

3892

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

3898

ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);

sys/dev/e1000/e1000_phy.c

3901

phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)

sys/dev/e1000/e1000_phy.c

3916

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

3923

ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);

sys/dev/e1000/e1000_phy.c

3929

ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);

sys/dev/e1000/e1000_phy.c

3935

if (phy->autoneg_wait_to_complete) {

sys/dev/e1000/e1000_phy.c

3965

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

3981

phy->polarity_correction = true;

sys/dev/e1000/e1000_phy.c

3987

ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);

sys/dev/e1000/e1000_phy.c

3991

phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);

sys/dev/e1000/e1000_phy.c

3995

ret_val = hw->phy.ops.get_cable_length(hw);

sys/dev/e1000/e1000_phy.c

3999

ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);

sys/dev/e1000/e1000_phy.c

4003

phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)

sys/dev/e1000/e1000_phy.c

4007

phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)

sys/dev/e1000/e1000_phy.c

4011

phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;

sys/dev/e1000/e1000_phy.c

4012

phy->local_rx = e1000_1000t_rx_status_undefined;

sys/dev/e1000/e1000_phy.c

4013

phy->remote_rx = e1000_1000t_rx_status_undefined;

sys/dev/e1000/e1000_phy.c

4028

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

4034

ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);

sys/dev/e1000/e1000_phy.c

4044

phy->cable_length = length;

sys/dev/e1000/e1000_phy.c

4066

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

4076

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_phy.c

4098

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

4108

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_phy.c

423

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

4282

ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);

sys/dev/e1000/e1000_phy.c

4286

ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);

sys/dev/e1000/e1000_phy.c

4290

ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |

sys/dev/e1000/e1000_phy.c

4296

ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);

sys/dev/e1000/e1000_phy.c

4298

ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);

sys/dev/e1000/e1000_phy.c

4303

ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);

sys/dev/e1000/e1000_phy.c

433

(phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |

sys/dev/e1000/e1000_phy.c

470

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

477

if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {

sys/dev/e1000/e1000_phy.c

479

hw->phy.addr);

sys/dev/e1000/e1000_phy.c

491

(phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |

sys/dev/e1000/e1000_phy.c

660

if (!hw->phy.ops.acquire)

sys/dev/e1000/e1000_phy.c

663

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

670

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_phy.c

690

if (!hw->phy.ops.acquire)

sys/dev/e1000/e1000_phy.c

693

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

700

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_phy.c

72

struct e1000_phy_info *phy = &hw->phy;

sys/dev/e1000/e1000_phy.c

720

hw->phy.addr = 1;

sys/dev/e1000/e1000_phy.c

744

if (!hw->phy.ops.acquire)

sys/dev/e1000/e1000_phy.c

747

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

76

phy->ops.init_params = e1000_null_ops_generic;

sys/dev/e1000/e1000_phy.c

761

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_phy.c

77

phy->ops.acquire = e1000_null_ops_generic;

sys/dev/e1000/e1000_phy.c

78

phy->ops.check_polarity = e1000_null_ops_generic;

sys/dev/e1000/e1000_phy.c

79

phy->ops.check_reset_block = e1000_null_ops_generic;

sys/dev/e1000/e1000_phy.c

80

phy->ops.commit = e1000_null_ops_generic;

sys/dev/e1000/e1000_phy.c

81

phy->ops.force_speed_duplex = e1000_null_ops_generic;

sys/dev/e1000/e1000_phy.c

813

if (!hw->phy.ops.acquire)

sys/dev/e1000/e1000_phy.c

816

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

82

phy->ops.get_cfg_done = e1000_null_ops_generic;

sys/dev/e1000/e1000_phy.c

83

phy->ops.get_cable_length = e1000_null_ops_generic;

sys/dev/e1000/e1000_phy.c

830

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_phy.c

84

phy->ops.get_info = e1000_null_ops_generic;

sys/dev/e1000/e1000_phy.c

85

phy->ops.set_page = e1000_null_set_page;

sys/dev/e1000/e1000_phy.c

86

phy->ops.read_reg = e1000_null_read_reg;

sys/dev/e1000/e1000_phy.c

87

phy->ops.read_reg_locked = e1000_null_read_reg;

sys/dev/e1000/e1000_phy.c

88

phy->ops.read_reg_page = e1000_null_read_reg;

sys/dev/e1000/e1000_phy.c

884

if (!hw->phy.ops.acquire)

sys/dev/e1000/e1000_phy.c

887

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

89

phy->ops.release = e1000_null_phy_generic;

sys/dev/e1000/e1000_phy.c

90

phy->ops.reset = e1000_null_ops_generic;

sys/dev/e1000/e1000_phy.c

903

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_phy.c

91

phy->ops.set_d0_lplu_state = e1000_null_lplu_state;

sys/dev/e1000/e1000_phy.c

92

phy->ops.set_d3_lplu_state = e1000_null_lplu_state;

sys/dev/e1000/e1000_phy.c

93

phy->ops.write_reg = e1000_null_write_reg;

sys/dev/e1000/e1000_phy.c

94

phy->ops.write_reg_locked = e1000_null_write_reg;

sys/dev/e1000/e1000_phy.c

95

phy->ops.write_reg_page = e1000_null_write_reg;

sys/dev/e1000/e1000_phy.c

959

if (!hw->phy.ops.acquire)

sys/dev/e1000/e1000_phy.c

96

phy->ops.power_up = e1000_null_phy_generic;

sys/dev/e1000/e1000_phy.c

962

ret_val = hw->phy.ops.acquire(hw);

sys/dev/e1000/e1000_phy.c

97

phy->ops.power_down = e1000_null_phy_generic;

sys/dev/e1000/e1000_phy.c

975

hw->phy.ops.release(hw);

sys/dev/e1000/e1000_phy.c

98

phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;

sys/dev/e1000/e1000_phy.c

99

phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;

sys/dev/e1000/e1000_vf.c

103

hw->phy.media_type = e1000_media_type_unknown;

sys/dev/e1000/e1000_vf.c

150

hw->phy.ops.init_params = e1000_init_phy_params_vf;

sys/dev/e1000/e1000_vf.c

64

hw->phy.type = e1000_phy_vf;

sys/dev/e1000/e1000_vf.c

65

hw->phy.ops.acquire = e1000_acquire_vf;

sys/dev/e1000/e1000_vf.c

66

hw->phy.ops.release = e1000_release_vf;

sys/dev/e1000/if_em.c

1470

hw->phy.autoneg_wait_to_complete = false;

sys/dev/e1000/if_em.c

1471

hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;

sys/dev/e1000/if_em.c

1478

if (hw->phy.media_type == e1000_media_type_copper) {

sys/dev/e1000/if_em.c

1479

hw->phy.mdix = AUTO_ALL_MODES;

sys/dev/e1000/if_em.c

1480

hw->phy.disable_polarity_correction = false;

sys/dev/e1000/if_em.c

1481

hw->phy.ms_type = EM_MASTER_SLAVE;

sys/dev/e1000/if_em.c

1941

sc->hw.phy.media_type == e1000_media_type_copper) {

sys/dev/e1000/if_em.c

2348

if ((sc->hw.phy.media_type == e1000_media_type_fiber) ||

sys/dev/e1000/if_em.c

2349

(sc->hw.phy.media_type == e1000_media_type_internal_serdes)) {

sys/dev/e1000/if_em.c

2394

sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;

sys/dev/e1000/if_em.c

2400

sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;

sys/dev/e1000/if_em.c

2404

sc->hw.phy.autoneg_advertised = 0;

sys/dev/e1000/if_em.c

2412

sc->hw.phy.autoneg_advertised = 0;

sys/dev/e1000/if_em.c

2645

switch (hw->phy.media_type) {

sys/dev/e1000/if_em.c

2712

(hw->phy.id == I210_I_PHY_ID))

sys/dev/e1000/if_em.c

3260

(sc->hw.phy.type != e1000_phy_igp) ||

sys/dev/e1000/if_em.c

3262

(sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)

sys/dev/e1000/if_em.c

3979

if (sc->hw.phy.media_type == e1000_media_type_fiber ||

sys/dev/e1000/if_em.c

3980

sc->hw.phy.media_type == e1000_media_type_internal_serdes) {

sys/dev/e1000/if_em.c

3995

if (sc->hw.phy.type != e1000_phy_ife) {

sys/dev/e1000/if_em.c

4228

if (hw->phy.media_type == e1000_media_type_fiber ||

sys/dev/e1000/if_em.c

4229

hw->phy.media_type == e1000_media_type_internal_serdes)

sys/dev/e1000/if_em.c

5205

if (sc->hw.phy.media_type == e1000_media_type_fiber ||

sys/dev/e1000/if_em.c

5206

sc->hw.phy.media_type == e1000_media_type_internal_serdes) {

sys/dev/e1000/if_em.c

5228

if (sc->hw.phy.type == e1000_phy_igp_3)

sys/dev/e1000/if_em.c

5290

ret = hw->phy.ops.acquire(hw);

sys/dev/e1000/if_em.c

5307

hw->phy.ops.release(hw);

sys/dev/e1000/if_em.c

5376

if(sc->hw.phy.media_type == e1000_media_type_copper ||

sys/dev/enetc/enetc_mdio.c

111

enetc_mdio_write(struct resource *regs, int mdio_base, int phy, int reg,

sys/dev/enetc/enetc_mdio.c

134

mdio_ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(dev_addr);

sys/dev/enetc/enetc_mdio.c

64

enetc_mdio_read(struct resource *regs, int mdio_base, int phy, int reg)

sys/dev/enetc/enetc_mdio.c

86

mdio_ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(dev_addr);

sys/dev/enetc/if_enetc.c

1426

enetc_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/enetc/if_enetc.c

1435

phy, reg);

sys/dev/enetc/if_enetc.c

1442

enetc_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/enetc/if_enetc.c

1451

phy, reg, data);

sys/dev/eqos/if_eqos.c

111

eqos_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/eqos/if_eqos.c

118

(phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) |

sys/dev/eqos/if_eqos.c

136

phy, reg);

sys/dev/eqos/if_eqos.c

143

eqos_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/eqos/if_eqos.c

152

(phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) |

sys/dev/eqos/if_eqos.c

168

phy, reg);

sys/dev/et/if_et.c

409

et_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/et/if_et.c

419

val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK;

sys/dev/et/if_et.c

436

"read phy %d, reg %d timed out\n", phy, reg);

sys/dev/et/if_et.c

453

et_miibus_writereg(device_t dev, int phy, int reg, int val0)

sys/dev/et/if_et.c

463

val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK;

sys/dev/et/if_et.c

481

"write phy %d, reg %d timed out\n", phy, reg);

sys/dev/et/if_et.c

482

et_miibus_readreg(dev, phy, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mdio.c

74

ar40xx_hw_phy_dbg_write(struct ar40xx_softc *sc, int phy, uint16_t dbg,

sys/dev/etherswitch/ar40xx/ar40xx_hw_mdio.c

83

ar40xx_hw_phy_dbg_read(struct ar40xx_softc *sc, int phy, uint16_t dbg)

sys/dev/etherswitch/ar40xx/ar40xx_hw_mdio.h

30

extern int ar40xx_hw_phy_dbg_write(struct ar40xx_softc *sc, int phy,

sys/dev/etherswitch/ar40xx/ar40xx_hw_mdio.h

32

extern int ar40xx_hw_phy_dbg_read(struct ar40xx_softc *sc, int phy,

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

121

ar40xx_hw_psgmii_single_phy_testing(struct ar40xx_softc *sc, int phy)

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

130

MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x9000);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

131

MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x4140);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

136

status = MDIO_READREG(sc->sc_mdio_dev, phy, 0x11);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

151

ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8029, 0x0000);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

152

ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8029, 0x0003);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

155

ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8020, 0xa000);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

163

tx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802e);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

164

tx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802d);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

165

tx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802f);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

166

rx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802b);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

167

rx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802a);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

168

rx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802c);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

174

sc->sc_psgmii.phy_t_status &= ~(1U << phy);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

180

"PHY %d single test PSGMII issue happen!\n", phy);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

181

sc->sc_psgmii.phy_t_status |= BIT(phy);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

184

MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x1840);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

191

int phy, j;

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

197

for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

200

status = MDIO_READREG(sc->sc_mdio_dev, phy, 0x11);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

205

if (phy >= (AR40XX_NUM_PORTS - 1))

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

223

for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

231

tx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802e);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

232

tx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802d);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

233

tx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802f);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

234

rx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802b);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

235

rx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802a);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

236

rx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802c);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

242

sc->sc_psgmii.phy_t_status &= ~(1U << (phy + 8));

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

247

phy, tx_all_ok, rx_all_ok, tx_error, rx_error);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

248

sc->sc_psgmii.phy_t_status |= (1U << (phy + 8));

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

322

uint32_t i, phy, reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

330

for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

332

ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8028, 0x801f);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

347

for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

351

AR40XX_REG_PORT_LOOKUP(phy + 1));

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

354

AR40XX_REG_PORT_LOOKUP(phy + 1), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

358

for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++)

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

359

ar40xx_hw_psgmii_single_phy_testing(sc, phy);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

390

int phy;

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

398

for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

400

reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_LOOKUP(phy + 1));

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

402

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(phy + 1), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

406

ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8028, 0x001f);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.h

35

int phy);

sys/dev/etherswitch/ar40xx/ar40xx_main.c

115

ar40xx_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/ar40xx/ar40xx_main.c

119

return MDIO_READREG(sc->sc_mdio_dev, phy, reg);

sys/dev/etherswitch/ar40xx/ar40xx_main.c

123

ar40xx_writephy(device_t dev, int phy, int reg, int val)

sys/dev/etherswitch/ar40xx/ar40xx_main.c

127

return MDIO_WRITEREG(sc->sc_mdio_dev, phy, reg, val);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

106

"%s: PHY %d: down -> up\n", __func__, phy);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

107

ar40xx_hw_port_link_up(sc, phy + 1);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

108

ar40xx_hw_atu_flush_port(sc, phy + 1);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

113

"%s: PHY %d: up -> down\n", __func__, phy);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

114

ar40xx_hw_port_link_down(sc, phy + 1);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

115

ar40xx_hw_atu_flush_port(sc, phy + 1);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

132

ar40xx_portforphy(int phy)

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

135

return (phy+1);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

141

int phy;

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

143

phy = port-1;

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

145

if (phy < 0 || phy >= AR40XX_NUM_PHYS)

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

147

return (device_get_softc(sc->sc_phys.miibus[phy]));

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

153

int phy;

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

155

phy = port-1;

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

156

if (phy < 0 || phy >= AR40XX_NUM_PHYS)

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

158

return (sc->sc_phys.ifp[phy]);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

196

int phy, err = 0;

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

201

for (phy = 0; phy < AR40XX_NUM_PHYS; phy++) {

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

202

sc->sc_phys.ifp[phy] = if_alloc(IFT_ETHER);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

203

if_setsoftc(sc->sc_phys.ifp[phy], sc);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

204

if_setflagbits(sc->sc_phys.ifp[phy], IFF_UP | IFF_BROADCAST |

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

206

sc->sc_phys.ifname[phy] = malloc(strlen(name)+1, M_DEVBUF,

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

208

bcopy(name, sc->sc_phys.ifname[phy], strlen(name)+1);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

209

if_initname(sc->sc_phys.ifp[phy], sc->sc_phys.ifname[phy],

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

210

ar40xx_portforphy(phy));

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

211

err = mii_attach(sc->sc_dev, &sc->sc_phys.miibus[phy],

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

212

sc->sc_phys.ifp[phy], ar40xx_ifmedia_upd,

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

214

phy, MII_OFFSET_ANY, 0);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

217

device_get_nameunit(sc->sc_phys.miibus[phy]),

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

218

if_name(sc->sc_phys.ifp[phy]));

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

222

phy);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

232

int phy;

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

235

for (phy = 0; phy < AR40XX_NUM_PHYS; phy++) {

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

236

id1 = MDIO_READREG(sc->sc_mdio_dev, phy, 2);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

237

id2 = MDIO_READREG(sc->sc_mdio_dev, phy, 3);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

240

__func__, phy, id1, id2);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

82

int phy;

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

91

for (phy = 0; phy < AR40XX_NUM_PHYS; phy++) {

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

95

reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(phy + 1));

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

97

mii = device_get_softc(sc->sc_phys.miibus[phy]);

sys/dev/etherswitch/arswitch/arswitch.c

1053

arswitch_setled(struct arswitch_softc *sc, int phy, int led, int style)

sys/dev/etherswitch/arswitch/arswitch.c

1058

if (phy < 0 || phy > sc->numphys)

sys/dev/etherswitch/arswitch/arswitch.c

1066

shift = ar8327_led_mapping[phy][led].shift;

sys/dev/etherswitch/arswitch/arswitch.c

1068

ar8327_led_mapping[phy][led].reg,

sys/dev/etherswitch/arswitch/arswitch.c

1249

arswitch_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/arswitch/arswitch.c

1253

return (sc->hal.arswitch_phy_read(dev, phy, reg));

sys/dev/etherswitch/arswitch/arswitch.c

1257

arswitch_writephy(device_t dev, int phy, int reg, int val)

sys/dev/etherswitch/arswitch/arswitch.c

1261

return (sc->hal.arswitch_phy_write(dev, phy, reg, val));

sys/dev/etherswitch/arswitch/arswitch.c

146

int phy, err = 0;

sys/dev/etherswitch/arswitch/arswitch.c

151

for (phy = 0; phy < sc->numphys; phy++) {

sys/dev/etherswitch/arswitch/arswitch.c

152

sc->ifp[phy] = if_alloc(IFT_ETHER);

sys/dev/etherswitch/arswitch/arswitch.c

153

if_setsoftc(sc->ifp[phy], sc);

sys/dev/etherswitch/arswitch/arswitch.c

154

if_setflagbits(sc->ifp[phy], IFF_UP | IFF_BROADCAST |

sys/dev/etherswitch/arswitch/arswitch.c

156

sc->ifname[phy] = malloc(strlen(name)+1, M_DEVBUF, M_WAITOK);

sys/dev/etherswitch/arswitch/arswitch.c

157

bcopy(name, sc->ifname[phy], strlen(name)+1);

sys/dev/etherswitch/arswitch/arswitch.c

158

if_initname(sc->ifp[phy], sc->ifname[phy],

sys/dev/etherswitch/arswitch/arswitch.c

159

arswitch_portforphy(phy));

sys/dev/etherswitch/arswitch/arswitch.c

160

err = mii_attach(sc->sc_dev, &sc->miibus[phy], sc->ifp[phy],

sys/dev/etherswitch/arswitch/arswitch.c

162

BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);

sys/dev/etherswitch/arswitch/arswitch.c

165

device_get_nameunit(sc->miibus[phy]),

sys/dev/etherswitch/arswitch/arswitch.c

166

if_name(sc->ifp[phy]));

sys/dev/etherswitch/arswitch/arswitch.c

171

phy);

sys/dev/etherswitch/arswitch/arswitch.c

181

arswitch_portforphy(phy), led+1);

sys/dev/etherswitch/arswitch/arswitch.c

182

sc->dev_led[phy][led].sc = sc;

sys/dev/etherswitch/arswitch/arswitch.c

183

sc->dev_led[phy][led].phy = phy;

sys/dev/etherswitch/arswitch/arswitch.c

184

sc->dev_led[phy][led].lednum = led;

sys/dev/etherswitch/arswitch/arswitch.c

695

arswitch_portforphy(int phy)

sys/dev/etherswitch/arswitch/arswitch.c

697

return (phy+1);

sys/dev/etherswitch/arswitch/arswitch.c

703

int phy = port-1;

sys/dev/etherswitch/arswitch/arswitch.c

705

if (phy < 0 || phy >= sc->numphys)

sys/dev/etherswitch/arswitch/arswitch.c

707

return (device_get_softc(sc->miibus[phy]));

sys/dev/etherswitch/arswitch/arswitch.c

713

int phy = port-1;

sys/dev/etherswitch/arswitch/arswitch.c

715

if (phy < 0 || phy >= sc->numphys)

sys/dev/etherswitch/arswitch/arswitch.c

717

return (sc->ifp[phy]);

sys/dev/etherswitch/arswitch/arswitch.c

82

static inline int arswitch_portforphy(int phy);

sys/dev/etherswitch/arswitch/arswitch.c

90

static int arswitch_setled(struct arswitch_softc *sc, int phy, int led,

sys/dev/etherswitch/arswitch/arswitch_8327.c

153

ar8327_phy_fixup(struct arswitch_softc *sc, int phy)

sys/dev/etherswitch/arswitch/arswitch_8327.c

158

phy,

sys/dev/etherswitch/arswitch/arswitch_8327.c

163

arswitch_writedbg(sc->sc_dev, phy, 0, 0x02ea);

sys/dev/etherswitch/arswitch/arswitch_8327.c

165

arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x68a0);

sys/dev/etherswitch/arswitch/arswitch_8327.c

169

arswitch_writemmd(sc->sc_dev, phy, 0x7, 0x3c);

sys/dev/etherswitch/arswitch/arswitch_8327.c

170

arswitch_writemmd(sc->sc_dev, phy, 0x4007, 0x0);

sys/dev/etherswitch/arswitch/arswitch_8327.c

173

arswitch_writemmd(sc->sc_dev, phy, 0x3, 0x800d);

sys/dev/etherswitch/arswitch/arswitch_8327.c

174

arswitch_writemmd(sc->sc_dev, phy, 0x4003, 0x803f);

sys/dev/etherswitch/arswitch/arswitch_8327.c

176

arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x6860);

sys/dev/etherswitch/arswitch/arswitch_8327.c

177

arswitch_writedbg(sc->sc_dev, phy, 0x5, 0x2c46);

sys/dev/etherswitch/arswitch/arswitch_8327.c

178

arswitch_writedbg(sc->sc_dev, phy, 0x3c, 0x6000);

sys/dev/etherswitch/arswitch/arswitch_phy.c

100

__func__, phy, reg, data);

sys/dev/etherswitch/arswitch/arswitch_phy.c

111

arswitch_readphy_internal(device_t dev, int phy, int reg)

sys/dev/etherswitch/arswitch/arswitch_phy.c

121

if (phy < 0 || phy >= 32)

sys/dev/etherswitch/arswitch/arswitch_phy.c

135

(phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |

sys/dev/etherswitch/arswitch/arswitch_phy.c

137

DEVERR(dev, err, "arswitch_readphy()=%d: phy=%d.%02x\n", phy, reg);

sys/dev/etherswitch/arswitch/arswitch_phy.c

148

phy, reg, timeout);

sys/dev/etherswitch/arswitch/arswitch_phy.c

157

__func__, phy, reg, data);

sys/dev/etherswitch/arswitch/arswitch_phy.c

166

__func__, phy, reg, err);

sys/dev/etherswitch/arswitch/arswitch_phy.c

172

arswitch_writephy_internal(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/arswitch/arswitch_phy.c

195

(phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |

sys/dev/etherswitch/arswitch/arswitch_phy.c

210

__func__, phy, reg, data, err);

sys/dev/etherswitch/arswitch/arswitch_phy.c

213

DEVERR(dev, err, "arswitch_writephy()=%d: phy=%d.%02x\n", phy, reg);

sys/dev/etherswitch/arswitch/arswitch_phy.c

71

arswitch_readphy_external(device_t dev, int phy, int reg)

sys/dev/etherswitch/arswitch/arswitch_phy.c

79

ret = (MDIO_READREG(device_get_parent(dev), phy, reg));

sys/dev/etherswitch/arswitch/arswitch_phy.c

82

__func__, phy, reg, ret);

sys/dev/etherswitch/arswitch/arswitch_phy.c

89

arswitch_writephy_external(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/arswitch/arswitch_phy.c

96

(void) MDIO_WRITEREG(device_get_parent(dev), phy,

sys/dev/etherswitch/arswitch/arswitch_phy.h

31

extern int arswitch_readphy_external(device_t dev, int phy, int reg);

sys/dev/etherswitch/arswitch/arswitch_phy.h

32

extern int arswitch_writephy_external(device_t dev, int phy, int reg, int data);

sys/dev/etherswitch/arswitch/arswitch_phy.h

34

extern int arswitch_readphy_internal(device_t dev, int phy, int reg);

sys/dev/etherswitch/arswitch/arswitch_phy.h

35

extern int arswitch_writephy_internal(device_t dev, int phy, int reg, int data);

sys/dev/etherswitch/arswitch/arswitch_reg.c

102

uint16_t phy, reg;

sys/dev/etherswitch/arswitch/arswitch_reg.c

104

arswitch_split_setpage(dev, addr, &phy, &reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

105

return (MDIO_WRITEREG(device_get_parent(dev), 0x10 | phy, reg, data));

sys/dev/etherswitch/arswitch/arswitch_reg.c

109

arswitch_writedbg(device_t dev, int phy, uint16_t dbg_addr,

sys/dev/etherswitch/arswitch/arswitch_reg.c

112

(void) MDIO_WRITEREG(device_get_parent(dev), phy,

sys/dev/etherswitch/arswitch/arswitch_reg.c

114

(void) MDIO_WRITEREG(device_get_parent(dev), phy,

sys/dev/etherswitch/arswitch/arswitch_reg.c

119

arswitch_writemmd(device_t dev, int phy, uint16_t dbg_addr,

sys/dev/etherswitch/arswitch/arswitch_reg.c

122

(void) MDIO_WRITEREG(device_get_parent(dev), phy,

sys/dev/etherswitch/arswitch/arswitch_reg.c

124

(void) MDIO_WRITEREG(device_get_parent(dev), phy,

sys/dev/etherswitch/arswitch/arswitch_reg.c

129

arswitch_reg_read32(device_t dev, int phy, int reg)

sys/dev/etherswitch/arswitch/arswitch_reg.c

132

lo = MDIO_READREG(device_get_parent(dev), phy, reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

133

hi = MDIO_READREG(device_get_parent(dev), phy, reg + 1);

sys/dev/etherswitch/arswitch/arswitch_reg.c

139

arswitch_reg_write32(device_t dev, int phy, int reg, uint32_t value)

sys/dev/etherswitch/arswitch/arswitch_reg.c

151

phy, reg, lo);

sys/dev/etherswitch/arswitch/arswitch_reg.c

153

phy, reg + 1, hi);

sys/dev/etherswitch/arswitch/arswitch_reg.c

156

phy, reg + 1, hi);

sys/dev/etherswitch/arswitch/arswitch_reg.c

158

phy, reg, lo);

sys/dev/etherswitch/arswitch/arswitch_reg.c

167

uint16_t phy, reg;

sys/dev/etherswitch/arswitch/arswitch_reg.c

169

arswitch_split_setpage(dev, addr, &phy, &reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

170

return arswitch_reg_read32(dev, 0x10 | phy, reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

176

uint16_t phy, reg;

sys/dev/etherswitch/arswitch/arswitch_reg.c

178

arswitch_split_setpage(dev, addr, &phy, &reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

179

return (arswitch_reg_write32(dev, 0x10 | phy, reg, value));

sys/dev/etherswitch/arswitch/arswitch_reg.c

221

uint16_t phy, reg;

sys/dev/etherswitch/arswitch/arswitch_reg.c

226

arswitch_split_setpage(dev, addr, &phy, &reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

228

value = arswitch_reg_read32(dev, 0x10 | phy, reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

231

return (arswitch_reg_write32(dev, 0x10 | phy, reg, value));

sys/dev/etherswitch/arswitch/arswitch_reg.c

239

uint16_t phy, reg;

sys/dev/etherswitch/arswitch/arswitch_reg.c

243

arswitch_split_setpage(dev, addr, &phy, &reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

247

v = arswitch_reg_read32(dev, 0x10 | phy, reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

65

arswitch_split_setpage(device_t dev, uint32_t addr, uint16_t *phy,

sys/dev/etherswitch/arswitch/arswitch_reg.c

72

*phy = (addr >> 6) & 0x7;

sys/dev/etherswitch/arswitch/arswitch_reg.c

90

uint16_t phy, reg;

sys/dev/etherswitch/arswitch/arswitch_reg.c

92

arswitch_split_setpage(dev, addr, &phy, &reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

93

return (MDIO_READREG(device_get_parent(dev), 0x10 | phy, reg));

sys/dev/etherswitch/arswitch/arswitch_reg.h

31

extern void arswitch_writedbg(device_t dev, int phy, uint16_t dbg_addr,

sys/dev/etherswitch/arswitch/arswitch_reg.h

33

extern void arswitch_writemmd(device_t dev, int phy, uint16_t dbg_addr,

sys/dev/etherswitch/arswitch/arswitchvar.h

54

int phy;

sys/dev/etherswitch/e6000sw/e6000sw.c

1409

e6000sw_miiforphy(e6000sw_softc_t *sc, unsigned int phy)

sys/dev/etherswitch/e6000sw/e6000sw.c

1413

if (!e6000sw_is_phyport(sc, phy))

sys/dev/etherswitch/e6000sw/e6000sw.c

1415

mii_dev = sc->miibus[phy];

sys/dev/etherswitch/e6000sw/e6000sw.c

1457

e6000sw_smi_waitready(e6000sw_softc_t *sc, int phy)

sys/dev/etherswitch/e6000sw/e6000sw.c

1462

if ((MDIO_READ(sc->dev, phy, SMI_CMD) & SMI_CMD_BUSY) == 0)

sys/dev/etherswitch/e6000sw/e6000sw.c

686

e6000sw_waitready(e6000sw_softc_t *sc, uint32_t phy, uint32_t reg,

sys/dev/etherswitch/e6000sw/e6000sw.c

692

if ((e6000sw_readreg(sc, phy, reg) & busybit) == 0)

sys/dev/etherswitch/e6000sw/e6000sw.c

702

e6000sw_read_xmdio(device_t dev, int phy, int devaddr, int devreg)

sys/dev/etherswitch/e6000sw/e6000sw.c

715

reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK;

sys/dev/etherswitch/e6000sw/e6000sw.c

741

e6000sw_write_xmdio(device_t dev, int phy, int devaddr, int devreg, int val)

sys/dev/etherswitch/e6000sw/e6000sw.c

754

reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK;

sys/dev/etherswitch/e6000sw/e6000sw.c

774

e6000sw_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/e6000sw/e6000sw.c

784

ret = e6000sw_readphy_locked(dev, phy, reg);

sys/dev/etherswitch/e6000sw/e6000sw.c

796

e6000sw_readphy_locked(device_t dev, int phy, int reg)

sys/dev/etherswitch/e6000sw/e6000sw.c

804

if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) {

sys/dev/etherswitch/e6000sw/e6000sw.c

816

((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK));

sys/dev/etherswitch/e6000sw/e6000sw.c

828

e6000sw_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/e6000sw/e6000sw.c

838

ret = e6000sw_writephy_locked(dev, phy, reg, data);

sys/dev/etherswitch/e6000sw/e6000sw.c

846

e6000sw_writephy_locked(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/e6000sw/e6000sw.c

853

if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) {

sys/dev/etherswitch/e6000sw/e6000sw.c

867

((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK));

sys/dev/etherswitch/e6000sw/e6000sw.c

875

int error, phy;

sys/dev/etherswitch/e6000sw/e6000sw.c

896

for (phy = 0; phy < sc->num_ports; phy++) {

sys/dev/etherswitch/e6000sw/e6000sw.c

897

if (sc->ifp[phy] != NULL)

sys/dev/etherswitch/e6000sw/e6000sw.c

898

if_free(sc->ifp[phy]);

sys/dev/etherswitch/e6000sw/e6000sw.c

899

if (sc->ifname[phy] != NULL)

sys/dev/etherswitch/e6000sw/e6000sw.c

900

free(sc->ifname[phy], M_E6000SW);

sys/dev/etherswitch/e6000sw/e6060sw.c

204

int phy, port, err;

sys/dev/etherswitch/e6000sw/e6060sw.c

211

for (phy = 0; phy < sc->numports; phy++) {

sys/dev/etherswitch/e6000sw/e6060sw.c

212

if (((1 << phy) & sc->phymask) == 0)

sys/dev/etherswitch/e6000sw/e6060sw.c

214

sc->ifpport[phy] = port;

sys/dev/etherswitch/e6000sw/e6060sw.c

215

sc->portphy[port] = phy;

sys/dev/etherswitch/e6000sw/e6060sw.c

225

BMSR_DEFCAPMASK, phy + sc->smi_offset, MII_OFFSET_ANY, 0);

sys/dev/etherswitch/e6000sw/e6060sw.c

232

phy);

sys/dev/etherswitch/e6000sw/e6060sw.c

358

e6060sw_portforphy(struct e6060sw_softc *sc, int phy)

sys/dev/etherswitch/e6000sw/e6060sw.c

361

return (sc->ifpport[phy]);

sys/dev/etherswitch/e6000sw/e6060sw.c

462

int err, phy;

sys/dev/etherswitch/e6000sw/e6060sw.c

477

phy = sc->portphy[p->es_port];

sys/dev/etherswitch/e6000sw/e6060sw.c

479

if (sc->cpuport != -1 && phy == sc->cpuport) {

sys/dev/etherswitch/e6000sw/e6060sw.c

909

e6060sw_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/e6000sw/e6060sw.c

917

if (phy < 0 || phy >= 32)

sys/dev/etherswitch/e6000sw/e6060sw.c

923

data = MDIO_READREG(device_get_parent(dev), phy, reg);

sys/dev/etherswitch/e6000sw/e6060sw.c

930

e6060sw_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/e6000sw/e6060sw.c

938

if (phy < 0 || phy >= 32)

sys/dev/etherswitch/e6000sw/e6060sw.c

944

err = MDIO_WRITEREG(device_get_parent(dev), phy, reg, data);

sys/dev/etherswitch/etherswitch.c

184

phyreg->val = ETHERSWITCH_READPHYREG(etherswitch, phyreg->phy, phyreg->reg);

sys/dev/etherswitch/etherswitch.c

189

error = ETHERSWITCH_WRITEPHYREG(etherswitch, phyreg->phy, phyreg->reg, phyreg->val);

sys/dev/etherswitch/etherswitch.h

21

uint16_t phy;

sys/dev/etherswitch/felix/felix.c

789

felix_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/felix/felix.c

795

return (enetc_mdio_read(sc->mdio, FELIX_MDIO_BASE, phy, reg));

sys/dev/etherswitch/felix/felix.c

799

felix_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/felix/felix.c

805

return (enetc_mdio_write(sc->mdio, FELIX_MDIO_BASE, phy, reg, data));

sys/dev/etherswitch/infineon/adm6996fc.c

163

int phy, port, err;

sys/dev/etherswitch/infineon/adm6996fc.c

170

for (phy = 0; phy < sc->numports; phy++) {

sys/dev/etherswitch/infineon/adm6996fc.c

171

if (((1 << phy) & sc->phymask) == 0)

sys/dev/etherswitch/infineon/adm6996fc.c

173

sc->ifpport[phy] = port;

sys/dev/etherswitch/infineon/adm6996fc.c

174

sc->portphy[port] = phy;

sys/dev/etherswitch/infineon/adm6996fc.c

184

BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);

sys/dev/etherswitch/infineon/adm6996fc.c

191

phy);

sys/dev/etherswitch/infineon/adm6996fc.c

206

for (phy = 0; phy < sc->numports; phy++) {

sys/dev/etherswitch/infineon/adm6996fc.c

207

if (((1 << phy) & sc->phymask) == 0)

sys/dev/etherswitch/infineon/adm6996fc.c

209

port = adm6996fc_portforphy(sc, phy);

sys/dev/etherswitch/infineon/adm6996fc.c

318

adm6996fc_portforphy(struct adm6996fc_softc *sc, int phy)

sys/dev/etherswitch/infineon/adm6996fc.c

321

return (sc->ifpport[phy]);

sys/dev/etherswitch/infineon/adm6996fc.c

423

int err, phy;

sys/dev/etherswitch/infineon/adm6996fc.c

453

phy = sc->portphy[p->es_port];

sys/dev/etherswitch/infineon/adm6996fc.c

455

if (sc->cpuport != -1 && phy == sc->cpuport) {

sys/dev/etherswitch/infineon/adm6996fc.c

735

adm6996fc_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/infineon/adm6996fc.c

743

if (phy < 0 || phy >= 32)

sys/dev/etherswitch/infineon/adm6996fc.c

750

(ADM6996FC_PHY_C0 + ADM6996FC_PHY_SIZE * phy) + reg);

sys/dev/etherswitch/infineon/adm6996fc.c

757

adm6996fc_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/infineon/adm6996fc.c

765

if (phy < 0 || phy >= 32)

sys/dev/etherswitch/infineon/adm6996fc.c

772

(ADM6996FC_PHY_C0 + ADM6996FC_PHY_SIZE * phy) + reg, data);

sys/dev/etherswitch/ip17x/ip175c.c

84

int i, err, phy;

sys/dev/etherswitch/ip17x/ip175c.c

92

phy = sc->portphy[i];

sys/dev/etherswitch/ip17x/ip175c.c

94

ports[phy] = v->ports;

sys/dev/etherswitch/ip17x/ip17x.c

162

int err, phy, port;

sys/dev/etherswitch/ip17x/ip17x.c

169

for (phy = 0; phy < MII_NPHY; phy++) {

sys/dev/etherswitch/ip17x/ip17x.c

170

if (((1 << phy) & sc->phymask) == 0)

sys/dev/etherswitch/ip17x/ip17x.c

172

sc->phyport[phy] = port;

sys/dev/etherswitch/ip17x/ip17x.c

173

sc->portphy[port] = phy;

sys/dev/etherswitch/ip17x/ip17x.c

183

BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);

sys/dev/etherswitch/ip17x/ip17x.c

190

phy);

sys/dev/etherswitch/ip17x/ip17x.c

401

int err, phy;

sys/dev/etherswitch/ip17x/ip17x.c

407

phy = sc->portphy[p->es_port];

sys/dev/etherswitch/ip17x/ip17x.c

410

p->es_pvid = sc->pvid[phy];

sys/dev/etherswitch/ip17x/ip17x.c

413

if (sc->addtag & (1 << phy))

sys/dev/etherswitch/ip17x/ip17x.c

415

if (sc->striptag & (1 << phy))

sys/dev/etherswitch/ip17x/ip17x.c

427

if (phy == sc->cpuport) {

sys/dev/etherswitch/ip17x/ip17x.c

455

int phy;

sys/dev/etherswitch/ip17x/ip17x.c

461

phy = sc->portphy[p->es_port];

sys/dev/etherswitch/ip17x/ip17x.c

475

sc->pvid[phy] = p->es_pvid;

sys/dev/etherswitch/ip17x/ip17x.c

484

sc->addtag &= ~(1 << phy);

sys/dev/etherswitch/ip17x/ip17x.c

485

sc->striptag &= ~(1 << phy);

sys/dev/etherswitch/ip17x/ip17x.c

489

sc->addtag |= (1 << phy);

sys/dev/etherswitch/ip17x/ip17x.c

491

sc->striptag |= (1 << phy);

sys/dev/etherswitch/ip17x/ip17x.c

499

if (phy == sc->cpuport)

sys/dev/etherswitch/ip17x/ip17x_phy.c

100

val = ip17x_readphy(dev, phy, reg);

sys/dev/etherswitch/ip17x/ip17x_phy.c

103

return (ip17x_writephy(dev, phy, reg, val));

sys/dev/etherswitch/ip17x/ip17x_phy.c

54

ip17x_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/ip17x/ip17x_phy.c

62

if (phy < 0 || phy >= 32)

sys/dev/etherswitch/ip17x/ip17x_phy.c

68

data = MDIO_READREG(device_get_parent(dev), phy, reg);

sys/dev/etherswitch/ip17x/ip17x_phy.c

75

ip17x_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/ip17x/ip17x_phy.c

83

if (phy < 0 || phy >= 32)

sys/dev/etherswitch/ip17x/ip17x_phy.c

89

err = MDIO_WRITEREG(device_get_parent(dev), phy, reg, data);

sys/dev/etherswitch/ip17x/ip17x_phy.c

96

ip17x_updatephy(device_t dev, int phy, int reg, int mask, int value)

sys/dev/etherswitch/ip17x/ip17x_vlans.c

143

uint32_t phy;

sys/dev/etherswitch/ip17x/ip17x_vlans.c

182

phy = sc->portphy[i];

sys/dev/etherswitch/ip17x/ip17x_vlans.c

183

sc->vlan[vg->es_vlangroup].ports |= (1 << phy);

sys/dev/etherswitch/ip17x/ip17x_vlans.c

62

int i, j, phy;

sys/dev/etherswitch/ip17x/ip17x_vlans.c

75

for (i = 0, phy = 0; phy < MII_NPHY; phy++) {

sys/dev/etherswitch/ip17x/ip17x_vlans.c

76

if (((1 << phy) & sc->phymask) == 0)

sys/dev/etherswitch/micrel/ksz8995ma.c

207

int phy, port, err;

sys/dev/etherswitch/micrel/ksz8995ma.c

214

for (phy = 0; phy < sc->numports; phy++) {

sys/dev/etherswitch/micrel/ksz8995ma.c

215

if (phy == sc->cpuport)

sys/dev/etherswitch/micrel/ksz8995ma.c

217

if (((1 << phy) & sc->phymask) == 0)

sys/dev/etherswitch/micrel/ksz8995ma.c

219

sc->ifpport[phy] = port;

sys/dev/etherswitch/micrel/ksz8995ma.c

220

sc->portphy[port] = phy;

sys/dev/etherswitch/micrel/ksz8995ma.c

230

BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);

sys/dev/etherswitch/micrel/ksz8995ma.c

237

phy);

sys/dev/etherswitch/micrel/ksz8995ma.c

253

for (phy = 0; phy < sc->numports; phy++) {

sys/dev/etherswitch/micrel/ksz8995ma.c

254

if (((1 << phy) & sc->phymask) == 0)

sys/dev/etherswitch/micrel/ksz8995ma.c

256

port = ksz8995ma_portforphy(sc, phy);

sys/dev/etherswitch/micrel/ksz8995ma.c

376

ksz8995ma_portforphy(struct ksz8995ma_softc *sc, int phy)

sys/dev/etherswitch/micrel/ksz8995ma.c

379

return (sc->ifpport[phy]);

sys/dev/etherswitch/micrel/ksz8995ma.c

482

int phy, err;

sys/dev/etherswitch/micrel/ksz8995ma.c

513

phy = sc->portphy[p->es_port];

sys/dev/etherswitch/micrel/ksz8995ma.c

515

if (sc->cpuport != -1 && phy == sc->cpuport) {

sys/dev/etherswitch/micrel/ksz8995ma.c

546

int phy, err;

sys/dev/etherswitch/micrel/ksz8995ma.c

590

phy = sc->portphy[p->es_port];

sys/dev/etherswitch/micrel/ksz8995ma.c

592

if (phy != sc->cpuport) {

sys/dev/etherswitch/micrel/ksz8995ma.c

785

ksz8995ma_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/micrel/ksz8995ma.c

795

KSZ8995MA_PORT_SIZE * phy);

sys/dev/etherswitch/micrel/ksz8995ma.c

805

KSZ8995MA_PORT_SIZE * phy);

sys/dev/etherswitch/micrel/ksz8995ma.c

809

KSZ8995MA_PORT_SIZE * phy);

sys/dev/etherswitch/micrel/ksz8995ma.c

817

ksz8995ma_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/micrel/ksz8995ma.c

827

KSZ8995MA_PORT_SIZE * phy);

sys/dev/etherswitch/micrel/ksz8995ma.c

837

KSZ8995MA_PORT_SIZE * phy, portreg);

sys/dev/etherswitch/micrel/ksz8995ma.c

840

KSZ8995MA_PORT_SIZE * phy);

sys/dev/etherswitch/micrel/ksz8995ma.c

844

KSZ8995MA_PORT_SIZE * phy, portreg);

sys/dev/etherswitch/miiproxy.c

282

miiproxy_readreg(device_t dev, int phy, int reg)

sys/dev/etherswitch/miiproxy.c

287

return (MDIO_READREG(sc->mdio, phy, reg));

sys/dev/etherswitch/miiproxy.c

292

miiproxy_writereg(device_t dev, int phy, int reg, int val)

sys/dev/etherswitch/miiproxy.c

297

return (MDIO_WRITEREG(sc->mdio, phy, reg, val));

sys/dev/etherswitch/mtkswitch/mtkswitch.c

111

int phy, err = 0;

sys/dev/etherswitch/mtkswitch/mtkswitch.c

116

for (phy = 0; phy < sc->numphys; phy++) {

sys/dev/etherswitch/mtkswitch/mtkswitch.c

117

if ((sc->phymap & (1u << phy)) == 0) {

sys/dev/etherswitch/mtkswitch/mtkswitch.c

118

sc->ifp[phy] = NULL;

sys/dev/etherswitch/mtkswitch/mtkswitch.c

119

sc->ifname[phy] = NULL;

sys/dev/etherswitch/mtkswitch/mtkswitch.c

120

sc->miibus[phy] = NULL;

sys/dev/etherswitch/mtkswitch/mtkswitch.c

123

sc->ifp[phy] = if_alloc(IFT_ETHER);

sys/dev/etherswitch/mtkswitch/mtkswitch.c

124

if_setsoftc(sc->ifp[phy], sc);

sys/dev/etherswitch/mtkswitch/mtkswitch.c

125

if_setflagbits(sc->ifp[phy], IFF_UP | IFF_BROADCAST |

sys/dev/etherswitch/mtkswitch/mtkswitch.c

127

sc->ifname[phy] = malloc(strlen(name) + 1, M_DEVBUF, M_WAITOK);

sys/dev/etherswitch/mtkswitch/mtkswitch.c

128

bcopy(name, sc->ifname[phy], strlen(name) + 1);

sys/dev/etherswitch/mtkswitch/mtkswitch.c

129

if_initname(sc->ifp[phy], sc->ifname[phy],

sys/dev/etherswitch/mtkswitch/mtkswitch.c

130

mtkswitch_portforphy(phy));

sys/dev/etherswitch/mtkswitch/mtkswitch.c

131

err = mii_attach(sc->sc_dev, &sc->miibus[phy], sc->ifp[phy],

sys/dev/etherswitch/mtkswitch/mtkswitch.c

133

BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);

sys/dev/etherswitch/mtkswitch/mtkswitch.c

137

phy);

sys/dev/etherswitch/mtkswitch/mtkswitch.c

140

"%s\n", device_get_nameunit(sc->miibus[phy]),

sys/dev/etherswitch/mtkswitch/mtkswitch.c

141

if_name(sc->ifp[phy]));

sys/dev/etherswitch/mtkswitch/mtkswitch.c

251

int error, phy;

sys/dev/etherswitch/mtkswitch/mtkswitch.c

259

for (phy = 0; phy < MTKSWITCH_MAX_PHYS; phy++) {

sys/dev/etherswitch/mtkswitch/mtkswitch.c

260

if (sc->ifp[phy] != NULL)

sys/dev/etherswitch/mtkswitch/mtkswitch.c

261

if_free(sc->ifp[phy]);

sys/dev/etherswitch/mtkswitch/mtkswitch.c

262

free(sc->ifname[phy], M_DEVBUF);

sys/dev/etherswitch/mtkswitch/mtkswitch.c

272

mtkswitch_portforphy(int phy)

sys/dev/etherswitch/mtkswitch/mtkswitch.c

275

return (phy);

sys/dev/etherswitch/mtkswitch/mtkswitch.c

288

int phy = mtkswitch_phyforport(port);

sys/dev/etherswitch/mtkswitch/mtkswitch.c

290

if (phy < 0 || phy >= MTKSWITCH_MAX_PHYS || sc->miibus[phy] == NULL)

sys/dev/etherswitch/mtkswitch/mtkswitch.c

293

return (device_get_softc(sc->miibus[phy]));

sys/dev/etherswitch/mtkswitch/mtkswitch.c

299

int phy = mtkswitch_phyforport(port);

sys/dev/etherswitch/mtkswitch/mtkswitch.c

301

if (phy < 0 || phy >= MTKSWITCH_MAX_PHYS)

sys/dev/etherswitch/mtkswitch/mtkswitch.c

304

return (sc->ifp[phy]);

sys/dev/etherswitch/mtkswitch/mtkswitch.c

587

mtkswitch_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/mtkswitch/mtkswitch.c

591

return (sc->hal.mtkswitch_phy_read(dev, phy, reg));

sys/dev/etherswitch/mtkswitch/mtkswitch.c

595

mtkswitch_writephy(device_t dev, int phy, int reg, int val)

sys/dev/etherswitch/mtkswitch/mtkswitch.c

599

return (sc->hal.mtkswitch_phy_write(dev, phy, reg, val));

sys/dev/etherswitch/mtkswitch/mtkswitch.c

69

static inline int mtkswitch_portforphy(int phy);

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

100

mtkswitch_phy_write(device_t dev, int phy, int reg, int val)

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

105

if ((phy < 0 || phy >= 32) || (reg < 0 || reg >= 32))

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

110

res = mtkswitch_phy_write_locked(sc, phy, reg, val);

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

57

mtkswitch_phy_read_locked(struct mtkswitch_softc *sc, int phy, int reg)

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

62

(reg << PIAC_MDIO_REG_ADDR_OFF) | (phy << PIAC_MDIO_PHY_ADDR_OFF) |

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

70

mtkswitch_phy_read(device_t dev, int phy, int reg)

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

75

if ((phy < 0 || phy >= 32) || (reg < 0 || reg >= 32))

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

80

data = mtkswitch_phy_read_locked(sc, phy, reg);

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

87

mtkswitch_phy_write_locked(struct mtkswitch_softc *sc, int phy, int reg,

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

92

(reg << PIAC_MDIO_REG_ADDR_OFF) | (phy << PIAC_MDIO_PHY_ADDR_OFF) |

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

108

mtkswitch_phy_write(device_t dev, int phy, int reg, int val)

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

116

PCR0_PHY(phy) | PCR0_DATA(val));

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

90

mtkswitch_phy_read(device_t dev, int phy, int reg)

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

99

PCR0_PHY(phy));

sys/dev/etherswitch/rtl8366/rtl8366rb.c

821

rtl_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/rtl8366/rtl8366rb.c

831

if (phy < 0 || phy >= RTL8366_NUM_PHYS)

sys/dev/etherswitch/rtl8366/rtl8366rb.c

842

err = smi_write_locked(sc, RTL8366_PHYREG(phy, 0, reg), 0, sleep);

sys/dev/etherswitch/rtl8366/rtl8366rb.c

852

DEVERR(dev, err, "rtl_readphy()=%d: phy=%d.%02x\n", phy, reg);

sys/dev/etherswitch/rtl8366/rtl8366rb.c

857

rtl_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/rtl8366/rtl8366rb.c

864

if (phy < 0 || phy >= RTL8366_NUM_PHYS)

sys/dev/etherswitch/rtl8366/rtl8366rb.c

875

err = smi_write_locked(sc, RTL8366_PHYREG(phy, 0, reg), data, sleep);

sys/dev/etherswitch/rtl8366/rtl8366rb.c

884

DEVERR(dev, err, "rtl_writephy()=%d: phy=%d.%02x\n", phy, reg);

sys/dev/etherswitch/rtl8366/rtl8366rbvar.h

175

#define RTL8366_PHYREG(phy, page, reg) \

sys/dev/etherswitch/rtl8366/rtl8366rbvar.h

176

(0x8000 | (1 << (((phy) & 0x1f) + 9)) | (((page) & (sc->chip_type == 0 ? 0xf : 0x7)) << 5) | ((reg) & 0x1f))

sys/dev/etherswitch/ukswitch/ukswitch.c

116

int phy, port = 0, err = 0;

sys/dev/etherswitch/ukswitch/ukswitch.c

121

for (phy = 0; phy < MII_NPHY; phy++) {

sys/dev/etherswitch/ukswitch/ukswitch.c

122

if (((1 << phy) & sc->phymask) == 0)

sys/dev/etherswitch/ukswitch/ukswitch.c

124

sc->ifpport[phy] = port;

sys/dev/etherswitch/ukswitch/ukswitch.c

125

sc->portphy[port] = phy;

sys/dev/etherswitch/ukswitch/ukswitch.c

137

BMSR_DEFCAPMASK, phy + sc->phyoffset, MII_OFFSET_ANY, 0);

sys/dev/etherswitch/ukswitch/ukswitch.c

144

phy);

sys/dev/etherswitch/ukswitch/ukswitch.c

259

ukswitch_portforphy(struct ukswitch_softc *sc, int phy)

sys/dev/etherswitch/ukswitch/ukswitch.c

262

return (sc->ifpport[phy]);

sys/dev/etherswitch/ukswitch/ukswitch.c

353

int err, phy;

sys/dev/etherswitch/ukswitch/ukswitch.c

359

phy = sc->portphy[p->es_port];

sys/dev/etherswitch/ukswitch/ukswitch.c

361

if (sc->cpuport != -1 && phy == sc->cpuport) {

sys/dev/etherswitch/ukswitch/ukswitch.c

466

ukswitch_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/ukswitch/ukswitch.c

474

if (phy < 0 || phy >= 32)

sys/dev/etherswitch/ukswitch/ukswitch.c

480

data = MDIO_READREG(device_get_parent(dev), phy, reg);

sys/dev/etherswitch/ukswitch/ukswitch.c

487

ukswitch_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/ukswitch/ukswitch.c

495

if (phy < 0 || phy >= 32)

sys/dev/etherswitch/ukswitch/ukswitch.c

501

err = MDIO_WRITEREG(device_get_parent(dev), phy, reg, data);

sys/dev/ffec/if_ffec.c

318

ffec_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/ffec/if_ffec.c

329

((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |

sys/dev/ffec/if_ffec.c

343

ffec_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/ffec/if_ffec.c

353

((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |

sys/dev/fxp/if_fxp.c

264

static int fxp_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/fxp/if_fxp.c

265

static int fxp_miibus_writereg(device_t dev, int phy, int reg,

sys/dev/fxp/if_fxp.c

2735

fxp_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/fxp/if_fxp.c

2742

(FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));

sys/dev/fxp/if_fxp.c

2755

fxp_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/fxp/if_fxp.c

2761

(FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |

sys/dev/gem/if_gem.c

147

int error, i, phy;

sys/dev/gem/if_gem.c

1832

gem_mii_readreg(device_t dev, int phy, int reg)

sys/dev/gem/if_gem.c

1839

printf("%s: phy %d reg %d\n", __func__, phy, reg);

sys/dev/gem/if_gem.c

1872

(phy << GEM_MIF_PHY_SHIFT) |

sys/dev/gem/if_gem.c

1890

gem_mii_writereg(device_t dev, int phy, int reg, int val)

sys/dev/gem/if_gem.c

1897

printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__);

sys/dev/gem/if_gem.c

1950

(phy << GEM_MIF_PHY_SHIFT) |

sys/dev/gem/if_gem.c

301

phy = GEM_PHYAD_INTERNAL;

sys/dev/gem/if_gem.c

304

phy = GEM_PHYAD_EXTERNAL;

sys/dev/gem/if_gem.c

307

phy = MII_PHY_ANY;

sys/dev/gem/if_gem.c

311

gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy,

sys/dev/gem/if_gemvar.h

258

int gem_mii_readreg(device_t dev, int phy, int reg);

sys/dev/gem/if_gemvar.h

260

int gem_mii_writereg(device_t dev, int phy, int reg, int val);

sys/dev/gpio/gpiomdio.c

185

gpiomdio_readreg(device_t dev, int phy, int reg)

sys/dev/gpio/gpiomdio.c

191

return (mii_bitbang_readreg(dev, &sc->miibb_ops, phy, reg));

sys/dev/gpio/gpiomdio.c

195

gpiomdio_writereg(device_t dev, int phy, int reg, int val)

sys/dev/gpio/gpiomdio.c

200

mii_bitbang_writereg(dev, &sc->miibb_ops, phy, reg, val);

sys/dev/hptiop/hptiop.c

2668

u_int64_t phy;

sys/dev/hptiop/hptiop.c

2671

phy = ((u_int64_t)segs->ds_addr + 0x1F)

sys/dev/hptiop/hptiop.c

2676

hba->ctlcfgcmd_phy = phy;

sys/dev/hptiop/hptiop.c

2680

phy += 0x800;

sys/dev/hptiop/hptiop.c

2683

hba->u.mvfrey.inlist_phy = phy;

sys/dev/hptiop/hptiop.c

2686

phy += list_count * sizeof(struct mvfrey_inlist_entry);

sys/dev/hptiop/hptiop.c

2689

hba->u.mvfrey.outlist_phy = phy;

sys/dev/hptiop/hptiop.c

2692

phy += list_count * sizeof(struct mvfrey_outlist_entry);

sys/dev/hptiop/hptiop.c

2695

hba->u.mvfrey.outlist_cptr_phy = phy;

sys/dev/ice/ice_common.c

3657

pi->phy.curr_user_phy_cfg = *cfg;

sys/dev/ice/ice_common.c

3674

li = &pi->phy.link_info;

sys/dev/ice/ice_common.c

3722

pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;

sys/dev/ice/ice_common.c

3725

pi->phy.curr_user_speed_req =

sys/dev/ice/ice_common.c

3729

pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;

sys/dev/ice/ice_common.c

4115

phy_info = &pi->phy;

sys/dev/ice/ice_common.c

4162

pi->phy.curr_user_phy_cfg.caps |= ICE_AQC_PHY_EN_LINK;

sys/dev/ice/ice_common.c

4164

pi->phy.curr_user_phy_cfg.caps &= ~ICE_AQC_PHY_EN_LINK;

sys/dev/ice/ice_common.c

464

phy_type_high = pi->phy.phy_type_high;

sys/dev/ice/ice_common.c

465

phy_type_low = pi->phy.phy_type_low;

sys/dev/ice/ice_common.c

466

media_type = &pi->phy.media_type;

sys/dev/ice/ice_common.c

469

if (!(pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE))

sys/dev/ice/ice_common.c

598

pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);

sys/dev/ice/ice_common.c

599

pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);

sys/dev/ice/ice_common.c

600

ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type,

sys/dev/ice/ice_common.c

601

sizeof(pi->phy.link_info.module_type),

sys/dev/ice/ice_common.c

605

pi->phy.media_type);

sys/dev/ice/ice_common.c

698

li_old = &pi->phy.link_info_old;

sys/dev/ice/ice_common.c

699

li = &pi->phy.link_info;

sys/dev/ice/ice_common.c

765

pi->phy.get_link_info = false;

sys/dev/ice/ice_iov.c

1648

hw->port_info->phy.link_info.link_speed);

sys/dev/ice/ice_lib.c

1169

uint64_t phy_low = pi->phy.phy_type_low;

sys/dev/ice/ice_lib.c

1170

uint64_t phy_high = pi->phy.phy_type_high;

sys/dev/ice/ice_lib.c

2222

pi->phy.get_link_info = true;

sys/dev/ice/ice_lib.c

2225

if (pi->phy.link_info.topo_media_conflict &

sys/dev/ice/ice_lib.c

2231

if ((pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) &&

sys/dev/ice/ice_lib.c

2232

!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP)) {

sys/dev/ice/ice_lib.c

2233

if (!(pi->phy.link_info.an_info & ICE_AQ_QUALIFIED_MODULE))

sys/dev/ice/ice_lib.c

2236

if (pi->phy.link_info.link_cfg_err & ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED)

sys/dev/ice/ice_lib.c

2239

if (pi->phy.link_info.link_cfg_err & ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT)

sys/dev/ice/ice_lib.c

2244

if (!(pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE)) {

sys/dev/ice/ice_lib.c

3336

pi->phy.curr_user_speed_req = sysctl_speeds;

sys/dev/ice/ice_lib.c

3410

pi->phy.curr_user_fec_req = new_mode;

sys/dev/ice/ice_lib.c

3572

pi->phy.curr_user_fc_req = new_mode;

sys/dev/ice/ice_lib.c

3668

cfg.phy_type_high = types & hw->port_info->phy.phy_type_high;

sys/dev/ice/ice_lib.c

3670

cfg.phy_type_low = types & hw->port_info->phy.phy_type_low;

sys/dev/ice/ice_lib.c

4415

if (user_pfc != 0 && pi->phy.curr_user_fc_req != ICE_FC_NONE) {

sys/dev/ice/ice_lib.c

4416

pi->phy.curr_user_fc_req = ICE_FC_NONE;

sys/dev/ice/ice_lib.c

7970

if (pi->phy.link_info.fec_info & (ICE_AQ_LINK_25G_RS_528_FEC_EN |

sys/dev/ice/ice_lib.c

7975

if (pi->phy.link_info.fec_info & ICE_AQ_LINK_25G_KR_FEC_EN)

sys/dev/ice/ice_lib.c

7990

if (pi->phy.link_info.an_info & ICE_AQ_AN_COMPLETED)

sys/dev/ice/ice_lib.c

894

switch (pi->phy.link_info.link_speed) {

sys/dev/ice/ice_lib.c

934

switch (pi->phy.link_info.link_speed) {

sys/dev/ice/ice_lib.c

9503

pi->phy.get_link_info = true;

sys/dev/ice/ice_lib.c

9525

if (pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) {

sys/dev/ice/ice_lib.c

9567

link_speeds = pi->phy.curr_user_speed_req;

sys/dev/ice/ice_lib.c

9681

status = ice_cfg_phy_fec(pi, cfg, pi->phy.curr_user_fec_req);

sys/dev/ice/ice_lib.c

9704

switch (pi->phy.curr_user_fc_req) {

sys/dev/ice/ice_lib.c

9776

pi->phy.curr_user_speed_req = dflt_user_speed;

sys/dev/ice/ice_lib.c

9782

pi->phy.curr_user_fec_req = dflt_fec_mode;

sys/dev/ice/ice_lib.c

9987

pi->phy.curr_user_speed_req =

sys/dev/ice/ice_lib.c

9989

pi->phy.curr_user_fec_req = ice_caps_to_fec_mode(pcaps.caps,

sys/dev/ice/ice_lib.c

9991

pi->phy.curr_user_fc_req = ice_caps_to_fc_mode(pcaps.caps);

sys/dev/ice/ice_type.h

965

struct ice_phy_info phy;

sys/dev/ice/if_ice_iflib.c

1981

struct ice_link_status *li = &sc->hw.port_info->phy.link_info;

sys/dev/ice/if_ice_iflib.c

2208

pi->phy.get_link_info = true;

sys/dev/ice/if_ice_iflib.c

2211

if (pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) {

sys/dev/ice/if_ice_iflib.c

745

if (!(hw->port_info->phy.link_info_old.link_info & ICE_AQ_LINK_UP))

sys/dev/igc/if_igc.c

1256

sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;

sys/dev/igc/if_igc.c

1259

sc->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL;

sys/dev/igc/if_igc.c

1262

sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;

sys/dev/igc/if_igc.c

1266

sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL;

sys/dev/igc/if_igc.c

1268

sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF;

sys/dev/igc/if_igc.c

1272

sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL;

sys/dev/igc/if_igc.c

1274

sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF;

sys/dev/igc/if_igc.c

1403

switch (hw->phy.media_type) {

sys/dev/igc/if_igc.c

607

hw->phy.autoneg_wait_to_complete = false;

sys/dev/igc/if_igc.c

608

hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;

sys/dev/igc/if_igc.c

611

if (hw->phy.media_type == igc_media_type_copper) {

sys/dev/igc/if_igc.c

612

hw->phy.mdix = AUTO_ALL_MODES;

sys/dev/igc/igc_api.c

439

if (hw->phy.ops.check_reset_block)

sys/dev/igc/igc_api.c

440

return hw->phy.ops.check_reset_block(hw);

sys/dev/igc/igc_api.c

456

if (hw->phy.ops.read_reg)

sys/dev/igc/igc_api.c

457

return hw->phy.ops.read_reg(hw, offset, data);

sys/dev/igc/igc_api.c

473

if (hw->phy.ops.write_reg)

sys/dev/igc/igc_api.c

474

return hw->phy.ops.write_reg(hw, offset, data);

sys/dev/igc/igc_api.c

488

if (hw->phy.ops.release)

sys/dev/igc/igc_api.c

489

hw->phy.ops.release(hw);

sys/dev/igc/igc_api.c

501

if (hw->phy.ops.acquire)

sys/dev/igc/igc_api.c

502

return hw->phy.ops.acquire(hw);

sys/dev/igc/igc_api.c

517

if (hw->phy.ops.get_info)

sys/dev/igc/igc_api.c

518

return hw->phy.ops.get_info(hw);

sys/dev/igc/igc_api.c

532

if (hw->phy.ops.reset)

sys/dev/igc/igc_api.c

533

return hw->phy.ops.reset(hw);

sys/dev/igc/igc_api.c

554

if (hw->phy.ops.set_d0_lplu_state)

sys/dev/igc/igc_api.c

555

return hw->phy.ops.set_d0_lplu_state(hw, active);

sys/dev/igc/igc_api.c

576

if (hw->phy.ops.set_d3_lplu_state)

sys/dev/igc/igc_api.c

577

return hw->phy.ops.set_d3_lplu_state(hw, active);

sys/dev/igc/igc_api.c

702

if (hw->phy.ops.power_up)

sys/dev/igc/igc_api.c

703

hw->phy.ops.power_up(hw);

sys/dev/igc/igc_api.c

717

if (hw->phy.ops.power_down)

sys/dev/igc/igc_api.c

718

hw->phy.ops.power_down(hw);

sys/dev/igc/igc_api.c

73

if (hw->phy.ops.init_params) {

sys/dev/igc/igc_api.c

74

ret_val = hw->phy.ops.init_params(hw);

sys/dev/igc/igc_base.c

100

if (!(phy->ops.check_reset_block))

sys/dev/igc/igc_base.c

104

if (phy->ops.check_reset_block(hw))

sys/dev/igc/igc_base.c

98

struct igc_phy_info *phy = &hw->phy;

sys/dev/igc/igc_hw.h

521

struct igc_phy_info phy;

sys/dev/igc/igc_i225.c

1076

hw->phy.ops.init_params = igc_init_phy_params_i225;

sys/dev/igc/igc_i225.c

1170

hw->phy.media_type != igc_media_type_copper)

sys/dev/igc/igc_i225.c

135

struct igc_phy_info *phy = &hw->phy;

sys/dev/igc/igc_i225.c

141

if (hw->phy.media_type != igc_media_type_copper) {

sys/dev/igc/igc_i225.c

142

phy->type = igc_phy_none;

sys/dev/igc/igc_i225.c

146

phy->ops.power_up = igc_power_up_phy_copper;

sys/dev/igc/igc_i225.c

147

phy->ops.power_down = igc_power_down_phy_copper_base;

sys/dev/igc/igc_i225.c

149

phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500;

sys/dev/igc/igc_i225.c

151

phy->reset_delay_us = 100;

sys/dev/igc/igc_i225.c

153

phy->ops.acquire = igc_acquire_phy_base;

sys/dev/igc/igc_i225.c

154

phy->ops.check_reset_block = igc_check_reset_block_generic;

sys/dev/igc/igc_i225.c

155

phy->ops.release = igc_release_phy_base;

sys/dev/igc/igc_i225.c

156

phy->ops.reset = igc_phy_hw_reset_generic;

sys/dev/igc/igc_i225.c

157

phy->ops.read_reg = igc_read_phy_reg_gpy;

sys/dev/igc/igc_i225.c

158

phy->ops.write_reg = igc_write_phy_reg_gpy;

sys/dev/igc/igc_i225.c

165

ret_val = hw->phy.ops.reset(hw);

sys/dev/igc/igc_i225.c

170

phy->type = igc_phy_i225;

sys/dev/igc/igc_i225.c

901

if ((hw->phy.media_type == igc_media_type_copper) &&

sys/dev/igc/igc_i225.c

93

hw->phy.media_type = igc_media_type_copper;

sys/dev/igc/igc_mac.c

536

if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))

sys/dev/igc/igc_mac.c

729

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);

sys/dev/igc/igc_mac.c

732

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);

sys/dev/igc/igc_mac.c

747

ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,

sys/dev/igc/igc_mac.c

751

ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,

sys/dev/igc/igc_phy.c

1018

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);

sys/dev/igc/igc_phy.c

1022

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);

sys/dev/igc/igc_phy.c

1026

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |

sys/dev/igc/igc_phy.c

1032

ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);

sys/dev/igc/igc_phy.c

1034

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);

sys/dev/igc/igc_phy.c

1039

ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);

sys/dev/igc/igc_phy.c

133

struct igc_phy_info *phy = &hw->phy;

sys/dev/igc/igc_phy.c

139

if (!phy->ops.read_reg)

sys/dev/igc/igc_phy.c

142

ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);

sys/dev/igc/igc_phy.c

146

phy->id = (u32)(phy_id << 16);

sys/dev/igc/igc_phy.c

148

ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);

sys/dev/igc/igc_phy.c

152

phy->id |= (u32)(phy_id & PHY_REVISION_MASK);

sys/dev/igc/igc_phy.c

153

phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

sys/dev/igc/igc_phy.c

169

struct igc_phy_info *phy = &hw->phy;

sys/dev/igc/igc_phy.c

184

(phy->addr << IGC_MDIC_PHY_SHIFT) |

sys/dev/igc/igc_phy.c

20

struct igc_phy_info *phy = &hw->phy;

sys/dev/igc/igc_phy.c

228

struct igc_phy_info *phy = &hw->phy;

sys/dev/igc/igc_phy.c

24

phy->ops.init_params = igc_null_ops_generic;

sys/dev/igc/igc_phy.c

244

(phy->addr << IGC_MDIC_PHY_SHIFT) |

sys/dev/igc/igc_phy.c

25

phy->ops.acquire = igc_null_ops_generic;

sys/dev/igc/igc_phy.c

26

phy->ops.check_reset_block = igc_null_ops_generic;

sys/dev/igc/igc_phy.c

27

phy->ops.force_speed_duplex = igc_null_ops_generic;

sys/dev/igc/igc_phy.c

28

phy->ops.get_info = igc_null_ops_generic;

sys/dev/igc/igc_phy.c

288

struct igc_phy_info *phy = &hw->phy;

sys/dev/igc/igc_phy.c

29

phy->ops.set_page = igc_null_set_page;

sys/dev/igc/igc_phy.c

296

phy->autoneg_advertised &= phy->autoneg_mask;

sys/dev/igc/igc_phy.c

299

ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);

sys/dev/igc/igc_phy.c

30

phy->ops.read_reg = igc_null_read_reg;

sys/dev/igc/igc_phy.c

303

if (phy->autoneg_mask & ADVERTISE_1000_FULL) {

sys/dev/igc/igc_phy.c

305

ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,

sys/dev/igc/igc_phy.c

31

phy->ops.read_reg_locked = igc_null_read_reg;

sys/dev/igc/igc_phy.c

311

if (phy->autoneg_mask & ADVERTISE_2500_FULL) {

sys/dev/igc/igc_phy.c

313

ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<

sys/dev/igc/igc_phy.c

32

phy->ops.read_reg_page = igc_null_read_reg;

sys/dev/igc/igc_phy.c

33

phy->ops.release = igc_null_phy_generic;

sys/dev/igc/igc_phy.c

339

DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);

sys/dev/igc/igc_phy.c

34

phy->ops.reset = igc_null_ops_generic;

sys/dev/igc/igc_phy.c

342

if (phy->autoneg_advertised & ADVERTISE_10_HALF) {

sys/dev/igc/igc_phy.c

348

if (phy->autoneg_advertised & ADVERTISE_10_FULL) {

sys/dev/igc/igc_phy.c

35

phy->ops.set_d0_lplu_state = igc_null_lplu_state;

sys/dev/igc/igc_phy.c

354

if (phy->autoneg_advertised & ADVERTISE_100_HALF) {

sys/dev/igc/igc_phy.c

36

phy->ops.set_d3_lplu_state = igc_null_lplu_state;

sys/dev/igc/igc_phy.c

360

if (phy->autoneg_advertised & ADVERTISE_100_FULL) {

sys/dev/igc/igc_phy.c

366

if (phy->autoneg_advertised & ADVERTISE_1000_HALF)

sys/dev/igc/igc_phy.c

37

phy->ops.write_reg = igc_null_write_reg;

sys/dev/igc/igc_phy.c

370

if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {

sys/dev/igc/igc_phy.c

376

if (phy->autoneg_advertised & ADVERTISE_2500_HALF)

sys/dev/igc/igc_phy.c

38

phy->ops.write_reg_locked = igc_null_write_reg;

sys/dev/igc/igc_phy.c

380

if (phy->autoneg_advertised & ADVERTISE_2500_FULL) {

sys/dev/igc/igc_phy.c

39

phy->ops.write_reg_page = igc_null_write_reg;

sys/dev/igc/igc_phy.c

40

phy->ops.power_up = igc_null_phy_generic;

sys/dev/igc/igc_phy.c

41

phy->ops.power_down = igc_null_phy_generic;

sys/dev/igc/igc_phy.c

441

ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);

sys/dev/igc/igc_phy.c

447

if (phy->autoneg_mask & ADVERTISE_1000_FULL)

sys/dev/igc/igc_phy.c

448

ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,

sys/dev/igc/igc_phy.c

451

if (phy->autoneg_mask & ADVERTISE_2500_FULL)

sys/dev/igc/igc_phy.c

452

ret_val = phy->ops.write_reg(hw,

sys/dev/igc/igc_phy.c

472

struct igc_phy_info *phy = &hw->phy;

sys/dev/igc/igc_phy.c

481

phy->autoneg_advertised &= phy->autoneg_mask;

sys/dev/igc/igc_phy.c

486

if (!phy->autoneg_advertised)

sys/dev/igc/igc_phy.c

487

phy->autoneg_advertised = phy->autoneg_mask;

sys/dev/igc/igc_phy.c

500

ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);

sys/dev/igc/igc_phy.c

505

ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);

sys/dev/igc/igc_phy.c

512

if (phy->autoneg_wait_to_complete) {

sys/dev/igc/igc_phy.c

553

ret_val = hw->phy.ops.force_speed_duplex(hw);

sys/dev/igc/igc_phy.c

656

struct igc_phy_info *phy = &hw->phy;

sys/dev/igc/igc_phy.c

662

if (!hw->phy.ops.read_reg)

sys/dev/igc/igc_phy.c

665

ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data);

sys/dev/igc/igc_phy.c

671

ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,

sys/dev/igc/igc_phy.c

680

if (phy->smart_speed == igc_smart_speed_on) {

sys/dev/igc/igc_phy.c

681

ret_val = phy->ops.read_reg(hw,

sys/dev/igc/igc_phy.c

688

ret_val = phy->ops.write_reg(hw,

sys/dev/igc/igc_phy.c

693

} else if (phy->smart_speed == igc_smart_speed_off) {

sys/dev/igc/igc_phy.c

694

ret_val = phy->ops.read_reg(hw,

sys/dev/igc/igc_phy.c

701

ret_val = phy->ops.write_reg(hw,

sys/dev/igc/igc_phy.c

707

} else if ((phy->autoneg_advertised == IGC_ALL_SPEED_DUPLEX) ||

sys/dev/igc/igc_phy.c

708

(phy->autoneg_advertised == IGC_ALL_NOT_GIG) ||

sys/dev/igc/igc_phy.c

709

(phy->autoneg_advertised == IGC_ALL_10_SPEED)) {

sys/dev/igc/igc_phy.c

711

ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,

sys/dev/igc/igc_phy.c

717

ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG,

sys/dev/igc/igc_phy.c

723

ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG,

sys/dev/igc/igc_phy.c

740

struct igc_phy_info *phy = &hw->phy;

sys/dev/igc/igc_phy.c

745

switch (phy->type) {

sys/dev/igc/igc_phy.c

749

phy->speed_downgraded = false;

sys/dev/igc/igc_phy.c

770

if (!hw->phy.ops.read_reg)

sys/dev/igc/igc_phy.c

775

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);

sys/dev/igc/igc_phy.c

778

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);

sys/dev/igc/igc_phy.c

809

if (!hw->phy.ops.read_reg)

sys/dev/igc/igc_phy.c

817

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);

sys/dev/igc/igc_phy.c

828

ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);

sys/dev/igc/igc_phy.c

855

struct igc_phy_info *phy = &hw->phy;

sys/dev/igc/igc_phy.c

861

if (phy->ops.check_reset_block) {

sys/dev/igc/igc_phy.c

862

ret_val = phy->ops.check_reset_block(hw);

sys/dev/igc/igc_phy.c

867

ret_val = phy->ops.acquire(hw);

sys/dev/igc/igc_phy.c

877

usec_delay(phy->reset_delay_us);

sys/dev/igc/igc_phy.c

893

phy->ops.release(hw);

sys/dev/igc/igc_phy.c

911

hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);

sys/dev/igc/igc_phy.c

913

hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);

sys/dev/igc/igc_phy.c

930

hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);

sys/dev/igc/igc_phy.c

932

hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);

sys/dev/igc/igc_phy.c

954

ret_val = hw->phy.ops.acquire(hw);

sys/dev/igc/igc_phy.c

960

hw->phy.ops.release(hw);

sys/dev/igc/igc_phy.c

988

ret_val = hw->phy.ops.acquire(hw);

sys/dev/igc/igc_phy.c

994

hw->phy.ops.release(hw);

sys/dev/isci/isci.c

186

int i, phy;

sys/dev/isci/isci.c

226

for (phy = 0; phy < SCI_MAX_PHYS; phy++) {

sys/dev/isci/isci.c

227

if (controller->phys[phy].cdev_fault)

sys/dev/isci/isci.c

228

led_destroy(controller->phys[phy].cdev_fault);

sys/dev/isci/isci.c

230

if (controller->phys[phy].cdev_locate)

sys/dev/isci/isci.c

231

led_destroy(controller->phys[phy].cdev_locate);

sys/dev/isci/isci.c

674

SCI_PORT_HANDLE_T port, SCI_PHY_HANDLE_T phy)

sys/dev/isci/isci_controller.c

279

struct ISCI_PHY *phy = priv;

sys/dev/isci/isci_controller.c

282

phy->led_fault = onoff;

sys/dev/isci/isci_controller.c

283

scic_sgpio_update_led_state(phy->handle, 1 << phy->index,

sys/dev/isci/isci_controller.c

284

phy->led_fault, phy->led_locate, 0);

sys/dev/isci/isci_controller.c

289

struct ISCI_PHY *phy = priv;

sys/dev/isci/isci_controller.c

292

phy->led_locate = onoff;

sys/dev/isci/isci_controller.c

293

scic_sgpio_update_led_state(phy->handle, 1 << phy->index,

sys/dev/isci/isci_controller.c

294

phy->led_fault, phy->led_locate, 0);

sys/dev/isci/scil/scic_phy.h

283

SCI_PHY_HANDLE_T phy,

sys/dev/isci/scil/scic_phy.h

305

SCI_PHY_HANDLE_T phy,

sys/dev/isci/scil/scic_phy.h

327

SCI_PHY_HANDLE_T phy,

sys/dev/isci/scil/scic_phy.h

344

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_phy.h

363

SCI_PHY_HANDLE_T phy,

sys/dev/isci/scil/scic_phy.h

383

SCI_PHY_HANDLE_T phy,

sys/dev/isci/scil/scic_phy.h

405

SCI_PHY_HANDLE_T phy,

sys/dev/isci/scil/scic_phy.h

426

SCI_PHY_HANDLE_T phy,

sys/dev/isci/scil/scic_phy.h

441

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_phy.h

454

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_port.h

171

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_port.h

193

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_remote_device.h

243

#define scic_remote_device_da_add_phy(device, phy) SCI_FAILURE

sys/dev/isci/scil/scic_remote_device.h

252

#define scic_remote_device_da_add_phy(device, phy) SCI_FAILURE

sys/dev/isci/scil/scic_sds_controller.c

2183

SCIC_SDS_PHY_T * phy;

sys/dev/isci/scil/scic_sds_controller.c

2207

phy = &this_controller->phy_table[index];

sys/dev/isci/scil/scic_sds_controller.c

2208

if (phy != NULL)

sys/dev/isci/scil/scic_sds_controller.c

2210

result = scic_sds_phy_frame_handler(phy, frame_index);

sys/dev/isci/scil/scic_sds_controller.c

2224

phy = &this_controller->phy_table[index];

sys/dev/isci/scil/scic_sds_controller.c

2225

result = scic_sds_phy_frame_handler(phy, frame_index);

sys/dev/isci/scil/scic_sds_controller.c

2266

SCIC_SDS_PHY_T *phy;

sys/dev/isci/scil/scic_sds_controller.c

2361

phy = &this_controller->phy_table[index];

sys/dev/isci/scil/scic_sds_controller.c

2362

scic_sds_phy_event_handler(phy, completion_entry);

sys/dev/isci/scil/scic_sds_controller.c

3787

SCIC_SDS_PHY_T * phy;

sys/dev/isci/scil/scic_sds_controller.c

3827

phy = &this_controller->phy_table[index];

sys/dev/isci/scil/scic_sds_controller.c

3828

scic_sds_phy_release_resource(this_controller, phy);

sys/dev/isci/scil/scic_sds_controller.c

5705

SCIC_SDS_PHY_T *phy

sys/dev/isci/scil/scic_sds_controller.c

5711

this_controller, &this_controller->port_agent, port, phy

sys/dev/isci/scil/scic_sds_controller.c

5734

SCIC_SDS_PHY_T *phy

sys/dev/isci/scil/scic_sds_controller.c

5738

this_controller, &this_controller->port_agent, port, phy

sys/dev/isci/scil/scic_sds_controller.c

6061

SCIC_SDS_PHY_T *phy

sys/dev/isci/scil/scic_sds_controller.c

6065

this_controller, &this_controller->port_agent, port, phy

sys/dev/isci/scil/scic_sds_controller.c

6085

SCIC_SDS_PHY_T *phy

sys/dev/isci/scil/scic_sds_controller.c

6089

this_controller, &this_controller->port_agent, port, phy

sys/dev/isci/scil/scic_sds_controller.h

428

struct SCIC_SDS_PHY *phy

sys/dev/isci/scil/scic_sds_controller.h

589

#define scic_sds_controller_set_invalid_phy(controller, phy) \

sys/dev/isci/scil/scic_sds_controller.h

590

((controller)->invalid_phy_mask |= (1 << (phy)->phy_index))

sys/dev/isci/scil/scic_sds_controller.h

597

#define scic_sds_controller_clear_invalid_phy(controller, phy) \

sys/dev/isci/scil/scic_sds_controller.h

598

((controller)->invalid_phy_mask &= ~(1 << (phy)->phy_index))

sys/dev/isci/scil/scic_sds_phy.c

1103

SCI_PHY_HANDLE_T phy,

sys/dev/isci/scil/scic_sds_phy.c

1110

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1119

if (phy == SCI_INVALID_HANDLE)

sys/dev/isci/scil/scic_sds_phy.c

1159

SCI_PHY_HANDLE_T phy,

sys/dev/isci/scil/scic_sds_phy.c

1164

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1193

SCI_PHY_HANDLE_T phy,

sys/dev/isci/scil/scic_sds_phy.c

1198

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1229

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_sds_phy.c

1233

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1254

SCI_PHY_HANDLE_T phy,

sys/dev/isci/scil/scic_sds_phy.c

1260

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1341

SCI_PHY_HANDLE_T phy,

sys/dev/isci/scil/scic_sds_phy.c

1348

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1424

SCI_PHY_HANDLE_T phy,

sys/dev/isci/scil/scic_sds_phy.c

1431

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1504

SCI_PHY_HANDLE_T phy,

sys/dev/isci/scil/scic_sds_phy.c

1510

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1582

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_sds_phy.c

1586

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1599

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_sds_phy.c

1603

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1634

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_phy.c

1638

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1663

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_phy.c

1667

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1691

SCI_BASE_PHY_T * phy

sys/dev/isci/scil/scic_sds_phy.c

1695

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1719

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_phy.c

1723

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1839

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_phy.c

1843

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1880

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_phy.c

1884

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1913

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_phy.c

1917

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

1946

SCI_BASE_PHY_T * phy

sys/dev/isci/scil/scic_sds_phy.c

1950

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

2632

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_phy.c

2636

this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_phy.c

2643

&phy->state_machine,

sys/dev/isci/scil/scic_sds_phy.c

3555

#define scic_sds_phy_set_starting_substate_handlers(phy, state_id) \

sys/dev/isci/scil/scic_sds_phy.c

3557

(phy), \

sys/dev/isci/scil/scic_sds_phy.h

345

#define scic_sds_phy_get_index(phy) \

sys/dev/isci/scil/scic_sds_phy.h

346

((phy)->phy_index)

sys/dev/isci/scil/scic_sds_phy.h

351

#define scic_sds_phy_get_controller(phy) \

sys/dev/isci/scil/scic_sds_phy.h

352

(scic_sds_port_get_controller((phy)->owning_port))

sys/dev/isci/scil/scic_sds_phy.h

357

#define scic_sds_phy_get_base_state_machine(phy) \

sys/dev/isci/scil/scic_sds_phy.h

358

(&(phy)->parent.state_machine)

sys/dev/isci/scil/scic_sds_phy.h

364

#define scic_sds_phy_get_starting_substate_machine(phy) \

sys/dev/isci/scil/scic_sds_phy.h

365

(&(phy)->starting_substate_machine)

sys/dev/isci/scil/scic_sds_phy.h

370

#define scic_sds_phy_set_state_handlers(phy, handlers) \

sys/dev/isci/scil/scic_sds_phy.h

371

((phy)->state_handlers = (handlers))

sys/dev/isci/scil/scic_sds_phy.h

376

#define scic_sds_phy_set_base_state_handlers(phy, state_id) \

sys/dev/isci/scil/scic_sds_phy.h

378

(phy), \

sys/dev/isci/scil/scic_sds_phy.h

386

#define scic_sds_phy_is_ready(phy) \

sys/dev/isci/scil/scic_sds_phy.h

390

scic_sds_phy_get_base_state_machine(phy) \

sys/dev/isci/scil/scic_sds_phy.h

489

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_phy.h

493

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_phy.h

497

SCI_BASE_PHY_T * phy

sys/dev/isci/scil/scic_sds_phy.h

501

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_phy.h

505

SCIC_SDS_PHY_T *phy,

sys/dev/isci/scil/scic_sds_phy.h

510

SCIC_SDS_PHY_T *phy,

sys/dev/isci/scil/scic_sds_phy.h

515

SCIC_SDS_PHY_T *phy

sys/dev/isci/scil/scic_sds_phy.h

520

struct SCIC_SDS_PHY * phy

sys/dev/isci/scil/scic_sds_phy_registers.h

102

#define SCU_TLCR_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

103

scu_transport_layer_read(phy, control)

sys/dev/isci/scil/scic_sds_phy_registers.h

108

#define SCU_TLCR_WRITE(phy, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

109

scu_transport_layer_write(phy, control, value)

sys/dev/isci/scil/scic_sds_phy_registers.h

114

#define SCU_TLADTR_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

115

scu_transport_layer_read(phy, address_translation)

sys/dev/isci/scil/scic_sds_phy_registers.h

120

#define SCU_TLADTR_WRITE(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

121

scu_transport_layer_write(phy, address_translation, value)

sys/dev/isci/scil/scic_sds_phy_registers.h

126

#define SCU_STPTLDARNI_WRITE(phy, index) \

sys/dev/isci/scil/scic_sds_phy_registers.h

127

scu_transport_layer_write(phy, stp_rni, index)

sys/dev/isci/scil/scic_sds_phy_registers.h

132

#define SCU_STPTLDARNI_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

133

scu_transport_layer_read(phy, stp_rni)

sys/dev/isci/scil/scic_sds_phy_registers.h

143

#define scu_link_layer_register_read(phy, reg) \

sys/dev/isci/scil/scic_sds_phy_registers.h

145

scic_sds_phy_get_controller(phy), \

sys/dev/isci/scil/scic_sds_phy_registers.h

146

(phy)->link_layer_registers->reg \

sys/dev/isci/scil/scic_sds_phy_registers.h

153

#define scu_link_layer_register_write(phy, reg, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

155

scic_sds_phy_get_controller(phy), \

sys/dev/isci/scil/scic_sds_phy_registers.h

156

(phy)->link_layer_registers->reg, \

sys/dev/isci/scil/scic_sds_phy_registers.h

165

#define SCU_SAS_TIPID_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

166

scu_link_layer_register_read(phy, identify_frame_phy_id)

sys/dev/isci/scil/scic_sds_phy_registers.h

169

#define SCU_SAS_TIPID_WRITE(phy, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

170

scu_link_layer_register_write(phy, identify_frame_phy_id, value)

sys/dev/isci/scil/scic_sds_phy_registers.h

173

#define SCU_SAS_TIID_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

174

scu_link_layer_register_read(phy, transmit_identification)

sys/dev/isci/scil/scic_sds_phy_registers.h

177

#define SCU_SAS_TIID_WRITE(phy, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

178

scu_link_layer_register_write(phy, transmit_identification, value)

sys/dev/isci/scil/scic_sds_phy_registers.h

181

#define SCU_SAS_TIDNH_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

182

scu_link_layer_register_read(phy, sas_device_name_high)

sys/dev/isci/scil/scic_sds_phy_registers.h

185

#define SCU_SAS_TIDNH_WRITE(phy, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

186

scu_link_layer_register_write(phy, sas_device_name_high, value)

sys/dev/isci/scil/scic_sds_phy_registers.h

189

#define SCU_SAS_TIDNL_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

190

scu_link_layer_register_read(phy, sas_device_name_low)

sys/dev/isci/scil/scic_sds_phy_registers.h

193

#define SCU_SAS_TIDNL_WRITE(phy, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

194

scu_link_layer_register_write(phy, sas_device_name_low, value)

sys/dev/isci/scil/scic_sds_phy_registers.h

197

#define SCU_SAS_TISSAH_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

198

scu_link_layer_register_read(phy, source_sas_address_high)

sys/dev/isci/scil/scic_sds_phy_registers.h

201

#define SCU_SAS_TISSAH_WRITE(phy, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

202

scu_link_layer_register_write(phy, source_sas_address_high, value)

sys/dev/isci/scil/scic_sds_phy_registers.h

205

#define SCU_SAS_TISSAL_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

206

scu_link_layer_register_read(phy, source_sas_address_low)

sys/dev/isci/scil/scic_sds_phy_registers.h

209

#define SCU_SAS_TISSAL_WRITE(phy, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

210

scu_link_layer_register_write(phy, source_sas_address_low, value)

sys/dev/isci/scil/scic_sds_phy_registers.h

213

#define SCU_SAS_PCFG_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

214

scu_link_layer_register_read(phy, phy_configuration);

sys/dev/isci/scil/scic_sds_phy_registers.h

217

#define SCU_SAS_PCFG_WRITE(phy, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

218

scu_link_layer_register_write(phy, phy_configuration, value)

sys/dev/isci/scil/scic_sds_phy_registers.h

221

#define SCU_SAS_ENSPINUP_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

222

scu_link_layer_register_read(phy, notify_enable_spinup_control)

sys/dev/isci/scil/scic_sds_phy_registers.h

225

#define SCU_SAS_ENSPINUP_WRITE(phy, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

226

scu_link_layer_register_write(phy, notify_enable_spinup_control, value)

sys/dev/isci/scil/scic_sds_phy_registers.h

229

#define SCU_SAS_CLKSM_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

230

scu_link_layer_register_read(phy, clock_skew_management)

sys/dev/isci/scil/scic_sds_phy_registers.h

233

#define SCU_SAS_CLKSM_WRITE(phy, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

234

scu_link_layer_register_write(phy, clock_skew_management, value)

sys/dev/isci/scil/scic_sds_phy_registers.h

237

#define SCU_SAS_PHYCAP_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

238

scu_link_layer_register_read(phy, phy_capabilities)

sys/dev/isci/scil/scic_sds_phy_registers.h

241

#define SCU_SAS_PHYCAP_WRITE(phy, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

242

scu_link_layer_register_write(phy, phy_capabilities, value)

sys/dev/isci/scil/scic_sds_phy_registers.h

245

#define SCU_SAS_RECPHYCAP_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

246

scu_link_layer_register_read(phy, receive_phycap)

sys/dev/isci/scil/scic_sds_phy_registers.h

249

#define SCU_SAS_LLCTL_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

250

scu_link_layer_register_read(phy, link_layer_control);

sys/dev/isci/scil/scic_sds_phy_registers.h

253

#define SCU_SAS_LLCTL_WRITE(phy, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

254

scu_link_layer_register_write(phy, link_layer_control, value);

sys/dev/isci/scil/scic_sds_phy_registers.h

257

#define SCU_SAS_LLSTA_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

258

scu_link_layer_register_read(phy, link_layer_status);

sys/dev/isci/scil/scic_sds_phy_registers.h

260

#define SCU_SAS_ECENCR_READ(phy) \

sys/dev/isci/scil/scic_sds_phy_registers.h

261

scu_link_layer_register_read(phy, error_counter_event_notification_control)

sys/dev/isci/scil/scic_sds_phy_registers.h

263

#define SCU_SAS_ECENCR_WRITE(phy, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

264

scu_link_layer_register_write(phy, error_counter_event_notification_control, value)

sys/dev/isci/scil/scic_sds_phy_registers.h

78

#define scu_transport_layer_read(phy, reg) \

sys/dev/isci/scil/scic_sds_phy_registers.h

80

scic_sds_phy_get_controller(phy), \

sys/dev/isci/scil/scic_sds_phy_registers.h

81

(phy)->transport_layer_registers->reg \

sys/dev/isci/scil/scic_sds_phy_registers.h

88

#define scu_transport_layer_write(phy, reg, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

90

scic_sds_phy_get_controller(phy), \

sys/dev/isci/scil/scic_sds_phy_registers.h

91

(phy)->transport_layer_registers->reg, \

sys/dev/isci/scil/scic_sds_port.c

1467

SCIC_SDS_PHY_T * phy = NULL;

sys/dev/isci/scil/scic_sds_port.c

1473

phy = this_port->phy_table[index];

sys/dev/isci/scil/scic_sds_port.c

1475

(phy != NULL)

sys/dev/isci/scil/scic_sds_port.c

1476

&& (scic_sds_port_active_phy(this_port, phy) == TRUE)

sys/dev/isci/scil/scic_sds_port.c

1477

&& (phy->max_negotiated_speed < max_allowed_speed)

sys/dev/isci/scil/scic_sds_port.c

1479

max_allowed_speed = phy->max_negotiated_speed;

sys/dev/isci/scil/scic_sds_port.c

1517

SCIC_SDS_PHY_T * phy;

sys/dev/isci/scil/scic_sds_port.c

1524

phy = this_port->phy_table[index];

sys/dev/isci/scil/scic_sds_port.c

1525

if ( phy != NULL)

sys/dev/isci/scil/scic_sds_port.c

1527

register_value = SCU_SAS_LLCTL_READ(phy);

sys/dev/isci/scil/scic_sds_port.c

1530

SCU_SAS_LLCTL_WRITE(phy, register_value);

sys/dev/isci/scil/scic_sds_port.c

1690

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.c

1697

port, phy,

sys/dev/isci/scil/scic_sds_port.c

1717

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.c

1724

port, phy,

sys/dev/isci/scil/scic_sds_port.c

1808

SCIC_SDS_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.c

1815

this_port, phy,

sys/dev/isci/scil/scic_sds_port.c

1833

SCIC_SDS_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.c

1840

this_port, phy,

sys/dev/isci/scil/scic_sds_port.c

2134

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.c

2138

SCIC_SDS_PHY_T * this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_port.c

2183

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.c

2187

SCIC_SDS_PHY_T *this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_port.c

2285

SCIC_SDS_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.c

2299

scic_sds_port_general_link_up_handler(this_port, phy, FALSE, TRUE);

sys/dev/isci/scil/scic_sds_port.c

2315

SCIC_SDS_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.c

2320

scic_sds_port_deactivate_phy(this_port, phy, FALSE);

sys/dev/isci/scil/scic_sds_port.c

274

SCIC_SDS_PHY_T *phy;

sys/dev/isci/scil/scic_sds_port.c

280

phy = this_port->phy_table[index];

sys/dev/isci/scil/scic_sds_port.c

282

(phy != NULL)

sys/dev/isci/scil/scic_sds_port.c

283

&& scic_sds_port_active_phy(this_port, phy)

sys/dev/isci/scil/scic_sds_port.c

286

return phy;

sys/dev/isci/scil/scic_sds_port.c

2904

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.c

2908

SCIC_SDS_PHY_T * this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_port.c

2931

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.c

2935

SCIC_SDS_PHY_T * this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_port.c

310

SCIC_SDS_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.c

317

(port->phy_table[phy->phy_index] == SCI_INVALID_HANDLE)

sys/dev/isci/scil/scic_sds_port.c

318

&& (scic_sds_phy_get_port(phy) == SCI_INVALID_HANDLE)

sys/dev/isci/scil/scic_sds_port.c

3180

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.c

3184

SCIC_SDS_PHY_T * this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_port.c

319

&& scic_sds_port_is_valid_phy_assignment(port, phy->phy_index)

sys/dev/isci/scil/scic_sds_port.c

3217

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.c

3221

SCIC_SDS_PHY_T * this_phy = (SCIC_SDS_PHY_T *)phy;

sys/dev/isci/scil/scic_sds_port.c

325

port->phy_table[phy->phy_index] = phy;

sys/dev/isci/scil/scic_sds_port.c

326

scic_sds_phy_set_port(phy, port);

sys/dev/isci/scil/scic_sds_port.c

347

SCIC_SDS_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.c

352

(port->phy_table[phy->phy_index] == phy)

sys/dev/isci/scil/scic_sds_port.c

353

&& (scic_sds_phy_get_port(phy) == port)

sys/dev/isci/scil/scic_sds_port.c

358

phy,

sys/dev/isci/scil/scic_sds_port.c

362

port->phy_table[phy->phy_index] = SCI_INVALID_HANDLE;

sys/dev/isci/scil/scic_sds_port.c

511

SCIC_SDS_PHY_T *phy;

sys/dev/isci/scil/scic_sds_port.c

522

phy = scic_sds_port_get_a_connected_phy(this_port);

sys/dev/isci/scil/scic_sds_port.c

523

if (phy != NULL)

sys/dev/isci/scil/scic_sds_port.c

525

scic_sds_phy_get_attached_phy_protocols(phy, &protocols);

sys/dev/isci/scil/scic_sds_port.c

529

scic_sds_phy_get_attached_sas_address(phy, sas_address);

sys/dev/isci/scil/scic_sds_port.c

533

scic_sds_phy_get_sas_address(phy, sas_address);

sys/dev/isci/scil/scic_sds_port.c

534

sas_address->low += phy->phy_index;

sys/dev/isci/scil/scic_sds_port.c

568

SCIC_SDS_PHY_T *phy;

sys/dev/isci/scil/scic_sds_port.c

579

phy = scic_sds_port_get_a_connected_phy(this_port);

sys/dev/isci/scil/scic_sds_port.c

580

if (phy != NULL)

sys/dev/isci/scil/scic_sds_port.c

581

scic_sds_phy_get_attached_phy_protocols(phy, protocols);

sys/dev/isci/scil/scic_sds_port.c

906

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_sds_port.c

917

handle, phy

sys/dev/isci/scil/scic_sds_port.c

935

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_sds_port.c

946

handle, phy

sys/dev/isci/scil/scic_sds_port.h

329

#define scic_sds_port_write_phy_assignment(port, phy) \

sys/dev/isci/scil/scic_sds_port.h

332

(phy)->phy_index, \

sys/dev/isci/scil/scic_sds_port.h

339

#define scic_sds_port_read_phy_assignment(port, phy) \

sys/dev/isci/scil/scic_sds_port.h

342

(phy)->phy_index \

sys/dev/isci/scil/scic_sds_port.h

345

#define scic_sds_port_active_phy(port, phy) \

sys/dev/isci/scil/scic_sds_port.h

346

(((port)->active_phy_mask & (1 << (phy)->phy_index)) != 0)

sys/dev/isci/scil/scic_sds_port.h

400

struct SCIC_SDS_PHY *phy,

sys/dev/isci/scil/scic_sds_port.h

407

struct SCIC_SDS_PHY *phy,

sys/dev/isci/scil/scic_sds_port.h

417

struct SCIC_SDS_PHY *phy

sys/dev/isci/scil/scic_sds_port.h

429

struct SCIC_SDS_PHY *phy

sys/dev/isci/scil/scic_sds_port.h

434

struct SCIC_SDS_PHY *phy

sys/dev/isci/scil/scic_sds_port.h

439

struct SCIC_SDS_PHY *phy

sys/dev/isci/scil/scic_sds_port.h

489

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.h

494

SCI_BASE_PHY_T *phy

sys/dev/isci/scil/scic_sds_port.h

509

struct SCIC_SDS_PHY *phy

sys/dev/isci/scil/scic_sds_port.h

514

struct SCIC_SDS_PHY *phy

sys/dev/isci/scil/scic_sds_port.h

569

struct SCIC_SDS_PHY *phy

sys/dev/isci/scil/scic_sds_port.h

574

struct SCIC_SDS_PHY *phy

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

143

SCIC_SDS_PHY_T * phy

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

157

controller, phy

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

163

scic_sds_phy_get_sas_address(phy, &phy_sas_address);

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

164

scic_sds_phy_get_attached_sas_address(phy, &phy_attached_device_address);

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

480

SCIC_SDS_PHY_T * phy

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

487

controller, port_agent, port, phy

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

495

port_agent->phy_ready_mask |= (1 << scic_sds_phy_get_index(phy));

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

497

scic_sds_port_link_up(port, phy);

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

499

if ((port->active_phy_mask & (1 << scic_sds_phy_get_index(phy))) != 0)

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

501

port_agent->phy_configured_mask |= (1 << scic_sds_phy_get_index(phy));

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

529

SCIC_SDS_PHY_T * phy

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

536

controller, port_agent, port, phy

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

545

port_agent->phy_ready_mask &= ~(1 << scic_sds_phy_get_index(phy));

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

546

port_agent->phy_configured_mask &= ~(1 << scic_sds_phy_get_index(phy));

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

566

scic_sds_port_link_down(port, phy);

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

649

SCIC_SDS_PHY_T * phy,

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

657

controller, port_agent, phy, timeout

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

683

SCIC_SDS_PHY_T * phy,

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

697

controller, port_agent, phy, start_timer

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

700

port = scic_sds_port_configuration_agent_find_port(controller, phy);

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

704

if (scic_sds_port_is_valid_phy_assignment(port, phy->phy_index))

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

717

port_index = port_agent->phy_valid_port_range[phy->phy_index].min_index;

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

718

port_index <= port_agent->phy_valid_port_range[phy->phy_index].max_index;

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

727

if (scic_sds_port_is_valid_phy_assignment(port, phy->phy_index))

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

732

if (port->active_phy_mask > (1 << phy->phy_index))

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

741

if (port->physical_port_index == phy->phy_index)

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

790

status = scic_sds_port_add_phy(port, phy);

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

794

port_agent->phy_configured_mask |= (1 << phy->phy_index);

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

800

controller, port_agent, phy, SCIC_SDS_APC_WAIT_LINK_UP_NOTIFICATION

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

828

SCIC_SDS_PHY_T * phy

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

835

controller, port_agent, port, phy

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

841

port_agent->phy_ready_mask |= (1 << scic_sds_phy_get_index(phy));

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

844

controller, port_agent, phy, SCIC_SDS_APC_WAIT_LINK_UP_NOTIFICATION

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

858

port_agent->phy_ready_mask |= (1 << scic_sds_phy_get_index(phy));

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

859

scic_sds_port_link_up(port, phy);

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

886

SCIC_SDS_PHY_T * phy

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

893

controller, port_agent, port, phy

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

896

port_agent->phy_ready_mask &= ~(1 << scic_sds_phy_get_index(phy));

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

900

if (port_agent->phy_configured_mask & (1 << phy->phy_index))

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

904

status = scic_sds_port_remove_phy(port, phy);

sys/dev/isci/scil/scic_sds_port_configuration_agent.c

908

port_agent->phy_configured_mask &= ~(1 << phy->phy_index);

sys/dev/isci/scil/scic_sds_remote_device.c

905

SCIC_SDS_PHY_T * phy;

sys/dev/isci/scil/scic_sds_remote_device.c

908

phy = scic_sds_port_get_a_connected_phy(this_device->owning_port);

sys/dev/isci/scil/scic_sds_remote_device.c

909

scic_sata_phy_get_properties(phy, &properties);

sys/dev/isci/scil/scic_user_callback.h

1002

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_user_callback.h

1023

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_user_callback.h

897

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_user_callback.h

918

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_user_callback.h

939

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_user_callback.h

960

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scic_user_callback.h

981

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scif_sas_domain.c

401

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scif_sas_domain.c

414

controller, port, phy

sys/dev/isci/scil/scif_sas_domain.c

439

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scif_sas_domain.c

446

controller, port, phy

sys/dev/isci/scil/scif_sas_domain.c

455

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scif_sas_domain.c

462

controller, port, phy

sys/dev/isci/scil/scif_sas_domain.c

471

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scif_sas_domain.c

478

controller, port, phy

sys/dev/isci/scil/scif_sas_domain.c

487

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scif_sas_domain.c

497

controller, port, phy

sys/dev/isci/scil/scif_sas_domain.c

508

SCI_PHY_HANDLE_T phy

sys/dev/isci/scil/scif_sas_domain.c

518

controller, port, phy

sys/dev/iwm/if_iwm_binding.c

170

cmd.phy = htole32(IWM_FW_CMD_ID_AND_COLOR(phyctxt->id, phyctxt->color));

sys/dev/iwm/if_iwmreg.h

2966

uint32_t phy;

sys/dev/iwm/if_iwmreg.h

2984

uint32_t phy;

sys/dev/iwn/if_iwn.c

5863

struct iwn4965_rx_phystat *phy = (void *)stat->phybuf;

sys/dev/iwn/if_iwn.c

5869

mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC;

sys/dev/iwn/if_iwn.c

5870

agc = (le16toh(phy->agc) >> 7) & 0x7f;

sys/dev/iwn/if_iwn.c

5874

rssi = MAX(rssi, phy->rssi[0]);

sys/dev/iwn/if_iwn.c

5876

rssi = MAX(rssi, phy->rssi[2]);

sys/dev/iwn/if_iwn.c

5878

rssi = MAX(rssi, phy->rssi[4]);

sys/dev/iwn/if_iwn.c

5882

mask, phy->rssi[0], phy->rssi[2], phy->rssi[4],

sys/dev/iwn/if_iwn.c

5890

struct iwn5000_rx_phystat *phy = (void *)stat->phybuf;

sys/dev/iwn/if_iwn.c

5896

agc = (le32toh(phy->agc) >> 9) & 0x7f;

sys/dev/iwn/if_iwn.c

5898

rssi = MAX(le16toh(phy->rssi[0]) & 0xff,

sys/dev/iwn/if_iwn.c

5899

le16toh(phy->rssi[1]) & 0xff);

sys/dev/iwn/if_iwn.c

5900

rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi);

sys/dev/iwn/if_iwn.c

5904

phy->rssi[0], phy->rssi[1], phy->rssi[2],

sys/dev/iwx/if_iwx.c

5023

cmd.phy = htole32(IWX_FW_CMD_ID_AND_COLOR(phyctxt->id, phyctxt->color));

sys/dev/iwx/if_iwxreg.h

3258

uint32_t phy;

sys/dev/ixgbe/if_ix.c

1063

hw->phy.smart_speed = ixgbe_smart_speed;

sys/dev/ixgbe/if_ix.c

1086

hw->phy.reset_if_overtemp = true;

sys/dev/ixgbe/if_ix.c

1088

hw->phy.reset_if_overtemp = false;

sys/dev/ixgbe/if_ix.c

1405

if (hw->phy.ops.read_i2c_byte == NULL)

sys/dev/ixgbe/if_ix.c

1408

hw->phy.ops.read_i2c_byte(hw, req->offset + i,

sys/dev/ixgbe/if_ix.c

1715

if (hw->phy.multispeed_fiber)

sys/dev/ixgbe/if_ix.c

1721

if (hw->phy.multispeed_fiber)

sys/dev/ixgbe/if_ix.c

1782

if (hw->phy.type == ixgbe_phy_nl)

sys/dev/ixgbe/if_ix.c

1826

autoneg = hw->phy.autoneg_advertised;

sys/dev/ixgbe/if_ix.c

1834

hw->phy.autoneg_advertised == 0) {

sys/dev/ixgbe/if_ix.c

1863

hw->phy.ops.init(hw);

sys/dev/ixgbe/if_ix.c

2876

if (hw->phy.media_type == ixgbe_media_type_backplane)

sys/dev/ixgbe/if_ix.c

3052

retval = hw->phy.ops.check_overtemp(hw);

sys/dev/ixgbe/if_ix.c

3064

retval = hw->phy.ops.check_overtemp(hw);

sys/dev/ixgbe/if_ix.c

3117

if ((hw->phy.type == ixgbe_phy_x550em_ext_t) &&

sys/dev/ixgbe/if_ix.c

3629

hw->phy.ops.enter_lplu) {

sys/dev/ixgbe/if_ix.c

3652

hw->phy.reset_disable = true;

sys/dev/ixgbe/if_ix.c

3654

error = hw->phy.ops.enter_lplu(hw);

sys/dev/ixgbe/if_ix.c

3658

hw->phy.reset_disable = false;

sys/dev/ixgbe/if_ix.c

3948

if (hw->phy.type == ixgbe_phy_none) {

sys/dev/ixgbe/if_ix.c

3949

err = hw->phy.ops.identify(hw);

sys/dev/ixgbe/if_ix.c

4319

if ((hw->phy.type == ixgbe_phy_nl) &&

sys/dev/ixgbe/if_ix.c

4320

(hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {

sys/dev/ixgbe/if_ix.c

4321

s32 ret = hw->phy.ops.identify_sfp(hw);

sys/dev/ixgbe/if_ix.c

4324

ret = hw->phy.ops.reset(hw);

sys/dev/ixgbe/if_ix.c

4373

err = hw->phy.ops.identify_sfp(hw);

sys/dev/ixgbe/if_ix.c

4381

err = hw->phy.ops.reset(hw);

sys/dev/ixgbe/if_ix.c

4413

autoneg = hw->phy.autoneg_advertised;

sys/dev/ixgbe/if_ix.c

4436

error = hw->phy.ops.handle_lasi(hw);

sys/dev/ixgbe/if_ix.c

4740

if (hw->phy.type == ixgbe_phy_x550em_ext_t)

sys/dev/ixgbe/if_ix.c

4937

if ((hw->phy.type == ixgbe_phy_x550em_ext_t) &&

sys/dev/ixgbe/if_ix.c

5140

if (hw->phy.media_type == ixgbe_media_type_backplane)

sys/dev/ixgbe/if_ix.c

5143

if (!((hw->phy.media_type == ixgbe_media_type_copper) ||

sys/dev/ixgbe/if_ix.c

5144

(hw->phy.multispeed_fiber))) {

sys/dev/ixgbe/if_ix.c

5257

if (!(hw->phy.media_type == ixgbe_media_type_copper) &&

sys/dev/ixgbe/if_ix.c

5258

!(hw->phy.multispeed_fiber))

sys/dev/ixgbe/if_ix.c

5538

if (hw->phy.ops.read_reg(hw, IXGBE_PHY_CURRENT_TEMP,

sys/dev/ixgbe/if_ix.c

5574

if (hw->phy.ops.read_reg(hw, IXGBE_PHY_OVERTEMP_STATUS,

sys/dev/ixgbe/if_ix_mdio.c

110

ixgbe_mdio_writereg_c22(device_t dev, int phy, int reg, int data)

sys/dev/ixgbe/if_ix_mdio.c

122

ret = ixgbe_write_mdio_c22(hw, phy, reg, data);

sys/dev/ixgbe/if_ix_mdio.c

78

ixgbe_mdio_readreg_c22(device_t dev, int phy, int reg)

sys/dev/ixgbe/if_ix_mdio.c

91

ret = ixgbe_read_mdio_c22(hw, phy, reg, &val);

sys/dev/ixgbe/if_ix_mdio_hw.c

144

ixgbe_read_mdio_c22(struct ixgbe_hw *hw, u16 phy, u16 reg, u16 *phy_data)

sys/dev/ixgbe/if_ix_mdio_hw.c

146

u32 gssr = hw->phy.phy_semaphore_mask;

sys/dev/ixgbe/if_ix_mdio_hw.c

157

ret = ixgbe_read_mdio_unlocked_c22(hw, phy, reg, phy_data);

sys/dev/ixgbe/if_ix_mdio_hw.c

166

ixgbe_write_mdio_c22(struct ixgbe_hw *hw, u16 phy, u16 reg, u16 data)

sys/dev/ixgbe/if_ix_mdio_hw.c

168

u32 gssr = hw->phy.phy_semaphore_mask;

sys/dev/ixgbe/if_ix_mdio_hw.c

177

ret = ixgbe_write_mdio_unlocked_c22(hw, phy, reg, data);

sys/dev/ixgbe/if_ix_mdio_hw.c

48

ixgbe_read_mdio_unlocked_c22(struct ixgbe_hw *hw, u16 phy, u16 reg, u16 *phy_data)

sys/dev/ixgbe/if_ix_mdio_hw.c

54

(phy << IXGBE_MSCA_PHY_ADDR_SHIFT) |

sys/dev/ixgbe/if_ix_mdio_hw.c

84

ixgbe_write_mdio_unlocked_c22(struct ixgbe_hw *hw, u16 phy, u16 reg, u16 phy_data)

sys/dev/ixgbe/if_ix_mdio_hw.c

93

(phy << IXGBE_MSCA_PHY_ADDR_SHIFT) |

sys/dev/ixgbe/if_ix_mdio_hw.h

30

s32 ixgbe_read_mdio_c22(struct ixgbe_hw *hw, u16 phy, u16 reg, u16 *phy_data);

sys/dev/ixgbe/if_ix_mdio_hw.h

31

s32 ixgbe_write_mdio_c22(struct ixgbe_hw *hw, u16 phy, u16 reg, u16 data);

sys/dev/ixgbe/ixgbe_82598.c

1146

if (hw->phy.type == ixgbe_phy_nl) {

sys/dev/ixgbe/ixgbe_82598.c

1154

hw->phy.ops.write_reg_mdi(hw,

sys/dev/ixgbe/ixgbe_82598.c

1161

hw->phy.ops.read_reg_mdi(hw,

sys/dev/ixgbe/ixgbe_82598.c

1178

hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,

sys/dev/ixgbe/ixgbe_82598.c

122

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/ixgbe/ixgbe_82598.c

1237

hw->phy.ops.identify(hw);

sys/dev/ixgbe/ixgbe_82598.c

1241

switch (hw->phy.type) {

sys/dev/ixgbe/ixgbe_82598.c

1244

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,

sys/dev/ixgbe/ixgbe_82598.c

1284

if (hw->phy.type == ixgbe_phy_nl) {

sys/dev/ixgbe/ixgbe_82598.c

1285

hw->phy.ops.identify_sfp(hw);

sys/dev/ixgbe/ixgbe_82598.c

1287

switch (hw->phy.sfp_type) {

sys/dev/ixgbe/ixgbe_82598.c

131

phy->ops.init = ixgbe_init_phy_ops_82598;

sys/dev/ixgbe/ixgbe_82598.c

164

phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598;

sys/dev/ixgbe/ixgbe_82598.c

165

phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_82598;

sys/dev/ixgbe/ixgbe_82598.c

194

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/ixgbe/ixgbe_82598.c

201

phy->ops.identify(hw);

sys/dev/ixgbe/ixgbe_82598.c

210

switch (hw->phy.type) {

sys/dev/ixgbe/ixgbe_82598.c

212

phy->ops.setup_link = ixgbe_setup_phy_link_tnx;

sys/dev/ixgbe/ixgbe_82598.c

213

phy->ops.check_link = ixgbe_check_phy_link_tnx;

sys/dev/ixgbe/ixgbe_82598.c

214

phy->ops.get_firmware_version =

sys/dev/ixgbe/ixgbe_82598.c

218

phy->ops.reset = ixgbe_reset_phy_nl;

sys/dev/ixgbe/ixgbe_82598.c

221

ret_val = phy->ops.identify_sfp(hw);

sys/dev/ixgbe/ixgbe_82598.c

224

else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {

sys/dev/ixgbe/ixgbe_82598.c

362

switch (hw->phy.type) {

sys/dev/ixgbe/ixgbe_82598.c

615

hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,

sys/dev/ixgbe/ixgbe_82598.c

658

if (hw->phy.type == ixgbe_phy_nl) {

sys/dev/ixgbe/ixgbe_82598.c

659

hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);

sys/dev/ixgbe/ixgbe_82598.c

660

hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);

sys/dev/ixgbe/ixgbe_82598.c

661

hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,

sys/dev/ixgbe/ixgbe_82598.c

673

hw->phy.ops.read_reg(hw, 0xC79F,

sys/dev/ixgbe/ixgbe_82598.c

676

hw->phy.ops.read_reg(hw, 0xC00C,

sys/dev/ixgbe/ixgbe_82598.c

794

status = hw->phy.ops.setup_link_speed(hw, speed,

sys/dev/ixgbe/ixgbe_82598.c

861

if (hw->phy.reset_disable == false) {

sys/dev/ixgbe/ixgbe_82598.c

865

phy_status = hw->phy.ops.init(hw);

sys/dev/ixgbe/ixgbe_82598.c

871

hw->phy.ops.reset(hw);

sys/dev/ixgbe/ixgbe_82599.c

1039

status = hw->phy.ops.setup_link_speed(hw, speed,

sys/dev/ixgbe/ixgbe_82599.c

1077

status = hw->phy.ops.init(hw);

sys/dev/ixgbe/ixgbe_82599.c

1083

if (hw->phy.sfp_setup_needed) {

sys/dev/ixgbe/ixgbe_82599.c

1085

hw->phy.sfp_setup_needed = false;

sys/dev/ixgbe/ixgbe_82599.c

1092

if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)

sys/dev/ixgbe/ixgbe_82599.c

1093

hw->phy.ops.reset(hw);

sys/dev/ixgbe/ixgbe_82599.c

1168

if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||

sys/dev/ixgbe/ixgbe_82599.c

118

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/ixgbe/ixgbe_82599.c

126

hw->phy.qsfp_shared_i2c_bus = true;

sys/dev/ixgbe/ixgbe_82599.c

138

phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599;

sys/dev/ixgbe/ixgbe_82599.c

139

phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599;

sys/dev/ixgbe/ixgbe_82599.c

142

ret_val = phy->ops.identify(hw);

sys/dev/ixgbe/ixgbe_82599.c

148

if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)

sys/dev/ixgbe/ixgbe_82599.c

149

hw->phy.ops.reset = NULL;

sys/dev/ixgbe/ixgbe_82599.c

159

switch (hw->phy.type) {

sys/dev/ixgbe/ixgbe_82599.c

161

phy->ops.setup_link = ixgbe_setup_phy_link_tnx;

sys/dev/ixgbe/ixgbe_82599.c

162

phy->ops.check_link = ixgbe_check_phy_link_tnx;

sys/dev/ixgbe/ixgbe_82599.c

163

phy->ops.get_firmware_version =

sys/dev/ixgbe/ixgbe_82599.c

180

if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {

sys/dev/ixgbe/ixgbe_82599.c

183

hw->phy.ops.reset = NULL;

sys/dev/ixgbe/ixgbe_82599.c

2195

if (hw->phy.type == ixgbe_phy_unknown) {

sys/dev/ixgbe/ixgbe_82599.c

2196

hw->phy.type = ixgbe_phy_none;

sys/dev/ixgbe/ixgbe_82599.c

2201

if (hw->phy.type == ixgbe_phy_sfp_unsupported)

sys/dev/ixgbe/ixgbe_82599.c

2225

hw->phy.ops.identify(hw);

sys/dev/ixgbe/ixgbe_82599.c

2227

switch (hw->phy.type) {

sys/dev/ixgbe/ixgbe_82599.c

2230

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,

sys/dev/ixgbe/ixgbe_82599.c

2344

if (hw->phy.media_type != ixgbe_media_type_fiber) {

sys/dev/ixgbe/ixgbe_82599.c

2569

if (hw->phy.qsfp_shared_i2c_bus == true) {

sys/dev/ixgbe/ixgbe_82599.c

2597

if (hw->phy.qsfp_shared_i2c_bus == true) {

sys/dev/ixgbe/ixgbe_82599.c

2627

if (hw->phy.qsfp_shared_i2c_bus == true) {

sys/dev/ixgbe/ixgbe_82599.c

2655

if (hw->phy.qsfp_shared_i2c_bus == true) {

sys/dev/ixgbe/ixgbe_82599.c

324

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/ixgbe/ixgbe_82599.c

335

phy->ops.identify = ixgbe_identify_phy_82599;

sys/dev/ixgbe/ixgbe_82599.c

336

phy->ops.init = ixgbe_init_phy_ops_82599;

sys/dev/ixgbe/ixgbe_82599.c

433

if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||

sys/dev/ixgbe/ixgbe_82599.c

434

hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||

sys/dev/ixgbe/ixgbe_82599.c

435

hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||

sys/dev/ixgbe/ixgbe_82599.c

436

hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||

sys/dev/ixgbe/ixgbe_82599.c

437

hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||

sys/dev/ixgbe/ixgbe_82599.c

438

hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||

sys/dev/ixgbe/ixgbe_82599.c

439

hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 ||

sys/dev/ixgbe/ixgbe_82599.c

440

hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1) {

sys/dev/ixgbe/ixgbe_82599.c

446

if (hw->phy.sfp_type == ixgbe_sfp_type_da_cu_core0 ||

sys/dev/ixgbe/ixgbe_82599.c

447

hw->phy.sfp_type == ixgbe_sfp_type_da_cu_core1) {

sys/dev/ixgbe/ixgbe_82599.c

451

if (hw->phy.multispeed_fiber)

sys/dev/ixgbe/ixgbe_82599.c

522

if (hw->phy.multispeed_fiber) {

sys/dev/ixgbe/ixgbe_82599.c

529

if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)

sys/dev/ixgbe/ixgbe_82599.c

552

switch (hw->phy.type) {

sys/dev/ixgbe/ixgbe_82599.c

593

hw->phy.multispeed_fiber = true;

sys/dev/ixgbe/ixgbe_82599.c

813

hw->phy.autoneg_advertised = 0;

sys/dev/ixgbe/ixgbe_82599.c

816

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;

sys/dev/ixgbe/ixgbe_82599.c

819

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;

sys/dev/ixgbe/ixgbe_82599.c

822

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;

sys/dev/ixgbe/ixgbe_82599.c

832

hw->phy.smart_speed_active = false;

sys/dev/ixgbe/ixgbe_82599.c

85

if (hw->phy.multispeed_fiber) {

sys/dev/ixgbe/ixgbe_82599.c

868

hw->phy.smart_speed_active = true;

sys/dev/ixgbe/ixgbe_82599.c

893

hw->phy.smart_speed_active = false;

sys/dev/ixgbe/ixgbe_82599.c

96

(hw->phy.smart_speed == ixgbe_smart_speed_auto ||

sys/dev/ixgbe/ixgbe_82599.c

960

(hw->phy.smart_speed_active == false))

sys/dev/ixgbe/ixgbe_82599.c

97

hw->phy.smart_speed == ixgbe_smart_speed_on) &&

sys/dev/ixgbe/ixgbe_82599.c

980

if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)

sys/dev/ixgbe/ixgbe_api.c

1412

return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw),

sys/dev/ixgbe/ixgbe_api.c

1429

return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw),

sys/dev/ixgbe/ixgbe_api.c

1549

return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,

sys/dev/ixgbe/ixgbe_api.c

1565

return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked,

sys/dev/ixgbe/ixgbe_api.c

1613

return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,

sys/dev/ixgbe/ixgbe_api.c

1630

return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked,

sys/dev/ixgbe/ixgbe_api.c

1676

return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,

sys/dev/ixgbe/ixgbe_api.c

1691

return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,

sys/dev/ixgbe/ixgbe_api.c

523

if (hw->phy.type == ixgbe_phy_unknown) {

sys/dev/ixgbe/ixgbe_api.c

524

status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw),

sys/dev/ixgbe/ixgbe_api.c

539

if (hw->phy.type == ixgbe_phy_unknown) {

sys/dev/ixgbe/ixgbe_api.c

545

status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),

sys/dev/ixgbe/ixgbe_api.c

560

status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,

sys/dev/ixgbe/ixgbe_api.c

578

if (hw->phy.id == 0)

sys/dev/ixgbe/ixgbe_api.c

581

return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,

sys/dev/ixgbe/ixgbe_api.c

597

if (hw->phy.id == 0)

sys/dev/ixgbe/ixgbe_api.c

600

return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,

sys/dev/ixgbe/ixgbe_api.c

612

return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),

sys/dev/ixgbe/ixgbe_api.c

626

return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw),

sys/dev/ixgbe/ixgbe_api.c

642

return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,

sys/dev/ixgbe/ixgbe_api.c

657

return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,

sys/dev/ixgbe/ixgbe_api.c

669

return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on),

sys/dev/ixgbe/ixgbe_common.c

171

switch (hw->phy.media_type) {

sys/dev/ixgbe/ixgbe_common.c

268

switch (hw->phy.media_type) {

sys/dev/ixgbe/ixgbe_common.c

284

hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,

sys/dev/ixgbe/ixgbe_common.c

305

if (hw->phy.media_type == ixgbe_media_type_backplane)

sys/dev/ixgbe/ixgbe_common.c

308

else if (hw->phy.media_type == ixgbe_media_type_copper)

sys/dev/ixgbe/ixgbe_common.c

3092

hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,

sys/dev/ixgbe/ixgbe_common.c

3095

hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,

sys/dev/ixgbe/ixgbe_common.c

3139

switch (hw->phy.media_type) {

sys/dev/ixgbe/ixgbe_common.c

318

if (hw->phy.media_type == ixgbe_media_type_backplane) {

sys/dev/ixgbe/ixgbe_common.c

321

} else if (hw->phy.media_type == ixgbe_media_type_copper) {

sys/dev/ixgbe/ixgbe_common.c

339

if (hw->phy.media_type == ixgbe_media_type_backplane)

sys/dev/ixgbe/ixgbe_common.c

342

else if (hw->phy.media_type == ixgbe_media_type_copper)

sys/dev/ixgbe/ixgbe_common.c

374

if (hw->phy.media_type == ixgbe_media_type_backplane) {

sys/dev/ixgbe/ixgbe_common.c

379

} else if ((hw->phy.media_type == ixgbe_media_type_copper) &&

sys/dev/ixgbe/ixgbe_common.c

381

hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,

sys/dev/ixgbe/ixgbe_common.c

408

hw->phy.media_type = hw->mac.ops.get_media_type(hw);

sys/dev/ixgbe/ixgbe_common.c

5015

status = hw->phy.ops.read_i2c_byte(hw,

sys/dev/ixgbe/ixgbe_common.c

5089

hw->phy.ops.write_i2c_byte(hw,

sys/dev/ixgbe/ixgbe_common.c

5702

switch (hw->phy.media_type) {

sys/dev/ixgbe/ixgbe_common.c

5753

switch (hw->phy.media_type) {

sys/dev/ixgbe/ixgbe_common.c

5802

hw->phy.autoneg_advertised = 0;

sys/dev/ixgbe/ixgbe_common.c

5805

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;

sys/dev/ixgbe/ixgbe_common.c

5808

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;

sys/dev/ixgbe/ixgbe_common.c

5840

status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,

sys/dev/ixgbe/ixgbe_common.c

5850

status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,

sys/dev/ixgbe/ixgbe_common.c

5859

status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,

sys/dev/ixgbe/ixgbe_common.c

5869

status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,

sys/dev/ixgbe/ixgbe_common.c

624

if (hw->phy.id == 0)

sys/dev/ixgbe/ixgbe_common.c

626

hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,

sys/dev/ixgbe/ixgbe_common.c

628

hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,

sys/dev/ixgbe/ixgbe_common.c

630

hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,

sys/dev/ixgbe/ixgbe_common.c

632

hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,

sys/dev/ixgbe/ixgbe_e610.c

1267

hw->phy.phy_type_low = IXGBE_LE64_TO_CPU(pcaps->phy_type_low);

sys/dev/ixgbe/ixgbe_e610.c

1268

hw->phy.phy_type_high = IXGBE_LE64_TO_CPU(pcaps->phy_type_high);

sys/dev/ixgbe/ixgbe_e610.c

1387

hw->phy.curr_user_phy_cfg = *cfg;

sys/dev/ixgbe/ixgbe_e610.c

4357

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/ixgbe/ixgbe_e610.c

4388

phy->ops.init = ixgbe_init_phy_ops_E610;

sys/dev/ixgbe/ixgbe_e610.c

4389

phy->ops.identify = ixgbe_identify_phy_E610;

sys/dev/ixgbe/ixgbe_e610.c

4392

phy->eee_speeds_supported = IXGBE_LINK_SPEED_2_5GB_FULL;

sys/dev/ixgbe/ixgbe_e610.c

4394

phy->eee_speeds_supported = IXGBE_LINK_SPEED_2_5GB_FULL |

sys/dev/ixgbe/ixgbe_e610.c

4398

phy->eee_speeds_advertised = phy->eee_speeds_supported;

sys/dev/ixgbe/ixgbe_e610.c

4428

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/ixgbe/ixgbe_e610.c

4442

status = hw->phy.ops.init(hw);

sys/dev/ixgbe/ixgbe_e610.c

4595

hw->phy.media_type = ixgbe_get_media_type_from_phy_type(hw);

sys/dev/ixgbe/ixgbe_e610.c

4597

return hw->phy.media_type;

sys/dev/ixgbe/ixgbe_e610.c

4665

return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);

sys/dev/ixgbe/ixgbe_e610.c

4765

*speed = hw->phy.speeds_supported;

sys/dev/ixgbe/ixgbe_e610.c

5027

if (hw->phy.eee_speeds_advertised & IXGBE_LINK_SPEED_100_FULL)

sys/dev/ixgbe/ixgbe_e610.c

5029

if (hw->phy.eee_speeds_advertised & IXGBE_LINK_SPEED_1GB_FULL)

sys/dev/ixgbe/ixgbe_e610.c

5031

if (hw->phy.eee_speeds_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)

sys/dev/ixgbe/ixgbe_e610.c

5033

if (hw->phy.eee_speeds_advertised & IXGBE_LINK_SPEED_5GB_FULL)

sys/dev/ixgbe/ixgbe_e610.c

5035

if (hw->phy.eee_speeds_advertised & IXGBE_LINK_SPEED_10GB_FULL)

sys/dev/ixgbe/ixgbe_e610.c

5107

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/ixgbe/ixgbe_e610.c

5110

phy->ops.identify_sfp = ixgbe_identify_module_E610;

sys/dev/ixgbe/ixgbe_e610.c

5111

phy->ops.read_reg = NULL; /* PHY reg access is not required */

sys/dev/ixgbe/ixgbe_e610.c

5112

phy->ops.write_reg = NULL;

sys/dev/ixgbe/ixgbe_e610.c

5113

phy->ops.read_reg_mdi = NULL;

sys/dev/ixgbe/ixgbe_e610.c

5114

phy->ops.write_reg_mdi = NULL;

sys/dev/ixgbe/ixgbe_e610.c

5115

phy->ops.setup_link = ixgbe_setup_phy_link_E610;

sys/dev/ixgbe/ixgbe_e610.c

5116

phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_E610;

sys/dev/ixgbe/ixgbe_e610.c

5117

phy->ops.read_i2c_byte = NULL; /* disabled for E610 */

sys/dev/ixgbe/ixgbe_e610.c

5118

phy->ops.write_i2c_byte = NULL; /* disabled for E610 */

sys/dev/ixgbe/ixgbe_e610.c

5119

phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_E610;

sys/dev/ixgbe/ixgbe_e610.c

5120

phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_E610;

sys/dev/ixgbe/ixgbe_e610.c

5121

phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_E610;

sys/dev/ixgbe/ixgbe_e610.c

5122

phy->ops.i2c_bus_clear = NULL; /* do not use generic implementation */

sys/dev/ixgbe/ixgbe_e610.c

5123

phy->ops.check_overtemp = ixgbe_check_overtemp_E610;

sys/dev/ixgbe/ixgbe_e610.c

5125

phy->ops.set_phy_power = ixgbe_set_phy_power_E610;

sys/dev/ixgbe/ixgbe_e610.c

5127

phy->ops.set_phy_power = NULL;

sys/dev/ixgbe/ixgbe_e610.c

5128

phy->ops.enter_lplu = ixgbe_enter_lplu_E610;

sys/dev/ixgbe/ixgbe_e610.c

5129

phy->ops.handle_lasi = NULL; /* no implementation for E610 */

sys/dev/ixgbe/ixgbe_e610.c

5130

phy->ops.read_i2c_byte_unlocked = NULL; /* disabled for E610 */

sys/dev/ixgbe/ixgbe_e610.c

5131

phy->ops.write_i2c_byte_unlocked = NULL; /* disabled for E610 */

sys/dev/ixgbe/ixgbe_e610.c

5136

ret_val = phy->ops.identify(hw);

sys/dev/ixgbe/ixgbe_e610.c

5159

hw->phy.type = ixgbe_phy_fw;

sys/dev/ixgbe/ixgbe_e610.c

5177

hw->phy.speeds_supported = IXGBE_LINK_SPEED_UNKNOWN;

sys/dev/ixgbe/ixgbe_e610.c

5181

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10_FULL;

sys/dev/ixgbe/ixgbe_e610.c

5185

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;

sys/dev/ixgbe/ixgbe_e610.c

5192

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;

sys/dev/ixgbe/ixgbe_e610.c

5201

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;

sys/dev/ixgbe/ixgbe_e610.c

5208

if (!hw->phy.autoneg_advertised &&

sys/dev/ixgbe/ixgbe_e610.c

5210

hw->phy.autoneg_advertised = hw->phy.speeds_supported;

sys/dev/ixgbe/ixgbe_e610.c

5217

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;

sys/dev/ixgbe/ixgbe_e610.c

5219

if (!hw->phy.autoneg_advertised &&

sys/dev/ixgbe/ixgbe_e610.c

5221

hw->phy.autoneg_advertised = hw->phy.speeds_supported;

sys/dev/ixgbe/ixgbe_e610.c

5226

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;

sys/dev/ixgbe/ixgbe_e610.c

5229

memcpy(&hw->phy.id, pcaps.phy_id_oui, sizeof(u32));

sys/dev/ixgbe/ixgbe_e610.c

5257

hw->phy.sfp_type = ixgbe_sfp_type_unknown;

sys/dev/ixgbe/ixgbe_e610.c

5264

hw->phy.sfp_type = ixgbe_sfp_type_da_cu;

sys/dev/ixgbe/ixgbe_e610.c

5266

hw->phy.sfp_type = ixgbe_sfp_type_sr;

sys/dev/ixgbe/ixgbe_e610.c

5269

hw->phy.sfp_type = ixgbe_sfp_type_lr;

sys/dev/ixgbe/ixgbe_e610.c

5273

hw->phy.sfp_type = ixgbe_sfp_type_not_present;

sys/dev/ixgbe/ixgbe_e610.c

5325

if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL) {

sys/dev/ixgbe/ixgbe_e610.c

5329

if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) {

sys/dev/ixgbe/ixgbe_e610.c

5334

if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) {

sys/dev/ixgbe/ixgbe_e610.c

5342

if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) {

sys/dev/ixgbe/ixgbe_e610.c

5349

if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) {

sys/dev/ixgbe/ixgbe_e610.c

5354

if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) {

sys/dev/ixgbe/ixgbe_phy.c

1016

status = hw->phy.ops.read_reg(hw,

sys/dev/ixgbe/ixgbe_phy.c

1054

hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,

sys/dev/ixgbe/ixgbe_phy.c

1059

if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)

sys/dev/ixgbe/ixgbe_phy.c

1062

hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,

sys/dev/ixgbe/ixgbe_phy.c

1069

hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,

sys/dev/ixgbe/ixgbe_phy.c

1074

if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)

sys/dev/ixgbe/ixgbe_phy.c

1077

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,

sys/dev/ixgbe/ixgbe_phy.c

1084

hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,

sys/dev/ixgbe/ixgbe_phy.c

1089

if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)

sys/dev/ixgbe/ixgbe_phy.c

1092

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,

sys/dev/ixgbe/ixgbe_phy.c

1113

status = hw->phy.ops.read_reg(hw, TNX_FW_REV,

sys/dev/ixgbe/ixgbe_phy.c

112

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/ixgbe/ixgbe_phy.c

1132

status = hw->phy.ops.read_reg(hw, AQ_FW_REV,

sys/dev/ixgbe/ixgbe_phy.c

1158

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,

sys/dev/ixgbe/ixgbe_phy.c

1162

hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,

sys/dev/ixgbe/ixgbe_phy.c

1167

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,

sys/dev/ixgbe/ixgbe_phy.c

1217

hw->phy.ops.write_reg(hw, phy_offset,

sys/dev/ixgbe/ixgbe_phy.c

1277

hw->phy.sfp_type = ixgbe_sfp_type_not_present;

sys/dev/ixgbe/ixgbe_phy.c

1295

enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;

sys/dev/ixgbe/ixgbe_phy.c

1308

hw->phy.sfp_type = ixgbe_sfp_type_not_present;

sys/dev/ixgbe/ixgbe_phy.c

1316

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1324

hw->phy.type = ixgbe_phy_sfp_unsupported;

sys/dev/ixgbe/ixgbe_phy.c

1327

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1334

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1340

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1365

hw->phy.sfp_type = ixgbe_sfp_type_da_cu;

sys/dev/ixgbe/ixgbe_phy.c

1367

hw->phy.sfp_type = ixgbe_sfp_type_sr;

sys/dev/ixgbe/ixgbe_phy.c

1369

hw->phy.sfp_type = ixgbe_sfp_type_lr;

sys/dev/ixgbe/ixgbe_phy.c

1371

hw->phy.sfp_type = ixgbe_sfp_type_unknown;

sys/dev/ixgbe/ixgbe_phy.c

1375

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1378

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1381

hw->phy.ops.read_i2c_eeprom(

sys/dev/ixgbe/ixgbe_phy.c

1387

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1390

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1393

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1400

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1403

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1407

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1410

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1414

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1417

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1421

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1424

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1428

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1431

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1434

hw->phy.sfp_type = ixgbe_sfp_type_unknown;

sys/dev/ixgbe/ixgbe_phy.c

1438

if (hw->phy.sfp_type != stored_sfp_type)

sys/dev/ixgbe/ixgbe_phy.c

1439

hw->phy.sfp_setup_needed = true;

sys/dev/ixgbe/ixgbe_phy.c

1442

hw->phy.multispeed_fiber = false;

sys/dev/ixgbe/ixgbe_phy.c

1449

hw->phy.multispeed_fiber = true;

sys/dev/ixgbe/ixgbe_phy.c

1452

if (hw->phy.type != ixgbe_phy_nl) {

sys/dev/ixgbe/ixgbe_phy.c

1453

hw->phy.id = identifier;

sys/dev/ixgbe/ixgbe_phy.c

1454

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1461

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1468

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1483

hw->phy.type =

sys/dev/ixgbe/ixgbe_phy.c

1488

hw->phy.type = ixgbe_phy_sfp_ftl_active;

sys/dev/ixgbe/ixgbe_phy.c

1490

hw->phy.type = ixgbe_phy_sfp_ftl;

sys/dev/ixgbe/ixgbe_phy.c

1493

hw->phy.type = ixgbe_phy_sfp_avago;

sys/dev/ixgbe/ixgbe_phy.c

1496

hw->phy.type = ixgbe_phy_sfp_intel;

sys/dev/ixgbe/ixgbe_phy.c

1500

hw->phy.type = ixgbe_phy_sfp_passive_unknown;

sys/dev/ixgbe/ixgbe_phy.c

1502

hw->phy.type = ixgbe_phy_sfp_active_unknown;

sys/dev/ixgbe/ixgbe_phy.c

1504

hw->phy.type = ixgbe_phy_sfp_unknown;

sys/dev/ixgbe/ixgbe_phy.c

1518

!(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||

sys/dev/ixgbe/ixgbe_phy.c

1519

hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||

sys/dev/ixgbe/ixgbe_phy.c

1520

hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||

sys/dev/ixgbe/ixgbe_phy.c

1521

hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||

sys/dev/ixgbe/ixgbe_phy.c

1522

hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||

sys/dev/ixgbe/ixgbe_phy.c

1523

hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||

sys/dev/ixgbe/ixgbe_phy.c

1524

hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 ||

sys/dev/ixgbe/ixgbe_phy.c

1525

hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1)) {

sys/dev/ixgbe/ixgbe_phy.c

1526

hw->phy.type = ixgbe_phy_sfp_unsupported;

sys/dev/ixgbe/ixgbe_phy.c

1539

!(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||

sys/dev/ixgbe/ixgbe_phy.c

1540

hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||

sys/dev/ixgbe/ixgbe_phy.c

1541

hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||

sys/dev/ixgbe/ixgbe_phy.c

1542

hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||

sys/dev/ixgbe/ixgbe_phy.c

1543

hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||

sys/dev/ixgbe/ixgbe_phy.c

1544

hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||

sys/dev/ixgbe/ixgbe_phy.c

1545

hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 ||

sys/dev/ixgbe/ixgbe_phy.c

1546

hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1)) {

sys/dev/ixgbe/ixgbe_phy.c

1548

if (hw->phy.type == ixgbe_phy_sfp_intel) {

sys/dev/ixgbe/ixgbe_phy.c

1562

hw->phy.type =

sys/dev/ixgbe/ixgbe_phy.c

1576

hw->phy.sfp_type = ixgbe_sfp_type_not_present;

sys/dev/ixgbe/ixgbe_phy.c

1577

if (hw->phy.type != ixgbe_phy_nl) {

sys/dev/ixgbe/ixgbe_phy.c

1578

hw->phy.id = 0;

sys/dev/ixgbe/ixgbe_phy.c

1579

hw->phy.type = ixgbe_phy_unknown;

sys/dev/ixgbe/ixgbe_phy.c

1598

hw->phy.ops.identify_sfp(hw);

sys/dev/ixgbe/ixgbe_phy.c

1599

if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)

sys/dev/ixgbe/ixgbe_phy.c

1602

switch (hw->phy.type) {

sys/dev/ixgbe/ixgbe_phy.c

1617

hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1619

hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1634

hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1658

enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;

sys/dev/ixgbe/ixgbe_phy.c

1673

hw->phy.sfp_type = ixgbe_sfp_type_not_present;

sys/dev/ixgbe/ixgbe_phy.c

1681

status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,

sys/dev/ixgbe/ixgbe_phy.c

1688

hw->phy.type = ixgbe_phy_sfp_unsupported;

sys/dev/ixgbe/ixgbe_phy.c

1693

hw->phy.id = identifier;

sys/dev/ixgbe/ixgbe_phy.c

1695

status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,

sys/dev/ixgbe/ixgbe_phy.c

1701

status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,

sys/dev/ixgbe/ixgbe_phy.c

1708

hw->phy.type = ixgbe_phy_qsfp_passive_unknown;

sys/dev/ixgbe/ixgbe_phy.c

1710

hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;

sys/dev/ixgbe/ixgbe_phy.c

1712

hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;

sys/dev/ixgbe/ixgbe_phy.c

1716

hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;

sys/dev/ixgbe/ixgbe_phy.c

1718

hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;

sys/dev/ixgbe/ixgbe_phy.c

1726

hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1730

hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1734

hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1747

hw->phy.type = ixgbe_phy_qsfp_active_unknown;

sys/dev/ixgbe/ixgbe_phy.c

1749

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1752

hw->phy.sfp_type =

sys/dev/ixgbe/ixgbe_phy.c

1756

hw->phy.type = ixgbe_phy_sfp_unsupported;

sys/dev/ixgbe/ixgbe_phy.c

1762

if (hw->phy.sfp_type != stored_sfp_type)

sys/dev/ixgbe/ixgbe_phy.c

1763

hw->phy.sfp_setup_needed = true;

sys/dev/ixgbe/ixgbe_phy.c

1766

hw->phy.multispeed_fiber = false;

sys/dev/ixgbe/ixgbe_phy.c

1771

hw->phy.multispeed_fiber = true;

sys/dev/ixgbe/ixgbe_phy.c

1776

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1783

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1790

status = hw->phy.ops.read_i2c_eeprom(hw,

sys/dev/ixgbe/ixgbe_phy.c

1803

hw->phy.type = ixgbe_phy_qsfp_intel;

sys/dev/ixgbe/ixgbe_phy.c

1805

hw->phy.type = ixgbe_phy_qsfp_unknown;

sys/dev/ixgbe/ixgbe_phy.c

1810

if (hw->phy.type == ixgbe_phy_qsfp_intel) {

sys/dev/ixgbe/ixgbe_phy.c

1823

hw->phy.type =

sys/dev/ixgbe/ixgbe_phy.c

1837

hw->phy.sfp_type = ixgbe_sfp_type_not_present;

sys/dev/ixgbe/ixgbe_phy.c

1838

hw->phy.id = 0;

sys/dev/ixgbe/ixgbe_phy.c

1839

hw->phy.type = ixgbe_phy_unknown;

sys/dev/ixgbe/ixgbe_phy.c

1858

u16 sfp_type = hw->phy.sfp_type;

sys/dev/ixgbe/ixgbe_phy.c

1862

if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)

sys/dev/ixgbe/ixgbe_phy.c

1865

if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)

sys/dev/ixgbe/ixgbe_phy.c

1869

(hw->phy.sfp_type == ixgbe_sfp_type_da_cu))

sys/dev/ixgbe/ixgbe_phy.c

189

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/ixgbe/ixgbe_phy.c

1954

return hw->phy.ops.read_i2c_byte(hw, byte_offset,

sys/dev/ixgbe/ixgbe_phy.c

1970

return hw->phy.ops.read_i2c_byte(hw, byte_offset,

sys/dev/ixgbe/ixgbe_phy.c

1988

return hw->phy.ops.write_i2c_byte(hw, byte_offset,

sys/dev/ixgbe/ixgbe_phy.c

2003

hw->phy.sfp_type == ixgbe_sfp_type_not_present)

sys/dev/ixgbe/ixgbe_phy.c

2025

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/ixgbe/ixgbe_phy.c

2148

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/ixgbe/ixgbe_phy.c

249

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/ixgbe/ixgbe_phy.c

254

phy->ops.identify = ixgbe_identify_phy_generic;

sys/dev/ixgbe/ixgbe_phy.c

255

phy->ops.reset = ixgbe_reset_phy_generic;

sys/dev/ixgbe/ixgbe_phy.c

256

phy->ops.read_reg = ixgbe_read_phy_reg_generic;

sys/dev/ixgbe/ixgbe_phy.c

257

phy->ops.write_reg = ixgbe_write_phy_reg_generic;

sys/dev/ixgbe/ixgbe_phy.c

258

phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;

sys/dev/ixgbe/ixgbe_phy.c

259

phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;

sys/dev/ixgbe/ixgbe_phy.c

260

phy->ops.setup_link = ixgbe_setup_phy_link_generic;

sys/dev/ixgbe/ixgbe_phy.c

261

phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;

sys/dev/ixgbe/ixgbe_phy.c

262

phy->ops.check_link = NULL;

sys/dev/ixgbe/ixgbe_phy.c

263

phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;

sys/dev/ixgbe/ixgbe_phy.c

264

phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;

sys/dev/ixgbe/ixgbe_phy.c

265

phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;

sys/dev/ixgbe/ixgbe_phy.c

266

phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;

sys/dev/ixgbe/ixgbe_phy.c

267

phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;

sys/dev/ixgbe/ixgbe_phy.c

2675

hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,

sys/dev/ixgbe/ixgbe_phy.c

268

phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;

sys/dev/ixgbe/ixgbe_phy.c

269

phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;

sys/dev/ixgbe/ixgbe_phy.c

270

phy->ops.identify_sfp = ixgbe_identify_module_generic;

sys/dev/ixgbe/ixgbe_phy.c

2700

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,

sys/dev/ixgbe/ixgbe_phy.c

271

phy->sfp_type = ixgbe_sfp_type_unknown;

sys/dev/ixgbe/ixgbe_phy.c

2714

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,

sys/dev/ixgbe/ixgbe_phy.c

272

phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;

sys/dev/ixgbe/ixgbe_phy.c

273

phy->ops.write_i2c_byte_unlocked =

sys/dev/ixgbe/ixgbe_phy.c

275

phy->ops.check_overtemp = ixgbe_tn_check_overtemp;

sys/dev/ixgbe/ixgbe_phy.c

299

hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);

sys/dev/ixgbe/ixgbe_phy.c

301

if (hw->phy.type == ixgbe_phy_unknown) {

sys/dev/ixgbe/ixgbe_phy.c

302

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,

sys/dev/ixgbe/ixgbe_phy.c

307

hw->phy.type = ixgbe_phy_cu_unknown;

sys/dev/ixgbe/ixgbe_phy.c

309

hw->phy.type = ixgbe_phy_generic;

sys/dev/ixgbe/ixgbe_phy.c

328

if (!hw->phy.phy_semaphore_mask) {

sys/dev/ixgbe/ixgbe_phy.c

330

hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;

sys/dev/ixgbe/ixgbe_phy.c

332

hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;

sys/dev/ixgbe/ixgbe_phy.c

335

if (hw->phy.type != ixgbe_phy_unknown)

sys/dev/ixgbe/ixgbe_phy.c

338

if (hw->phy.nw_mng_if_sel) {

sys/dev/ixgbe/ixgbe_phy.c

339

phy_addr = (hw->phy.nw_mng_if_sel &

sys/dev/ixgbe/ixgbe_phy.c

360

hw->phy.addr = 0;

sys/dev/ixgbe/ixgbe_phy.c

407

hw->phy.addr = phy_addr;

sys/dev/ixgbe/ixgbe_phy.c

408

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,

sys/dev/ixgbe/ixgbe_phy.c

432

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,

sys/dev/ixgbe/ixgbe_phy.c

437

hw->phy.id = (u32)(phy_id_high << 16);

sys/dev/ixgbe/ixgbe_phy.c

438

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,

sys/dev/ixgbe/ixgbe_phy.c

441

hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);

sys/dev/ixgbe/ixgbe_phy.c

442

hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);

sys/dev/ixgbe/ixgbe_phy.c

502

if (hw->phy.type == ixgbe_phy_unknown)

sys/dev/ixgbe/ixgbe_phy.c

505

if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)

sys/dev/ixgbe/ixgbe_phy.c

509

if (!hw->phy.reset_if_overtemp &&

sys/dev/ixgbe/ixgbe_phy.c

510

(IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))

sys/dev/ixgbe/ixgbe_phy.c

521

hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,

sys/dev/ixgbe/ixgbe_phy.c

532

if (hw->phy.type == ixgbe_phy_x550em_ext_t) {

sys/dev/ixgbe/ixgbe_phy.c

533

status = hw->phy.ops.read_reg(hw,

sys/dev/ixgbe/ixgbe_phy.c

545

status = hw->phy.ops.read_reg(hw,

sys/dev/ixgbe/ixgbe_phy.c

582

hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,

sys/dev/ixgbe/ixgbe_phy.c

585

hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,

sys/dev/ixgbe/ixgbe_phy.c

605

(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |

sys/dev/ixgbe/ixgbe_phy.c

636

(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |

sys/dev/ixgbe/ixgbe_phy.c

683

u32 gssr = hw->phy.phy_semaphore_mask;

sys/dev/ixgbe/ixgbe_phy.c

690

status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);

sys/dev/ixgbe/ixgbe_phy.c

716

(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |

sys/dev/ixgbe/ixgbe_phy.c

745

(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |

sys/dev/ixgbe/ixgbe_phy.c

783

u32 gssr = hw->phy.phy_semaphore_mask;

sys/dev/ixgbe/ixgbe_phy.c

788

status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,

sys/dev/ixgbe/ixgbe_phy.c

816

hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,

sys/dev/ixgbe/ixgbe_phy.c

821

if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&

sys/dev/ixgbe/ixgbe_phy.c

825

hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,

sys/dev/ixgbe/ixgbe_phy.c

829

hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,

sys/dev/ixgbe/ixgbe_phy.c

836

if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&

sys/dev/ixgbe/ixgbe_phy.c

842

if ((hw->phy.autoneg_advertised &

sys/dev/ixgbe/ixgbe_phy.c

850

if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&

sys/dev/ixgbe/ixgbe_phy.c

854

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,

sys/dev/ixgbe/ixgbe_phy.c

859

hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,

sys/dev/ixgbe/ixgbe_phy.c

865

if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&

sys/dev/ixgbe/ixgbe_phy.c

869

hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,

sys/dev/ixgbe/ixgbe_phy.c

895

hw->phy.autoneg_advertised = 0;

sys/dev/ixgbe/ixgbe_phy.c

898

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;

sys/dev/ixgbe/ixgbe_phy.c

901

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;

sys/dev/ixgbe/ixgbe_phy.c

904

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;

sys/dev/ixgbe/ixgbe_phy.c

907

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;

sys/dev/ixgbe/ixgbe_phy.c

910

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;

sys/dev/ixgbe/ixgbe_phy.c

913

hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;

sys/dev/ixgbe/ixgbe_phy.c

933

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,

sys/dev/ixgbe/ixgbe_phy.c

940

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;

sys/dev/ixgbe/ixgbe_phy.c

942

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;

sys/dev/ixgbe/ixgbe_phy.c

944

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;

sys/dev/ixgbe/ixgbe_phy.c

948

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;

sys/dev/ixgbe/ixgbe_phy.c

949

hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;

sys/dev/ixgbe/ixgbe_phy.c

953

hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;

sys/dev/ixgbe/ixgbe_phy.c

977

if (!hw->phy.speeds_supported)

sys/dev/ixgbe/ixgbe_phy.c

980

*speed = hw->phy.speeds_supported;

sys/dev/ixgbe/ixgbe_type.h

4278

struct ixgbe_phy_info phy;

sys/dev/ixgbe/ixgbe_x540.c

204

return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);

sys/dev/ixgbe/ixgbe_x540.c

218

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/ixgbe/ixgbe_x540.c

346

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,

sys/dev/ixgbe/ixgbe_x540.c

62

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/ixgbe/ixgbe_x540.c

84

phy->ops.init = ixgbe_init_phy_ops_generic;

sys/dev/ixgbe/ixgbe_x540.c

85

phy->ops.reset = NULL;

sys/dev/ixgbe/ixgbe_x540.c

86

phy->ops.set_phy_power = ixgbe_set_copper_phy_power;

sys/dev/ixgbe/ixgbe_x550.c

1462

hw->phy.type = ixgbe_phy_sgmii;

sys/dev/ixgbe/ixgbe_x550.c

1484

switch (hw->phy.sfp_type) {

sys/dev/ixgbe/ixgbe_x550.c

1555

hw->phy.ops.reset = NULL;

sys/dev/ixgbe/ixgbe_x550.c

1673

return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);

sys/dev/ixgbe/ixgbe_x550.c

1746

return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);

sys/dev/ixgbe/ixgbe_x550.c

1820

if (hw->phy.type == ixgbe_phy_fw) {

sys/dev/ixgbe/ixgbe_x550.c

1822

*speed = hw->phy.speeds_supported;

sys/dev/ixgbe/ixgbe_x550.c

1827

if (hw->phy.media_type == ixgbe_media_type_fiber) {

sys/dev/ixgbe/ixgbe_x550.c

1833

if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||

sys/dev/ixgbe/ixgbe_x550.c

1834

hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||

sys/dev/ixgbe/ixgbe_x550.c

1835

hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||

sys/dev/ixgbe/ixgbe_x550.c

1836

hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||

sys/dev/ixgbe/ixgbe_x550.c

1837

hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 ||

sys/dev/ixgbe/ixgbe_x550.c

1838

hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1) {

sys/dev/ixgbe/ixgbe_x550.c

1844

if (hw->phy.multispeed_fiber)

sys/dev/ixgbe/ixgbe_x550.c

1852

switch (hw->phy.type) {

sys/dev/ixgbe/ixgbe_x550.c

1865

if (hw->phy.nw_mng_if_sel &

sys/dev/ixgbe/ixgbe_x550.c

1908

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,

sys/dev/ixgbe/ixgbe_x550.c

1917

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,

sys/dev/ixgbe/ixgbe_x550.c

1927

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,

sys/dev/ixgbe/ixgbe_x550.c

1941

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,

sys/dev/ixgbe/ixgbe_x550.c

1957

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,

sys/dev/ixgbe/ixgbe_x550.c

1965

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,

sys/dev/ixgbe/ixgbe_x550.c

2007

status = hw->phy.ops.read_reg(hw,

sys/dev/ixgbe/ixgbe_x550.c

2016

status = hw->phy.ops.write_reg(hw,

sys/dev/ixgbe/ixgbe_x550.c

2025

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,

sys/dev/ixgbe/ixgbe_x550.c

2035

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,

sys/dev/ixgbe/ixgbe_x550.c

2043

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,

sys/dev/ixgbe/ixgbe_x550.c

2053

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,

sys/dev/ixgbe/ixgbe_x550.c

2061

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,

sys/dev/ixgbe/ixgbe_x550.c

2070

status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,

sys/dev/ixgbe/ixgbe_x550.c

2144

if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))

sys/dev/ixgbe/ixgbe_x550.c

2191

hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);

sys/dev/ixgbe/ixgbe_x550.c

2197

hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {

sys/dev/ixgbe/ixgbe_x550.c

2198

hw->phy.addr = (hw->phy.nw_mng_if_sel &

sys/dev/ixgbe/ixgbe_x550.c

2216

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/ixgbe/ixgbe_x550.c

2225

phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;

sys/dev/ixgbe/ixgbe_x550.c

2227

phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;

sys/dev/ixgbe/ixgbe_x550.c

2233

phy->ops.read_reg_mdi = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2234

phy->ops.write_reg_mdi = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2235

hw->phy.ops.read_reg = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2236

hw->phy.ops.write_reg = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2237

phy->ops.check_overtemp = ixgbe_check_overtemp_fw;

sys/dev/ixgbe/ixgbe_x550.c

2239

hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;

sys/dev/ixgbe/ixgbe_x550.c

2241

hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;

sys/dev/ixgbe/ixgbe_x550.c

2246

hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;

sys/dev/ixgbe/ixgbe_x550.c

2247

hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;

sys/dev/ixgbe/ixgbe_x550.c

2249

hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;

sys/dev/ixgbe/ixgbe_x550.c

2251

hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;

sys/dev/ixgbe/ixgbe_x550.c

2255

hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;

sys/dev/ixgbe/ixgbe_x550.c

2258

phy->ops.read_reg_mdi = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2259

phy->ops.write_reg_mdi = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2265

ret_val = phy->ops.identify(hw);

sys/dev/ixgbe/ixgbe_x550.c

2272

if (phy->sfp_type != ixgbe_sfp_type_unknown)

sys/dev/ixgbe/ixgbe_x550.c

2273

phy->ops.reset = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2276

switch (hw->phy.type) {

sys/dev/ixgbe/ixgbe_x550.c

2278

phy->ops.setup_link = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2279

phy->ops.read_reg = ixgbe_read_phy_reg_x550em;

sys/dev/ixgbe/ixgbe_x550.c

2280

phy->ops.write_reg = ixgbe_write_phy_reg_x550em;

sys/dev/ixgbe/ixgbe_x550.c

2283

phy->ops.setup_link = ixgbe_setup_kr_x550em;

sys/dev/ixgbe/ixgbe_x550.c

2284

phy->ops.read_reg = ixgbe_read_phy_reg_x550em;

sys/dev/ixgbe/ixgbe_x550.c

2285

phy->ops.write_reg = ixgbe_write_phy_reg_x550em;

sys/dev/ixgbe/ixgbe_x550.c

2289

phy->ops.setup_link = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2290

phy->ops.reset = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2294

phy->ops.setup_link = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2295

phy->ops.read_reg = ixgbe_read_phy_reg_x550em;

sys/dev/ixgbe/ixgbe_x550.c

2296

phy->ops.write_reg = ixgbe_write_phy_reg_x550em;

sys/dev/ixgbe/ixgbe_x550.c

2302

phy->ops.setup_internal_link =

sys/dev/ixgbe/ixgbe_x550.c

2309

phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;

sys/dev/ixgbe/ixgbe_x550.c

2311

phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;

sys/dev/ixgbe/ixgbe_x550.c

2312

phy->ops.reset = ixgbe_reset_phy_t_X550em;

sys/dev/ixgbe/ixgbe_x550.c

2315

phy->ops.setup_link = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2318

phy->ops.setup_link = ixgbe_setup_fw_link;

sys/dev/ixgbe/ixgbe_x550.c

2319

phy->ops.reset = ixgbe_reset_phy_fw;

sys/dev/ixgbe/ixgbe_x550.c

2374

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/ixgbe/ixgbe_x550.c

2390

status = hw->phy.ops.init(hw);

sys/dev/ixgbe/ixgbe_x550.c

2403

if (hw->phy.type == ixgbe_phy_x550em_ext_t) {

sys/dev/ixgbe/ixgbe_x550.c

2413

if (hw->phy.sfp_setup_needed) {

sys/dev/ixgbe/ixgbe_x550.c

2415

hw->phy.sfp_setup_needed = false;

sys/dev/ixgbe/ixgbe_x550.c

2422

if (!hw->phy.reset_disable && hw->phy.ops.reset) {

sys/dev/ixgbe/ixgbe_x550.c

2423

if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)

sys/dev/ixgbe/ixgbe_x550.c

2505

status = hw->phy.ops.read_reg(hw,

sys/dev/ixgbe/ixgbe_x550.c

2517

status = hw->phy.ops.read_reg(hw,

sys/dev/ixgbe/ixgbe_x550.c

252

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/ixgbe/ixgbe_x550.c

2527

status = hw->phy.ops.write_reg(hw,

sys/dev/ixgbe/ixgbe_x550.c

2546

if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)

sys/dev/ixgbe/ixgbe_x550.c

2552

return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);

sys/dev/ixgbe/ixgbe_x550.c

2706

if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {

sys/dev/ixgbe/ixgbe_x550.c

2713

ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,

sys/dev/ixgbe/ixgbe_x550.c

2731

ret_val = hw->phy.ops.read_reg(hw, reg_slice,

sys/dev/ixgbe/ixgbe_x550.c

2744

ret_val = hw->phy.ops.write_reg(hw, reg_slice,

sys/dev/ixgbe/ixgbe_x550.c

2748

ret_val = hw->phy.ops.read_reg(hw, reg_slice,

sys/dev/ixgbe/ixgbe_x550.c

2898

ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,

sys/dev/ixgbe/ixgbe_x550.c

2904

ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,

sys/dev/ixgbe/ixgbe_x550.c

2938

!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {

sys/dev/ixgbe/ixgbe_x550.c

2947

status = hw->phy.ops.read_reg(hw,

sys/dev/ixgbe/ixgbe_x550.c

3580

hw->phy.ops.identify(hw);

sys/dev/ixgbe/ixgbe_x550.c

3582

switch (hw->phy.type) {

sys/dev/ixgbe/ixgbe_x550.c

3585

if (hw->phy.nw_mng_if_sel &

sys/dev/ixgbe/ixgbe_x550.c

3609

hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,

sys/dev/ixgbe/ixgbe_x550.c

3618

if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)

sys/dev/ixgbe/ixgbe_x550.c

3620

if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)

sys/dev/ixgbe/ixgbe_x550.c

3622

if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)

sys/dev/ixgbe/ixgbe_x550.c

363

hw->phy.type = ixgbe_phy_x550em_kx4;

sys/dev/ixgbe/ixgbe_x550.c

366

hw->phy.type = ixgbe_phy_x550em_xfi;

sys/dev/ixgbe/ixgbe_x550.c

371

hw->phy.type = ixgbe_phy_x550em_kr;

sys/dev/ixgbe/ixgbe_x550.c

3758

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,

sys/dev/ixgbe/ixgbe_x550.c

377

hw->phy.type = ixgbe_phy_ext_1g_t;

sys/dev/ixgbe/ixgbe_x550.c

3781

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,

sys/dev/ixgbe/ixgbe_x550.c

3788

status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,

sys/dev/ixgbe/ixgbe_x550.c

3795

status = hw->phy.ops.read_reg(hw,

sys/dev/ixgbe/ixgbe_x550.c

3803

save_autoneg = hw->phy.autoneg_advertised;

sys/dev/ixgbe/ixgbe_x550.c

3809

hw->phy.autoneg_advertised = save_autoneg;

sys/dev/ixgbe/ixgbe_x550.c

381

hw->phy.type = ixgbe_phy_fw;

sys/dev/ixgbe/ixgbe_x550.c

3829

status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,

sys/dev/ixgbe/ixgbe_x550.c

383

hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;

sys/dev/ixgbe/ixgbe_x550.c

385

hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;

sys/dev/ixgbe/ixgbe_x550.c

4283

hw->phy.id);

sys/dev/ixgbe/ixgbe_x550.c

4322

u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;

sys/dev/ixgbe/ixgbe_x550.c

4329

status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);

sys/dev/ixgbe/ixgbe_x550.c

4350

u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;

sys/dev/ixgbe/ixgbe_x550.c

4355

status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,

sys/dev/ixgbe/ixgbe_x550.c

4425

!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {

sys/dev/ixgbe/ixgbe_x550.c

4445

return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);

sys/dev/ixgbe/ixgbe_x550.c

4479

status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,

sys/dev/ixgbe/ixgbe_x550.c

469

hw->phy.speeds_supported = 0;

sys/dev/ixgbe/ixgbe_x550.c

473

hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;

sys/dev/ixgbe/ixgbe_x550.c

475

if (!hw->phy.autoneg_advertised)

sys/dev/ixgbe/ixgbe_x550.c

476

hw->phy.autoneg_advertised = hw->phy.speeds_supported;

sys/dev/ixgbe/ixgbe_x550.c

478

hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;

sys/dev/ixgbe/ixgbe_x550.c

480

hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;

sys/dev/ixgbe/ixgbe_x550.c

481

hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;

sys/dev/ixgbe/ixgbe_x550.c

482

if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)

sys/dev/ixgbe/ixgbe_x550.c

496

hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;

sys/dev/ixgbe/ixgbe_x550.c

498

hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;

sys/dev/ixgbe/ixgbe_x550.c

500

hw->phy.type = ixgbe_phy_fw;

sys/dev/ixgbe/ixgbe_x550.c

501

hw->phy.ops.read_reg = NULL;

sys/dev/ixgbe/ixgbe_x550.c

502

hw->phy.ops.write_reg = NULL;

sys/dev/ixgbe/ixgbe_x550.c

607

struct ixgbe_phy_info *phy = &hw->phy;

sys/dev/ixgbe/ixgbe_x550.c

663

phy->ops.init = ixgbe_init_phy_ops_X550em;

sys/dev/ixgbe/ixgbe_x550.c

668

phy->ops.identify = ixgbe_identify_phy_fw;

sys/dev/ixgbe/ixgbe_x550.c

669

phy->ops.set_phy_power = NULL;

sys/dev/ixgbe/ixgbe_x550.c

670

phy->ops.get_firmware_version = NULL;

sys/dev/ixgbe/ixgbe_x550.c

674

phy->ops.identify = ixgbe_identify_phy_x550em;

sys/dev/ixgbe/ixgbe_x550.c

675

phy->ops.set_phy_power = NULL;

sys/dev/ixgbe/ixgbe_x550.c

678

phy->ops.identify = ixgbe_identify_phy_x550em;

sys/dev/ixgbe/ixgbe_x550.c

682

phy->ops.set_phy_power = NULL;

sys/dev/ixgbe/ixgbe_x550.c

708

if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))

sys/dev/ixgbe/ixgbe_x550.c

735

if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)

sys/dev/ixgbe/ixgbe_x550.c

740

if (hw->phy.eee_speeds_advertised)

sys/dev/ixgbe/ixgbe_x550.c

775

if (!!hw->phy.eee_speeds_advertised == enable_eee)

sys/dev/ixgbe/ixgbe_x550.c

778

hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;

sys/dev/ixgbe/ixgbe_x550.c

780

hw->phy.eee_speeds_advertised = 0;

sys/dev/ixgbe/ixgbe_x550.c

781

return hw->phy.ops.setup_link(hw);

sys/dev/ixgbe/ixgbe_x550.c

825

hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |

sys/dev/ixgbe/ixgbe_x550.c

827

hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;

sys/dev/ixl/i40e_common.c

1011

hw->phy.get_link_info = TRUE;

sys/dev/ixl/i40e_common.c

1245

switch (hw->phy.link_info.phy_type) {

sys/dev/ixl/i40e_common.c

1713

hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);

sys/dev/ixl/i40e_common.c

1714

hw->phy.phy_types |=

sys/dev/ixl/i40e_common.c

1964

struct i40e_link_status *hw_link_info = &hw->phy.link_info;

sys/dev/ixl/i40e_common.c

1983

i40e_memcpy(&hw->phy.link_info_old, hw_link_info,

sys/dev/ixl/i40e_common.c

1988

hw->phy.media_type = i40e_get_media_type(hw);

sys/dev/ixl/i40e_common.c

2035

hw->phy.phy_types = LE32_TO_CPU(tmp);

sys/dev/ixl/i40e_common.c

2036

hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);

sys/dev/ixl/i40e_common.c

2045

hw->phy.get_link_info = FALSE;

sys/dev/ixl/i40e_common.c

2875

if (hw->phy.get_link_info) {

sys/dev/ixl/i40e_common.c

2883

*link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;

sys/dev/ixl/i40e_common.c

2902

if (((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&

sys/dev/ixl/i40e_common.c

2903

((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||

sys/dev/ixl/i40e_common.c

2904

!(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) ||

sys/dev/ixl/i40e_common.c

2915

hw->phy.link_info.req_fec_info =

sys/dev/ixl/i40e_common.c

2919

hw->phy.link_info.req_fec_info =

sys/dev/ixl/i40e_common.c

2924

i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,

sys/dev/ixl/i40e_common.c

2925

sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);

sys/dev/ixl/i40e_common.c

2942

if (hw->phy.get_link_info) {

sys/dev/ixl/i40e_common.c

2949

speed = hw->phy.link_info.link_speed;

sys/dev/ixl/i40e_common.c

6990

(hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||

sys/dev/ixl/i40e_common.c

6991

hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB);

sys/dev/ixl/i40e_common.c

7041

hw->phy.link_info.link_speed != I40E_LINK_SPEED_1GB) {

sys/dev/ixl/i40e_common.c

7097

if (hw->phy.link_info.link_speed == I40E_LINK_SPEED_1GB &&

sys/dev/ixl/i40e_type.h

690

struct i40e_phy_info phy;

sys/dev/ixl/if_ixl.c

1354

baudrate = ixl_max_aq_speed_to_value(hw->phy.link_info.link_speed);

sys/dev/ixl/if_ixl.c

1554

switch (hw->phy.link_info.phy_type) {

sys/dev/ixl/if_ixl.c

1670

if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)

sys/dev/ixl/if_ixl.c

1672

if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)

sys/dev/ixl/if_ixl.c

451

hw->phy.get_link_info = TRUE;

sys/dev/ixl/if_ixl.c

798

hw->phy.get_link_info = true;

sys/dev/ixl/ixl_pf_iflib.c

386

ixl_add_ifmedia(vsi->media, hw->phy.phy_types);

sys/dev/ixl/ixl_pf_iflib.c

405

struct i40e_link_status *link_info = &hw->phy.link_info;

sys/dev/ixl/ixl_pf_iflib.c

413

hw->phy.get_link_info = TRUE;

sys/dev/ixl/ixl_pf_iov.c

1396

i40e_virtchnl_link_speed(hw->phy.link_info.link_speed);

sys/dev/ixl/ixl_pf_main.c

2864

ixl_link_speed_string(hw->phy.link_info.link_speed)),

sys/dev/ixl/ixl_pf_main.c

4815

hw->phy.get_link_info = TRUE;

sys/dev/ixl/ixl_pf_main.c

748

fec_abilities = hw->phy.link_info.req_fec_info;

sys/dev/ixl/ixl_pf_main.c

757

if (hw->phy.link_info.fec_info & I40E_AQ_CONFIG_FEC_RS_ENA)

sys/dev/ixl/ixl_pf_main.c

759

else if (hw->phy.link_info.fec_info & I40E_AQ_CONFIG_FEC_KR_ENA)

sys/dev/ixl/ixl_pf_main.c

766

ixl_link_speed_string(hw->phy.link_info.link_speed),

sys/dev/ixl/ixl_pf_main.c

768

(hw->phy.link_info.an_info & I40E_AQ_AN_COMPLETED) ? "True" : "False",

sys/dev/ixl/ixl_pf_main.c

769

(hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX &&

sys/dev/ixl/ixl_pf_main.c

770

hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX) ?

sys/dev/ixl/ixl_pf_main.c

771

ixl_fc_string[3] : (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) ?

sys/dev/ixl/ixl_pf_main.c

772

ixl_fc_string[2] : (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX) ?

sys/dev/jme/if_jme.c

212

jme_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/jme/if_jme.c

221

if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0)

sys/dev/jme/if_jme.c

225

SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));

sys/dev/jme/if_jme.c

244

jme_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/jme/if_jme.c

252

if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0)

sys/dev/jme/if_jme.c

257

SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));

sys/dev/lge/if_lge.c

261

lge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/lge/if_lge.c

273

if (sc->lge_pcs == 0 && phy == 0)

sys/dev/lge/if_lge.c

276

CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);

sys/dev/lge/if_lge.c

291

lge_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/lge/if_lge.c

299

(data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);

sys/dev/mdio/mdio.c

64

mdio_readreg(device_t dev, int phy, int reg)

sys/dev/mdio/mdio.c

67

return (MDIO_READREG(device_get_parent(dev), phy, reg));

sys/dev/mdio/mdio.c

71

mdio_writereg(device_t dev, int phy, int reg, int val)

sys/dev/mdio/mdio.c

74

return (MDIO_WRITEREG(device_get_parent(dev), phy, reg, val));

sys/dev/mdio/mdio.c

78

mdio_readextreg(device_t dev, int phy, int devad, int reg)

sys/dev/mdio/mdio.c

81

return (MDIO_READEXTREG(device_get_parent(dev), phy, devad, reg));

sys/dev/mdio/mdio.c

85

mdio_writeextreg(device_t dev, int phy, int devad, int reg,

sys/dev/mdio/mdio.c

89

return (MDIO_WRITEEXTREG(device_get_parent(dev), phy, devad, reg, val));

sys/dev/mgb/if_mgb.c

1540

mgb_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/mgb/if_mgb.c

1550

mii_access = (phy & MGB_MII_PHY_ADDR_MASK) << MGB_MII_PHY_ADDR_SHIFT;

sys/dev/mgb/if_mgb.c

1561

mgb_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/mgb/if_mgb.c

1571

mii_access = (phy & MGB_MII_PHY_ADDR_MASK) << MGB_MII_PHY_ADDR_SHIFT;

sys/dev/mge/if_mge.c

1553

mge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/mge/if_mge.c

1558

return (mv_read_ext_phy(dev, phy, reg));

sys/dev/mge/if_mge.c

1562

mge_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/mge/if_mge.c

1567

mv_write_ext_phy(dev, phy, reg, value);

sys/dev/mge/if_mge.c

207

mv_read_ge_smi(device_t dev, int phy, int reg)

sys/dev/mge/if_mge.c

2121

mge_mdio_writereg(device_t dev, int phy, int reg, int value)

sys/dev/mge/if_mge.c

2124

mv_write_ge_smi(dev, phy, reg, value);

sys/dev/mge/if_mge.c

2131

mge_mdio_readreg(device_t dev, int phy, int reg)

sys/dev/mge/if_mge.c

2135

ret = mv_read_ge_smi(dev, phy, reg);

sys/dev/mge/if_mge.c

229

(MGE_SMI_READ | (reg << 21) | (phy << 16)));

sys/dev/mge/if_mge.c

254

mv_write_ge_smi(device_t dev, int phy, int reg, uint32_t value)

sys/dev/mge/if_mge.c

274

(MGE_SMI_WRITE | (reg << 21) | (phy << 16) |

sys/dev/mge/if_mge.c

282

mv_read_ext_phy(device_t dev, int phy, int reg)

sys/dev/mge/if_mge.c

292

(MGE_SMI_READ | (reg << 21) | (phy << 16)));

sys/dev/mge/if_mge.c

309

mv_write_ext_phy(device_t dev, int phy, int reg, int value)

sys/dev/mge/if_mge.c

318

(MGE_SMI_WRITE | (reg << 21) | (phy << 16) |

sys/dev/mge/if_mge.c

767

int i, error, phy;

sys/dev/mge/if_mge.c

772

phy = 0;

sys/dev/mge/if_mge.c

774

if (fdt_get_phyaddr(sc->node, sc->dev, &phy, (void **)&sc->phy_sc) == 0) {

sys/dev/mge/if_mge.c

775

device_printf(dev, "PHY%i attached, phy_sc points to %s\n", phy,

sys/dev/mge/if_mge.c

862

mge_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);

sys/dev/mge/if_mge.c

94

static int mge_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/mge/if_mge.c

95

static int mge_miibus_writereg(device_t dev, int phy, int reg, int value);

sys/dev/mge/if_mge.c

97

static int mge_mdio_readreg(device_t dev, int phy, int reg);

sys/dev/mge/if_mge.c

98

static int mge_mdio_writereg(device_t dev, int phy, int reg, int value);

sys/dev/mge/if_mgevar.h

180

#define SW_SMI_READ_CMD(phy, reg) ((1 << 15) | (1 << 12) | (1 << 11) | (phy << 5) | reg)

sys/dev/mge/if_mgevar.h

181

#define SW_SMI_WRITE_CMD(phy, reg) ((1 << 15) | (1 << 12) | (1 << 10) | (phy << 5) | reg)

sys/dev/mii/mii.c

241

device_t *children, phy;

sys/dev/mii/mii.c

268

phy = device_add_child(dev, name, unit);

sys/dev/mii/mii.c

269

if (phy == NULL) {

sys/dev/mii/mii.c

279

device_set_ivars(phy, ma);

sys/dev/mii/mii.c

291

miibus_readreg(device_t dev, int phy, int reg)

sys/dev/mii/mii.c

296

return (MIIBUS_READREG(parent, phy, reg));

sys/dev/mii/mii.c

300

miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/mii/mii.c

305

return (MIIBUS_WRITEREG(parent, phy, reg, data));

sys/dev/mii/mii.c

374

device_t *children, phy;

sys/dev/mii/mii.c

500

phy = device_add_child(*miibus, NULL, DEVICE_UNIT_ANY);

sys/dev/mii/mii.c

501

if (phy == NULL) {

sys/dev/mii/mii.c

505

device_set_ivars(phy, args);

sys/dev/mii/mii_bitbang.c

117

mii_bitbang_readreg(device_t dev, mii_bitbang_ops_t ops, int phy, int reg)

sys/dev/mii/mii_bitbang.c

125

mii_bitbang_sendbits(dev, ops, phy, 5);

sys/dev/mii/mii_bitbang.c

165

mii_bitbang_writereg(device_t dev, mii_bitbang_ops_t ops, int phy, int reg,

sys/dev/mii/mii_bitbang.c

173

mii_bitbang_sendbits(dev, ops, phy, 5);

sys/dev/mii/mii_bitbang.h

51

int phy, int reg);

sys/dev/mii/mii_bitbang.h

54

int phy, int reg, int val);

sys/dev/mii/mv88e151x.c

178

mv88e151x_fiber_status(struct mii_softc *phy)

sys/dev/mii/mv88e151x.c

180

struct mii_data *mii = phy->mii_pdata;

sys/dev/mii/mv88e151x.c

189

PHY_WRITE(phy, MV88E151X_PAGE, MV88E151X_PAGE_FIBER);

sys/dev/mii/mv88e151x.c

191

reg = PHY_READ(phy, MV88E151X_FIBER_STATUS);

sys/dev/mii/mv88e151x.c

192

bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);

sys/dev/mii/mv88e151x.c

195

bmcr = PHY_READ(phy, MII_BMCR);

sys/dev/mii/mv88e151x.c

199

PHY_WRITE(phy, MV88E151X_PAGE, MV88E151X_PAGE_COPPER);

sys/dev/mii/mv88e151x.c

215

PHY_WRITE(phy, MV88E151X_PAGE, MV88E151X_PAGE_COPPER);

sys/dev/mii/mv88e151x.c

219

anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);

sys/dev/mii/mv88e151x.c

244

phy->mii_flags |= MIIF_IS_1000X;

sys/dev/mii/mv88e151x.c

246

mii->mii_media_active |= mii_phy_flowstatus(phy);

sys/dev/mii/mv88e151x.c

251

phy->mii_flags &= ~MIIF_IS_1000X;

sys/dev/mii/mv88e151x.c

254

PHY_WRITE(phy, MV88E151X_PAGE, MV88E151X_PAGE_COPPER);

sys/dev/mii/mv88e151x.c

258

mv88e151x_status(struct mii_softc *phy)

sys/dev/mii/mv88e151x.c

260

struct mii_data *mii = phy->mii_pdata;

sys/dev/mii/mv88e151x.c

262

mv88e151x_fiber_status(phy);

sys/dev/mii/mv88e151x.c

265

ukphy_status(phy);

sys/dev/mii/rlphy.c

161

rlphy_status(struct mii_softc *phy)

sys/dev/mii/rlphy.c

163

struct mii_data *mii = phy->mii_pdata;

sys/dev/mii/rlphy.c

170

bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);

sys/dev/mii/rlphy.c

174

bmcr = PHY_READ(phy, MII_BMCR);

sys/dev/mii/rlphy.c

196

if ((anlpar = PHY_READ(phy, MII_ANAR) &

sys/dev/mii/rlphy.c

197

PHY_READ(phy, MII_ANLPAR))) {

sys/dev/mii/rlphy.c

212

mii_phy_flowstatus(phy);

sys/dev/mii/rlphy.c

242

if (!(phy->mii_mpd_model == 0 && phy->mii_mpd_rev == 0)) {

sys/dev/mii/rlphy.c

243

if (PHY_READ(phy, 0x0019) & 0x01)

sys/dev/mii/rlphy.c

248

if (PHY_READ(phy, RL_MEDIASTAT) &

sys/dev/mii/rlswitch.c

367

rlswitch_status(struct mii_softc *phy)

sys/dev/mii/rlswitch.c

369

struct mii_data *mii = phy->mii_pdata;

sys/dev/mii/rlswitch.c

375

IFM_100_TX | IFM_FDX | mii_phy_flowstatus(phy);

sys/dev/mii/rlswitch.c

381

int phy, reg, val;

sys/dev/mii/rlswitch.c

386

for (phy = 0; phy <= 5; phy++) {

sys/dev/mii/rlswitch.c

387

printf("PHY%i:", phy);

sys/dev/mii/rlswitch.c

389

val = MIIBUS_READREG(sc->mii_dev, phy, reg);

sys/dev/mii/tdkphy.c

145

tdkphy_status(struct mii_softc *phy)

sys/dev/mii/tdkphy.c

147

struct mii_data *mii = phy->mii_pdata;

sys/dev/mii/tdkphy.c

154

bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);

sys/dev/mii/tdkphy.c

158

bmcr = PHY_READ(phy, MII_BMCR);

sys/dev/mii/tdkphy.c

180

anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);

sys/dev/mii/tdkphy.c

203

diag = PHY_READ(phy, MII_DIAG);

sys/dev/mii/tdkphy.c

218

mii->mii_media_active |= mii_phy_flowstatus(phy);

sys/dev/mii/ukphy_subr.c

126

mii->mii_media_active |= mii_phy_flowstatus(phy);

sys/dev/mii/ukphy_subr.c

59

ukphy_status(struct mii_softc *phy)

sys/dev/mii/ukphy_subr.c

61

struct mii_data *mii = phy->mii_pdata;

sys/dev/mii/ukphy_subr.c

68

bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);

sys/dev/mii/ukphy_subr.c

72

bmcr = PHY_READ(phy, MII_BMCR);

sys/dev/mii/ukphy_subr.c

94

anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);

sys/dev/mii/ukphy_subr.c

95

if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &&

sys/dev/mii/ukphy_subr.c

96

(phy->mii_extcapabilities &

sys/dev/mii/ukphy_subr.c

98

gtcr = PHY_READ(phy, MII_100T2CR);

sys/dev/mii/ukphy_subr.c

99

gtsr = PHY_READ(phy, MII_100T2SR);

sys/dev/mpr/mpr_sas_lsi.c

211

MPI2_EVENT_SAS_TOPO_PHY_ENTRY *phy;

sys/dev/mpr/mpr_sas_lsi.c

220

phy = &data->PHY[i];

sys/dev/mpr/mpr_sas_lsi.c

221

switch (phy->PhyStatus & MPI2_EVENT_SAS_TOPO_RC_MASK) {

sys/dev/mpr/mpr_sas_lsi.c

224

le16toh(phy->AttachedDevHandle),

sys/dev/mpr/mpr_sas_lsi.c

225

phy->LinkRate)) {

sys/dev/mpr/mpr_sas_lsi.c

229

le16toh(phy->AttachedDevHandle));

sys/dev/mpr/mpr_sas_lsi.c

231

phy->AttachedDevHandle));

sys/dev/mpr/mpr_sas_lsi.c

236

phy->AttachedDevHandle));

sys/dev/mpr/mpr_table.c

392

MPI2_EVENT_SAS_TOPO_PHY_ENTRY *phy;

sys/dev/mpr/mpr_table.c

407

phy = &data->PHY[i];

sys/dev/mpr/mpr_table.c

411

le16toh(phy->AttachedDevHandle));

sys/dev/mpr/mpr_table.c

415

(phy->LinkRate >> 4) & 0xf), phy->LinkRate);

sys/dev/mpr/mpr_table.c

418

phy->PhyStatus));

sys/dev/mps/mps_sas_lsi.c

208

MPI2_EVENT_SAS_TOPO_PHY_ENTRY *phy;

sys/dev/mps/mps_sas_lsi.c

217

phy = &data->PHY[i];

sys/dev/mps/mps_sas_lsi.c

218

switch (phy->PhyStatus & MPI2_EVENT_SAS_TOPO_RC_MASK) {

sys/dev/mps/mps_sas_lsi.c

221

le16toh(phy->AttachedDevHandle),

sys/dev/mps/mps_sas_lsi.c

222

phy->LinkRate)){

sys/dev/mps/mps_sas_lsi.c

226

le16toh(phy->AttachedDevHandle));

sys/dev/mps/mps_sas_lsi.c

228

phy->AttachedDevHandle));

sys/dev/mps/mps_sas_lsi.c

233

phy->AttachedDevHandle));

sys/dev/mps/mps_table.c

371

MPI2_EVENT_SAS_TOPO_PHY_ENTRY *phy;

sys/dev/mps/mps_table.c

386

phy = &data->PHY[i];

sys/dev/mps/mps_table.c

390

phy->AttachedDevHandle);

sys/dev/mps/mps_table.c

394

(phy->LinkRate >> 4) & 0xf), phy->LinkRate);

sys/dev/mps/mps_table.c

397

phy->PhyStatus));

sys/dev/msk/if_msk.c

397

msk_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/msk/if_msk.c

403

return (msk_phy_readreg(sc_if, phy, reg));

sys/dev/msk/if_msk.c

407

msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg)

sys/dev/msk/if_msk.c

415

GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

sys/dev/msk/if_msk.c

435

msk_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/msk/if_msk.c

441

return (msk_phy_writereg(sc_if, phy, reg, val));

sys/dev/msk/if_msk.c

445

msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val)

sys/dev/msk/if_msk.c

454

GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));

sys/dev/neta/if_mvneta.c

875

mvneta_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/neta/if_mvneta.c

898

smi = MVNETA_SMI_PHYAD(phy) |

sys/dev/neta/if_mvneta.c

936

CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", if_getname(ifp), phy,

sys/dev/neta/if_mvneta.c

943

mvneta_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/neta/if_mvneta.c

954

phy, reg, val);

sys/dev/neta/if_mvneta.c

970

smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) |

sys/dev/neta/if_mvnetareg.h

346

#define MVNETA_PHYADDR_PHYAD(phy) ((phy) & 0x1f)

sys/dev/neta/if_mvnetareg.h

351

#define MVNETA_SMI_PHYAD(phy) (((phy) & 0x1f) << 16)

sys/dev/nfe/if_nfe.c

1006

nfe_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/nfe/if_nfe.c

1019

NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);

sys/dev/nfe/if_nfe.c

1038

sc->mii_phyaddr = phy;

sys/dev/nfe/if_nfe.c

1040

DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);

sys/dev/nfe/if_nfe.c

1046

nfe_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/nfe/if_nfe.c

1060

ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;

sys/dev/nfe/if_nfe.c

916

uint32_t link, misc, phy, seed;

sys/dev/nfe/if_nfe.c

921

phy = NFE_READ(sc, NFE_PHY_IFACE);

sys/dev/nfe/if_nfe.c

922

phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);

sys/dev/nfe/if_nfe.c

931

phy |= NFE_PHY_HDX; /* half-duplex */

sys/dev/nfe/if_nfe.c

939

phy |= NFE_PHY_1000T;

sys/dev/nfe/if_nfe.c

944

phy |= NFE_PHY_100TX;

sys/dev/nfe/if_nfe.c

952

if ((phy & 0x10000000) != 0) {

sys/dev/nfe/if_nfe.c

963

NFE_WRITE(sc, NFE_PHY_IFACE, phy);

sys/dev/nge/if_nge.c

411

nge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/nge/if_nge.c

419

if (phy != 0)

sys/dev/nge/if_nge.c

457

return (mii_bitbang_readreg(dev, &nge_mii_bitbang_ops, phy, reg));

sys/dev/nge/if_nge.c

461

nge_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/nge/if_nge.c

468

if (phy != 0)

sys/dev/nge/if_nge.c

500

mii_bitbang_writereg(dev, &nge_mii_bitbang_ops, phy, reg, data);

sys/dev/otus/if_otus.c

1484

le32toh(tx->phy));

sys/dev/otus/if_otusreg.h

352

uint32_t phy;

sys/dev/pci/pci_dw_mv.c

108

rv = phy_get_by_ofw_idx(sc->dev, sc->node, i, &(sc->phy[i]));

sys/dev/pci/pci_dw_mv.c

118

if (sc->phy[i] == NULL)

sys/dev/pci/pci_dw_mv.c

120

rv = phy_enable(sc->phy[i]);

sys/dev/pci/pci_dw_mv.c

130

if (sc->phy[i] == NULL)

sys/dev/pci/pci_dw_mv.c

132

phy_release(sc->phy[i]);

sys/dev/pci/pci_dw_mv.c

91

phy_t phy[MV_MAX_LANES];

sys/dev/phy/phy.c

315

struct phy *phy;

sys/dev/phy/phy.c

319

phy = malloc(sizeof(struct phy), M_PHY, M_WAITOK | M_ZERO);

sys/dev/phy/phy.c

320

phy->cdev = cdev;

sys/dev/phy/phy.c

321

phy->phynode = phynode;

sys/dev/phy/phy.c

322

phy->enable_cnt = 0;

sys/dev/phy/phy.c

326

TAILQ_INSERT_TAIL(&phynode->consumers_list, phy, link);

sys/dev/phy/phy.c

329

return (phy);

sys/dev/phy/phy.c

333

phy_enable(phy_t phy)

sys/dev/phy/phy.c

338

phynode = phy->phynode;

sys/dev/phy/phy.c

345

phy->enable_cnt++;

sys/dev/phy/phy.c

351

phy_disable(phy_t phy)

sys/dev/phy/phy.c

356

phynode = phy->phynode;

sys/dev/phy/phy.c

359

KASSERT(phy->enable_cnt > 0,

sys/dev/phy/phy.c

365

phy->enable_cnt--;

sys/dev/phy/phy.c

371

phy_set_mode(phy_t phy, phy_mode_t mode, phy_submode_t submode)

sys/dev/phy/phy.c

376

phynode = phy->phynode;

sys/dev/phy/phy.c

387

phy_status(phy_t phy, int *status)

sys/dev/phy/phy.c

392

phynode = phy->phynode;

sys/dev/phy/phy.c

404

phy_t *phy)

sys/dev/phy/phy.c

415

*phy = phy_create(phynode, consumer_dev);

sys/dev/phy/phy.c

422

phy_release(phy_t phy)

sys/dev/phy/phy.c

426

phynode = phy->phynode;

sys/dev/phy/phy.c

431

while (phy->enable_cnt > 0) {

sys/dev/phy/phy.c

433

phy->enable_cnt--;

sys/dev/phy/phy.c

436

TAILQ_REMOVE(&phynode->consumers_list, phy, link);

sys/dev/phy/phy.c

441

free(phy, M_PHY);

sys/dev/phy/phy.c

479

phy_get_by_ofw_idx(device_t consumer_dev, phandle_t cnode, int idx, phy_t *phy)

sys/dev/phy/phy.c

511

return (phy_get_by_id(consumer_dev, phydev, id, phy));

sys/dev/phy/phy.c

516

phy_t *phy)

sys/dev/phy/phy.c

530

return (phy_get_by_ofw_idx(consumer_dev, cnode, idx, phy));

sys/dev/phy/phy.c

535

phy_t *phy)

sys/dev/phy/phy.c

566

return (phy_get_by_id(consumer_dev, phydev, id, phy));

sys/dev/phy/phy.h

138

phy_t *phy);

sys/dev/phy/phy.h

139

void phy_release(phy_t phy);

sys/dev/phy/phy.h

140

int phy_enable(phy_t phy);

sys/dev/phy/phy.h

141

int phy_disable(phy_t phy);

sys/dev/phy/phy.h

142

int phy_set_mode(phy_t phy, phy_mode_t mode, phy_submode_t submode);

sys/dev/phy/phy.h

143

int phy_status(phy_t phy, int *value);

sys/dev/phy/phy.h

146

phy_t *phy);

sys/dev/phy/phy.h

147

int phy_get_by_ofw_idx(device_t consumer, phandle_t node, int idx, phy_t *phy);

sys/dev/phy/phy.h

149

phy_t *phy);

sys/dev/phy/phy.h

95

typedef struct phy *phy_t;

sys/dev/phy/phy_internal.h

30

struct phy;

sys/dev/phy/phy_internal.h

34

typedef TAILQ_HEAD(phy_list, phy) phy_list_t;

sys/dev/phy/phy_internal.h

63

TAILQ_ENTRY(phy) link; /* Consumers list entry */

sys/dev/phy/phy_usb.c

117

int phy_usb_set_mode(phy_t phy, int usb_mode)

sys/dev/phy/phy_usb.c

122

phynode = phy->phynode;

sys/dev/phy/phy_usb.c

132

int phy_usb_get_mode(phy_t phy, int *usb_mode)

sys/dev/phy/phy_usb.c

137

phynode = phy->phynode;

sys/dev/phy/phy_usb.h

80

int phy_usb_set_mode(phy_t phy, int usb_mode);

sys/dev/phy/phy_usb.h

81

int phy_usb_get_mode(phy_t phy, int *usb_mode);

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4198

bit32 AnalogTableBase,CFGTableOffset, value,phy;

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4217

for(phy = 0; phy < 10; phy++) /* upto 10 phys See PM*/

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4219

ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 0 ),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister0 );

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4220

ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 4 ),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister1 );

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4221

ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 8 ),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister2 );

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4222

ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 12),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister3 );

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4223

ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 16),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister4 );

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4224

ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 20),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister5 );

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4225

ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 24),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister6 );

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4226

ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 28),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister7 );

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4227

ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 32),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister8 );

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4228

ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 36),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister9 );

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4230

SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister0 0x%x 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) + 0,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister0 ,ossaHwRegReadExt(agRoot, pcibar,AnalogTableBase + ( AnalogtableSize * phy)+ 0 )));

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4231

SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister1 0x%x 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) + 4,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister1 ,ossaHwRegReadExt(agRoot, pcibar,AnalogTableBase + ( AnalogtableSize * phy)+ 4 )));

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4232

SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister2 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) + 8,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister2 ));

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4233

SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister3 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +12,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister3 ));

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4234

SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister4 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +16,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister4 ));

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4235

SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister5 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +20,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister5 ));

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4236

SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister6 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +24,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister6 ));

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4237

SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister7 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +28,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister7 ));

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4238

SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister8 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +32,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister8 ));

sys/dev/pms/RefTisa/sallsdk/spc/sainit.c

4239

SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister9 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +36,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister9 ));

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

180

int phy, int reg)

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

186

((phy & 0xff) << 8) | (reg & 0xff));

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

191

qcom_mdio_ipq4018_readreg(device_t dev, int phy, int reg)

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

198

__func__, phy, reg);

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

207

qcom_mdio_ipq4018_set_phy_reg_addr(sc, phy, reg);

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

233

qcom_mdio_ipq4018_writereg(device_t dev, int phy, int reg, int value)

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

239

__func__, phy, reg, value);

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

248

qcom_mdio_ipq4018_set_phy_reg_addr(sc, phy, reg);

sys/dev/ral/rt2860.c

1188

uint16_t phy;

sys/dev/ral/rt2860.c

1295

phy = le16toh(rxwi->phy);

sys/dev/ral/rt2860.c

1296

switch (phy & RT2860_PHY_MODE) {

sys/dev/ral/rt2860.c

1298

switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) {

sys/dev/ral/rt2860.c

1304

if (phy & RT2860_PHY_SHPRE)

sys/dev/ral/rt2860.c

1308

switch (phy & RT2860_PHY_MCS) {

sys/dev/ral/rt2860.c

1525

if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {

sys/dev/ral/rt2860.c

1526

txwi->phy = htole16(RT2860_PHY_CCK);

sys/dev/ral/rt2860.c

1531

txwi->phy = htole16(RT2860_PHY_OFDM);

sys/dev/ral/rt2860.c

1532

txwi->phy |= htole16(mcs);

sys/dev/ral/rt2860.c

1548

rt2860_rates[ridx].phy == IEEE80211_T_OFDM)))

sys/dev/ral/rt2860.c

1773

if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {

sys/dev/ral/rt2860.c

1774

txwi->phy = htole16(RT2860_PHY_CCK);

sys/dev/ral/rt2860.c

1779

txwi->phy = htole16(RT2860_PHY_OFDM);

sys/dev/ral/rt2860.c

1780

txwi->phy |= htole16(mcs);

sys/dev/ral/rt2860.c

4286

txwi.phy = htole16(rt2860_rates[ridx].mcs);

sys/dev/ral/rt2860.c

4287

if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM)

sys/dev/ral/rt2860.c

4288

txwi.phy |= htole16(RT2860_PHY_OFDM);

sys/dev/ral/rt2860reg.h

819

uint16_t phy;

sys/dev/ral/rt2860reg.h

889

uint16_t phy;

sys/dev/ral/rt2860reg.h

975

enum ieee80211_phytype phy;

sys/dev/re/if_re.c

1225

phy, reg, rid;

sys/dev/re/if_re.c

1670

phy = RE_PHYAD_INTERNAL;

sys/dev/re/if_re.c

1672

phy = 1;

sys/dev/re/if_re.c

1677

re_ifmedia_sts, capmask, phy, MII_OFFSET_ANY, MIIF_DOPAUSE);

sys/dev/re/if_re.c

451

re_gmii_readreg(device_t dev, int phy, int reg)

sys/dev/re/if_re.c

489

re_gmii_writereg(device_t dev, int phy, int reg, int data)

sys/dev/re/if_re.c

521

re_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/re/if_re.c

530

rval = re_gmii_readreg(dev, phy, reg);

sys/dev/re/if_re.c

575

re_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/re/if_re.c

584

rval = re_gmii_writereg(dev, phy, reg, data);

sys/dev/rl/if_rl.c

388

rl_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/rl/if_rl.c

430

return (mii_bitbang_readreg(dev, &rl_mii_bitbang_ops, phy, reg));

sys/dev/rl/if_rl.c

434

rl_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/rl/if_rl.c

470

mii_bitbang_writereg(dev, &rl_mii_bitbang_ops, phy, reg, data);

sys/dev/rl/if_rl.c

643

int error = 0, hwrev, i, phy, rid;

sys/dev/rl/if_rl.c

787

phy = MII_PHY_ANY;

sys/dev/rl/if_rl.c

789

phy = RL_PHYAD_INTERNAL;

sys/dev/rl/if_rl.c

791

rl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);

sys/dev/rtwn/rtl8188e/r88e_rx.c

164

struct r88e_rx_phystat *phy = (struct r88e_rx_phystat *)physt;

sys/dev/rtwn/rtl8188e/r88e_rx.c

167

lna_idx = (phy->agc_rpt & 0xe0) >> 5;

sys/dev/rtwn/rtl8188e/r88e_rx.c

168

vga_idx = (phy->agc_rpt & 0x1f);

sys/dev/rtwn/rtl8188e/r88e_rx.c

209

struct r88e_rx_phystat *phy = (struct r88e_rx_phystat *)physt;

sys/dev/rtwn/rtl8188e/r88e_rx.c

213

rssi = ((phy->sig_qual >> 1) & 0x7f) - 110;

sys/dev/rtwn/rtl8192c/r92c_rx.c

82

struct r92c_rx_phystat *phy = (struct r92c_rx_phystat *)physt;

sys/dev/rtwn/rtl8192c/r92c_rx.c

86

rssi = ((phy->pwdb_all >> 1) & 0x7f) - 110;

sys/dev/sdhci/sdhci_fdt.c

219

error = phy_get_by_ofw_name(sc->dev, 0, "phy_arasan", &sc->phy);

sys/dev/sdhci/sdhci_fdt.c

226

error = phy_enable(sc->phy);

sys/dev/sdhci/sdhci_fdt.h

51

phy_t phy; /* phy to be used */

sys/dev/sge/if_sge.c

329

sge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/sge/if_sge.c

336

CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |

sys/dev/sge/if_sge.c

353

sge_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/sge/if_sge.c

360

CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |

sys/dev/sis/if_sis.c

468

sis_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/sis/if_sis.c

475

if (phy != 0)

sys/dev/sis/if_sis.c

501

if (phy != 0)

sys/dev/sis/if_sis.c

505

(phy << 11) | (reg << 6) | SIS_PHYOP_READ);

sys/dev/sis/if_sis.c

526

return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy,

sys/dev/sis/if_sis.c

531

sis_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/sis/if_sis.c

538

if (phy != 0)

sys/dev/sis/if_sis.c

553

if (phy != 0)

sys/dev/sis/if_sis.c

556

CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |

sys/dev/sis/if_sis.c

569

mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg,

sys/dev/sk/if_sk.c

1253

int error, i, phy, port;

sys/dev/sk/if_sk.c

1437

phy = MII_PHY_ANY;

sys/dev/sk/if_sk.c

1442

phy = 0;

sys/dev/sk/if_sk.c

1448

phy = 0;

sys/dev/sk/if_sk.c

1454

sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);

sys/dev/sk/if_sk.c

3224

u_int32_t phy, v;

sys/dev/sk/if_sk.c

3264

phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |

sys/dev/sk/if_sk.c

3268

phy |= SK_GPHY_COPPER;

sys/dev/sk/if_sk.c

3270

phy |= SK_GPHY_FIBER;

sys/dev/sk/if_sk.c

3272

SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);

sys/dev/sk/if_sk.c

3274

SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);

sys/dev/sk/if_sk.c

432

sk_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/sk/if_sk.c

442

v = sk_xmac_miibus_readreg(sc_if, phy, reg);

sys/dev/sk/if_sk.c

447

v = sk_marv_miibus_readreg(sc_if, phy, reg);

sys/dev/sk/if_sk.c

459

sk_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/sk/if_sk.c

469

v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);

sys/dev/sk/if_sk.c

474

v = sk_marv_miibus_writereg(sc_if, phy, reg, val);

sys/dev/sk/if_sk.c

509

sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)

sys/dev/sk/if_sk.c

513

SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));

sys/dev/sk/if_sk.c

535

sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)

sys/dev/sk/if_sk.c

539

SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));

sys/dev/sk/if_sk.c

583

sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)

sys/dev/sk/if_sk.c

593

SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |

sys/dev/sk/if_sk.c

614

sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)

sys/dev/sk/if_sk.c

619

SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |

sys/dev/smc/if_smc.c

1003

smc_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/smc/if_smc.c

1014

val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg);

sys/dev/smc/if_smc.c

1021

smc_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/smc/if_smc.c

1031

mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data);

sys/dev/ste/if_ste.c

234

ste_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/ste/if_ste.c

237

return (mii_bitbang_readreg(dev, &ste_mii_bitbang_ops, phy, reg));

sys/dev/ste/if_ste.c

241

ste_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/ste/if_ste.c

244

mii_bitbang_writereg(dev, &ste_mii_bitbang_ops, phy, reg, data);

sys/dev/ste/if_ste.c

908

int error = 0, phy, prefer_iomap, rid;

sys/dev/ste/if_ste.c

992

phy = MII_PHY_ANY;

sys/dev/ste/if_ste.c

994

phy = 0;

sys/dev/ste/if_ste.c

996

ste_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);

sys/dev/stge/if_stge.c

284

stge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/stge/if_stge.c

300

val = mii_bitbang_readreg(dev, &stge_mii_bitbang_ops, phy, reg);

sys/dev/stge/if_stge.c

311

stge_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/stge/if_stge.c

318

mii_bitbang_writereg(dev, &stge_mii_bitbang_ops, phy, reg, val);

sys/dev/tsec/if_tsec.c

1563

tsec_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/tsec/if_tsec.c

1572

TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);

sys/dev/tsec/if_tsec.c

1587

tsec_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/tsec/if_tsec.c

1595

TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);

sys/dev/tsec/if_tsec.h

298

int tsec_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/tsec/if_tsec.h

299

int tsec_miibus_writereg(device_t dev, int phy, int reg, int value);

sys/dev/tsec/if_tsec_fdt.c

166

phandle_t child, mdio, phy;

sys/dev/tsec/if_tsec_fdt.c

191

if (OF_getencprop(sc->node, "phy-handle", &phy, sizeof(phy)) <= 0) {

sys/dev/tsec/if_tsec_fdt.c

196

phy = OF_node_from_xref(phy);

sys/dev/tsec/if_tsec_fdt.c

197

mdio = OF_parent(phy);

sys/dev/tsec/if_tsec_fdt.c

199

OF_getencprop(phy, "reg", &sc->phyaddr, sizeof(sc->phyaddr));

sys/dev/usb/controller/generic_ehci_fdt.c

114

phy_t phy;

sys/dev/usb/controller/generic_ehci_fdt.c

148

for (off = 0; phy_get_by_ofw_idx(dev, 0, off, &phy) == 0; off++) {

sys/dev/usb/controller/generic_ehci_fdt.c

149

err = phy_usb_set_mode(phy, PHY_USB_MODE_HOST);

sys/dev/usb/controller/generic_ehci_fdt.c

154

err = phy_enable(phy);

sys/dev/usb/controller/generic_ehci_fdt.c

160

phyp->phy = phy;

sys/dev/usb/controller/generic_ehci_fdt.c

181

struct phy_list *phy, *phy_tmp;

sys/dev/usb/controller/generic_ehci_fdt.c

213

TAILQ_FOREACH_SAFE(phy, &sc->phy_list, next, phy_tmp) {

sys/dev/usb/controller/generic_ehci_fdt.c

214

err = phy_disable(phy->phy);

sys/dev/usb/controller/generic_ehci_fdt.c

217

phy_release(phy->phy);

sys/dev/usb/controller/generic_ehci_fdt.c

218

TAILQ_REMOVE(&sc->phy_list, phy, next);

sys/dev/usb/controller/generic_ehci_fdt.c

219

free(phy, M_DEVBUF);

sys/dev/usb/controller/generic_ehci_fdt.c

75

phy_t phy;

sys/dev/usb/controller/generic_ohci.c

111

phy_t phy;

sys/dev/usb/controller/generic_ohci.c

191

for (off = 0; phy_get_by_ofw_idx(dev, 0, off, &phy) == 0; off++) {

sys/dev/usb/controller/generic_ohci.c

192

err = phy_usb_set_mode(phy, PHY_USB_MODE_HOST);

sys/dev/usb/controller/generic_ohci.c

197

err = phy_enable(phy);

sys/dev/usb/controller/generic_ohci.c

203

phyp->phy = phy;

sys/dev/usb/controller/generic_ohci.c

230

struct phy_list *phy, *phy_tmp;

sys/dev/usb/controller/generic_ohci.c

273

TAILQ_FOREACH_SAFE(phy, &sc->phy_list, next, phy_tmp) {

sys/dev/usb/controller/generic_ohci.c

274

err = phy_disable(phy->phy);

sys/dev/usb/controller/generic_ohci.c

277

phy_release(phy->phy);

sys/dev/usb/controller/generic_ohci.c

278

TAILQ_REMOVE(&sc->phy_list, phy, next);

sys/dev/usb/controller/generic_ohci.c

279

free(phy, M_DEVBUF);

sys/dev/usb/controller/generic_ohci.c

69

phy_t phy;

sys/dev/usb/controller/generic_xhci_fdt.c

108

phy_t phy;

sys/dev/usb/controller/generic_xhci_fdt.c

116

if (phy_get_by_ofw_property(dev, node, "usb-phy", &phy) == 0)

sys/dev/usb/controller/generic_xhci_fdt.c

117

phy_release(phy);

sys/dev/usb/controller/generic_xhci_fdt.c

89

phy_t phy;

sys/dev/usb/controller/generic_xhci_fdt.c

93

if (phy_get_by_ofw_property(dev, node, "usb-phy", &phy) == 0)

sys/dev/usb/controller/generic_xhci_fdt.c

94

if (phy_enable(phy) != 0)

sys/dev/usb/controller/musb_otg_allwinner.c

123

phy_t phy;

sys/dev/usb/controller/musb_otg_allwinner.c

447

(void)phy_get_by_ofw_name(dev, 0, "usb", &sc->phy);

sys/dev/usb/controller/musb_otg_allwinner.c

448

if (sc->phy != NULL) {

sys/dev/usb/controller/musb_otg_allwinner.c

451

error = phy_enable(sc->phy);

sys/dev/usb/controller/musb_otg_allwinner.c

457

error = phy_usb_set_mode(sc->phy, phy_mode);

sys/dev/usb/controller/musb_otg_allwinner.c

546

if (sc->phy != NULL) {

sys/dev/usb/controller/musb_otg_allwinner.c

548

(void)phy_disable(sc->phy);

sys/dev/usb/controller/musb_otg_allwinner.c

549

phy_release(sc->phy);

sys/dev/usb/controller/musb_otg_allwinner.c

580

if (sc->phy != NULL) {

sys/dev/usb/controller/musb_otg_allwinner.c

582

phy_disable(sc->phy);

sys/dev/usb/controller/musb_otg_allwinner.c

583

phy_release(sc->phy);

sys/dev/usb/controller/usb_nop_xceiv.c

63

static int usb_nop_xceiv_phy_enable(struct phynode *phy, bool enable);

sys/dev/usb/controller/usb_nop_xceiv.c

78

intptr_t phy;

sys/dev/usb/controller/usb_nop_xceiv.c

82

phy = phynode_get_id(phynode);

sys/dev/usb/controller/usb_nop_xceiv.c

85

if (phy != 0)

sys/dev/usb/net/if_aue.c

419

aue_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_aue.c

437

if (phy == 3)

sys/dev/usb/net/if_aue.c

440

if (phy != 1)

sys/dev/usb/net/if_aue.c

444

aue_csr_write_1(sc, AUE_PHY_ADDR, phy);

sys/dev/usb/net/if_aue.c

466

aue_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/usb/net/if_aue.c

472

if (phy == 3)

sys/dev/usb/net/if_aue.c

480

aue_csr_write_1(sc, AUE_PHY_ADDR, phy);

sys/dev/usb/net/if_axe.c

318

axe_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_axe.c

329

axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);

sys/dev/usb/net/if_axe.c

349

axe_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/usb/net/if_axe.c

360

axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);

sys/dev/usb/net/if_axge.c

288

axge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_axge.c

299

val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy);

sys/dev/usb/net/if_axge.c

308

axge_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/usb/net/if_axge.c

318

axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val);

sys/dev/usb/net/if_mos.c

421

mos_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_mos.c

431

mos_reg_write_1(sc, MOS_PHY_CTL, (phy & MOS_PHYCTL_PHYADDR) |

sys/dev/usb/net/if_mos.c

451

mos_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/usb/net/if_mos.c

461

mos_reg_write_1(sc, MOS_PHY_CTL, (phy & MOS_PHYCTL_PHYADDR) |

sys/dev/usb/net/if_muge.c

654

lan78xx_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_muge.c

671

addr = (phy << 11) | (reg << 6) |

sys/dev/usb/net/if_muge.c

707

lan78xx_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/usb/net/if_muge.c

713

if (sc->sc_phyno != phy)

sys/dev/usb/net/if_muge.c

729

addr = (phy << 11) | (reg << 6) |

sys/dev/usb/net/if_rue.c

310

rue_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_rue.c

317

if (phy != 0) /* RTL8150 supports PHY == 0, only */

sys/dev/usb/net/if_rue.c

362

rue_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/usb/net/if_rue.c

368

if (phy != 0) /* RTL8150 supports PHY == 0, only */

sys/dev/usb/net/if_smsc.c

443

smsc_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_smsc.c

459

addr = (phy << 11) | (reg << 6) | SMSC_MII_READ | SMSC_MII_BUSY;

sys/dev/usb/net/if_smsc.c

491

smsc_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/usb/net/if_smsc.c

497

if (sc->sc_phyno != phy)

sys/dev/usb/net/if_smsc.c

512

addr = (phy << 11) | (reg << 6) | SMSC_MII_WRITE | SMSC_MII_BUSY;

sys/dev/usb/net/if_udav.c

802

udav_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_udav.c

810

if (phy != 0)

sys/dev/usb/net/if_udav.c

835

phy, reg, data16);

sys/dev/usb/net/if_udav.c

843

udav_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/usb/net/if_udav.c

850

if (phy != 0)

sys/dev/usb/net/if_ure.c

404

ure_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_ure.c

430

ure_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/usb/net/if_ure.c

436

if (sc->sc_phyno != phy)

sys/dev/usb/net/ruephy.c

177

ruephy_status(struct mii_softc *phy)

sys/dev/usb/net/ruephy.c

179

struct mii_data *mii = phy->mii_pdata;

sys/dev/usb/net/ruephy.c

186

msr = PHY_READ(phy, RUEPHY_MII_MSR) | PHY_READ(phy, RUEPHY_MII_MSR);

sys/dev/usb/net/ruephy.c

190

bmcr = PHY_READ(phy, MII_BMCR);

sys/dev/usb/net/ruephy.c

197

bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);

sys/dev/usb/net/ruephy.c

212

IFM_FDX | mii_phy_flowstatus(phy);

sys/dev/usb/wlan/if_mtw.c

2487

uint16_t phy;

sys/dev/usb/wlan/if_mtw.c

2499

phy = le16toh(rxwi->phy);

sys/dev/usb/wlan/if_mtw.c

2500

switch (phy >> MT7601_PHY_SHIFT) {

sys/dev/usb/wlan/if_mtw.c

2502

switch ((phy & MTW_PHY_MCS) & ~MTW_PHY_SHPRE) {

sys/dev/usb/wlan/if_mtw.c

2516

if (phy & MTW_PHY_SHPRE)

sys/dev/usb/wlan/if_mtw.c

2520

switch (phy & MTW_PHY_MCS) {

sys/dev/usb/wlan/if_mtw.c

2798

if (le16toh(txwi->phy) & MTW_PHY_SHPRE)

sys/dev/usb/wlan/if_mtw.c

3034

if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {

sys/dev/usb/wlan/if_mtw.c

3039

} else if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) {

sys/dev/usb/wlan/if_mtw.c

3041

} else if (rt2860_rates[ridx].phy == IEEE80211_T_HT) {

sys/dev/usb/wlan/if_mtw.c

3045

txwi->phy = htole16(mcs);

sys/dev/usb/wlan/if_mtw.c

3051

rt2860_rates[ridx].phy == IEEE80211_T_OFDM) ||

sys/dev/usb/wlan/if_mtw.c

3053

rt2860_rates[ridx].phy == IEEE80211_T_HT)))

sys/dev/usb/wlan/if_mtw.c

3904

txwi.phy = htole16(rt2860_rates[ridx].mcs);

sys/dev/usb/wlan/if_mtw.c

3905

if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM)

sys/dev/usb/wlan/if_mtw.c

3906

txwi.phy |= htole16(MTW_PHY_OFDM);

sys/dev/usb/wlan/if_mtwreg.h

795

uint16_t phy;

sys/dev/usb/wlan/if_mtwreg.h

874

uint16_t phy;

sys/dev/usb/wlan/if_mtwreg.h

964

enum ieee80211_phytype phy;

sys/dev/usb/wlan/if_rsu.c

2299

struct r92s_rx_phystat *phy;

sys/dev/usb/wlan/if_rsu.c

2310

phy = (struct r92s_rx_phystat *)physt;

sys/dev/usb/wlan/if_rsu.c

2311

rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 106;

sys/dev/usb/wlan/if_run.c

2965

uint16_t phy;

sys/dev/usb/wlan/if_run.c

2977

phy = le16toh(rxwi->phy);

sys/dev/usb/wlan/if_run.c

2978

switch (phy & RT2860_PHY_MODE) {

sys/dev/usb/wlan/if_run.c

2980

switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) {

sys/dev/usb/wlan/if_run.c

2986

if (phy & RT2860_PHY_SHPRE)

sys/dev/usb/wlan/if_run.c

2990

switch (phy & RT2860_PHY_MCS) {

sys/dev/usb/wlan/if_run.c

3253

if (le16toh(txwi->phy) & RT2860_PHY_SHPRE)

sys/dev/usb/wlan/if_run.c

3397

if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {

sys/dev/usb/wlan/if_run.c

3402

} else if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) {

sys/dev/usb/wlan/if_run.c

3404

} else if (rt2860_rates[ridx].phy == IEEE80211_T_HT) {

sys/dev/usb/wlan/if_run.c

3408

txwi->phy = htole16(mcs);

sys/dev/usb/wlan/if_run.c

3414

rt2860_rates[ridx].phy == IEEE80211_T_OFDM) ||

sys/dev/usb/wlan/if_run.c

3416

rt2860_rates[ridx].phy == IEEE80211_T_HT)))

sys/dev/usb/wlan/if_run.c

5087

txwi.phy = htole16(rt2860_rates[ridx].mcs);

sys/dev/usb/wlan/if_run.c

5088

if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM)

sys/dev/usb/wlan/if_run.c

5089

txwi.phy |= htole16(RT2860_PHY_OFDM);

sys/dev/usb/wlan/if_run.c

510

enum ieee80211_phytype phy;

sys/dev/usb/wlan/if_runreg.h

777

uint16_t phy;

sys/dev/usb/wlan/if_runreg.h

847

uint16_t phy;

sys/dev/usb/wlan/if_zyd.c

1072

static const struct zyd_phy_pair phy[] = ZYD_AL2230_PHY_FINI_PART1;

sys/dev/usb/wlan/if_zyd.c

1074

for (i = 0; i < nitems(phy); i++)

sys/dev/usb/wlan/if_zyd.c

1075

zyd_write16_m(sc, phy[i].reg, phy[i].val);

sys/dev/usb/wlan/if_zyd.c

2440

uint8_t phy;

sys/dev/usb/wlan/if_zyd.c

2485

phy = zyd_plcp_signal(sc, rate);

sys/dev/usb/wlan/if_zyd.c

2486

desc->phy = phy;

sys/dev/usb/wlan/if_zyd.c

2488

desc->phy |= ZYD_TX_PHY_OFDM;

sys/dev/usb/wlan/if_zyd.c

2490

desc->phy |= ZYD_TX_PHY_5GHZ;

sys/dev/usb/wlan/if_zyd.c

2492

desc->phy |= ZYD_TX_PHY_SHPREAMBLE;

sys/dev/usb/wlan/if_zyd.c

2522

desc->plcp_length = htole16(bits / ratediv[phy]);

sys/dev/usb/wlan/if_zydreg.h

1028

uint8_t phy;

sys/dev/vge/if_vge.c

358

vge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/vge/if_vge.c

392

vge_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/vnic/thunder_bgx_fdt.c

372

phandle_t phy, mdio;

sys/dev/vnic/thunder_bgx_fdt.c

418

if (OF_getencprop(child, "phy-handle", &phy,

sys/dev/vnic/thunder_bgx_fdt.c

419

sizeof(phy)) <= 0) {

sys/dev/vnic/thunder_bgx_fdt.c

426

phy = OF_instance_to_package(phy);

sys/dev/vnic/thunder_bgx_fdt.c

431

mdio = OF_parent(phy);

sys/dev/vnic/thunder_bgx_fdt.c

73

bgx_fdt_get_macaddr(phandle_t phy, uint8_t *hwaddr)

sys/dev/vnic/thunder_bgx_fdt.c

77

if (OF_getprop(phy, "local-mac-address", addr, ETHER_ADDR_LEN) == -1) {

sys/dev/vnic/thunder_mdio.c

212

thunder_mdio_c45_addr(struct thunder_mdio_softc *sc, int phy, int reg)

sys/dev/vnic/thunder_mdio.c

229

smi_cmd |= ((phy << SMI_CMD_PHY_ADR_SHIFT) & SMI_CMD_PHY_ADR_MASK);

sys/dev/vnic/thunder_mdio.c

252

thunder_mdio_read(device_t dev, int phy, int reg)

sys/dev/vnic/thunder_mdio.c

273

err = thunder_mdio_c45_addr(sc, phy, reg);

sys/dev/vnic/thunder_mdio.c

281

smi_cmd |= ((phy << SMI_CMD_PHY_ADR_SHIFT) & SMI_CMD_PHY_ADR_MASK);

sys/dev/vnic/thunder_mdio.c

304

thunder_mdio_write(device_t dev, int phy, int reg, int data)

sys/dev/vnic/thunder_mdio.c

328

smi_cmd |= ((phy << SMI_CMD_PHY_ADR_SHIFT) & SMI_CMD_PHY_ADR_MASK);

sys/dev/vnic/thunder_mdio.c

440

thunder_mdio_phy_connect(device_t dev, int lmacid, int phy)

sys/dev/vnic/thunder_mdio.c

461

BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);

sys/dev/vnic/thunder_mdio.c

464

device_printf(dev, "Could not attach PHY%d\n", phy);

sys/dev/vnic/thunder_mdio.c

478

thunder_mdio_phy_disconnect(device_t dev, int lmacid, int phy)

sys/dev/vr/if_vr.c

240

vr_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/vr/if_vr.c

257

device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg);

sys/dev/vr/if_vr.c

263

vr_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/vr/if_vr.c

281

device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy,

sys/dev/vr/if_vr.c

610

int i, phy;

sys/dev/vr/if_vr.c

773

phy = 1;

sys/dev/vr/if_vr.c

775

phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK;

sys/dev/vr/if_vr.c

777

vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,

sys/dev/vte/if_vte.c

168

vte_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/vte/if_vte.c

176

(phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));

sys/dev/vte/if_vte.c

192

vte_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/vte/if_vte.c

201

(phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));

sys/dev/xilinx/if_xae.c

834

xae_miibus_read_reg(device_t dev, int phy, int reg)

sys/dev/xilinx/if_xae.c

847

mii |= (phy << MDIO_TX_PHYAD_S);

sys/dev/xilinx/if_xae.c

860

xae_miibus_write_reg(device_t dev, int phy, int reg, int val)

sys/dev/xilinx/if_xae.c

872

mii |= (phy << MDIO_TX_PHYAD_S);

sys/dev/xl/if_xl.c

1067

int error = 0, phy, rid, res;

sys/dev/xl/if_xl.c

1380

phy = MII_PHY_ANY;

sys/dev/xl/if_xl.c

1382

phy = 24;

sys/dev/xl/if_xl.c

1384

xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,

sys/dev/xl/if_xl.c

412

xl_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/xl/if_xl.c

421

return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg));

sys/dev/xl/if_xl.c

425

xl_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/xl/if_xl.c

434

mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data);

sys/net80211/ieee80211_phy.c

100

[8] = { .phy = OFDM, 24000, 0x00, 48, 8 },

sys/net80211/ieee80211_phy.c

101

[9] = { .phy = OFDM, 36000, 0x00, 72, 8 },

sys/net80211/ieee80211_phy.c

102

[10] = { .phy = OFDM, 48000, 0x00, 96, 8 },

sys/net80211/ieee80211_phy.c

103

[11] = { .phy = OFDM, 54000, 0x00, 108, 8 }

sys/net80211/ieee80211_phy.c

112

[0] = { .phy = OFDM, 6000, 0x00, B(12), 0 },

sys/net80211/ieee80211_phy.c

113

[1] = { .phy = OFDM, 9000, 0x00, 18, 0 },

sys/net80211/ieee80211_phy.c

114

[2] = { .phy = OFDM, 12000, 0x00, B(24), 2 },

sys/net80211/ieee80211_phy.c

115

[3] = { .phy = OFDM, 18000, 0x00, 36, 2 },

sys/net80211/ieee80211_phy.c

116

[4] = { .phy = OFDM, 24000, 0x00, B(48), 4 },

sys/net80211/ieee80211_phy.c

117

[5] = { .phy = OFDM, 36000, 0x00, 72, 4 },

sys/net80211/ieee80211_phy.c

118

[6] = { .phy = OFDM, 48000, 0x00, 96, 4 },

sys/net80211/ieee80211_phy.c

119

[7] = { .phy = OFDM, 54000, 0x00, 108, 4 }

sys/net80211/ieee80211_phy.c

128

[0] = { .phy = HALF, 3000, 0x00, B(6), 0 },

sys/net80211/ieee80211_phy.c

129

[1] = { .phy = HALF, 4500, 0x00, 9, 0 },

sys/net80211/ieee80211_phy.c

130

[2] = { .phy = HALF, 6000, 0x00, B(12), 2 },

sys/net80211/ieee80211_phy.c

131

[3] = { .phy = HALF, 9000, 0x00, 18, 2 },

sys/net80211/ieee80211_phy.c

132

[4] = { .phy = HALF, 12000, 0x00, B(24), 4 },

sys/net80211/ieee80211_phy.c

133

[5] = { .phy = HALF, 18000, 0x00, 36, 4 },

sys/net80211/ieee80211_phy.c

134

[6] = { .phy = HALF, 24000, 0x00, 48, 4 },

sys/net80211/ieee80211_phy.c

135

[7] = { .phy = HALF, 27000, 0x00, 54, 4 }

sys/net80211/ieee80211_phy.c

144

[0] = { .phy = QUART, 1500, 0x00, B(3), 0 },

sys/net80211/ieee80211_phy.c

145

[1] = { .phy = QUART, 2250, 0x00, 4, 0 },

sys/net80211/ieee80211_phy.c

146

[2] = { .phy = QUART, 3000, 0x00, B(9), 2 },

sys/net80211/ieee80211_phy.c

147

[3] = { .phy = QUART, 4500, 0x00, 9, 2 },

sys/net80211/ieee80211_phy.c

148

[4] = { .phy = QUART, 6000, 0x00, B(12), 4 },

sys/net80211/ieee80211_phy.c

149

[5] = { .phy = QUART, 9000, 0x00, 18, 4 },

sys/net80211/ieee80211_phy.c

150

[6] = { .phy = QUART, 12000, 0x00, 24, 4 },

sys/net80211/ieee80211_phy.c

151

[7] = { .phy = QUART, 13500, 0x00, 27, 4 }

sys/net80211/ieee80211_phy.c

160

[0] = { .phy = TURBO, 12000, 0x00, B(12), 0 },

sys/net80211/ieee80211_phy.c

161

[1] = { .phy = TURBO, 24000, 0x00, B(24), 1 },

sys/net80211/ieee80211_phy.c

162

[2] = { .phy = TURBO, 36000, 0x00, 36, 1 },

sys/net80211/ieee80211_phy.c

163

[3] = { .phy = TURBO, 48000, 0x00, B(48), 3 },

sys/net80211/ieee80211_phy.c

164

[4] = { .phy = TURBO, 72000, 0x00, 72, 3 },

sys/net80211/ieee80211_phy.c

165

[5] = { .phy = TURBO, 96000, 0x00, 96, 3 },

sys/net80211/ieee80211_phy.c

166

[6] = { .phy = TURBO, 108000, 0x00, 108, 3 }

sys/net80211/ieee80211_phy.c

175

[0] = { .phy = TURBO, 12000, 0x00, B(12), 0 },

sys/net80211/ieee80211_phy.c

176

[1] = { .phy = TURBO, 18000, 0x00, 18, 0 },

sys/net80211/ieee80211_phy.c

177

[2] = { .phy = TURBO, 24000, 0x00, B(24), 2 },

sys/net80211/ieee80211_phy.c

178

[3] = { .phy = TURBO, 36000, 0x00, 36, 2 },

sys/net80211/ieee80211_phy.c

179

[4] = { .phy = TURBO, 48000, 0x00, B(48), 4 },

sys/net80211/ieee80211_phy.c

180

[5] = { .phy = TURBO, 72000, 0x00, 72, 4 },

sys/net80211/ieee80211_phy.c

181

[6] = { .phy = TURBO, 96000, 0x00, 96, 4 },

sys/net80211/ieee80211_phy.c

182

[7] = { .phy = TURBO, 108000, 0x00, 108, 4 }

sys/net80211/ieee80211_phy.c

191

[0] = { .phy = CCK, 1000, 0x00, B(2), 0 },

sys/net80211/ieee80211_phy.c

192

[1] = { .phy = CCK, 2000, 0x04, B(4), 1 },

sys/net80211/ieee80211_phy.c

193

[2] = { .phy = CCK, 5500, 0x04, B(11), 2 },

sys/net80211/ieee80211_phy.c

194

[3] = { .phy = CCK, 11000, 0x04, B(22), 3 },

sys/net80211/ieee80211_phy.c

195

[4] = { .phy = OFDM, 6000, 0x00, 12, 4 },

sys/net80211/ieee80211_phy.c

196

[5] = { .phy = OFDM, 9000, 0x00, 18, 4 },

sys/net80211/ieee80211_phy.c

197

[6] = { .phy = OFDM, 12000, 0x00, 24, 6 },

sys/net80211/ieee80211_phy.c

198

[7] = { .phy = OFDM, 18000, 0x00, 36, 6 },

sys/net80211/ieee80211_phy.c

199

[8] = { .phy = OFDM, 24000, 0x00, 48, 8 },

sys/net80211/ieee80211_phy.c

200

[9] = { .phy = OFDM, 36000, 0x00, 72, 8 },

sys/net80211/ieee80211_phy.c

201

[10] = { .phy = OFDM, 48000, 0x00, 96, 8 },

sys/net80211/ieee80211_phy.c

202

[11] = { .phy = OFDM, 54000, 0x00, 108, 8 },

sys/net80211/ieee80211_phy.c

204

[12] = { .phy = HT, 6500, 0x00, N(0), 4 },

sys/net80211/ieee80211_phy.c

205

[13] = { .phy = HT, 13000, 0x00, N(1), 6 },

sys/net80211/ieee80211_phy.c

206

[14] = { .phy = HT, 19500, 0x00, N(2), 6 },

sys/net80211/ieee80211_phy.c

207

[15] = { .phy = HT, 26000, 0x00, N(3), 8 },

sys/net80211/ieee80211_phy.c

208

[16] = { .phy = HT, 39000, 0x00, N(4), 8 },

sys/net80211/ieee80211_phy.c

209

[17] = { .phy = HT, 52000, 0x00, N(5), 8 },

sys/net80211/ieee80211_phy.c

210

[18] = { .phy = HT, 58500, 0x00, N(6), 8 },

sys/net80211/ieee80211_phy.c

211

[19] = { .phy = HT, 65000, 0x00, N(7), 8 },

sys/net80211/ieee80211_phy.c

213

[20] = { .phy = HT, 13000, 0x00, N(8), 4 },

sys/net80211/ieee80211_phy.c

214

[21] = { .phy = HT, 26000, 0x00, N(9), 6 },

sys/net80211/ieee80211_phy.c

215

[22] = { .phy = HT, 39000, 0x00, N(10), 6 },

sys/net80211/ieee80211_phy.c

216

[23] = { .phy = HT, 52000, 0x00, N(11), 8 },

sys/net80211/ieee80211_phy.c

217

[24] = { .phy = HT, 78000, 0x00, N(12), 8 },

sys/net80211/ieee80211_phy.c

218

[25] = { .phy = HT, 104000, 0x00, N(13), 8 },

sys/net80211/ieee80211_phy.c

219

[26] = { .phy = HT, 117000, 0x00, N(14), 8 },

sys/net80211/ieee80211_phy.c

220

[27] = { .phy = HT, 130000, 0x00, N(15), 8 },

sys/net80211/ieee80211_phy.c

222

[28] = { .phy = HT, 19500, 0x00, N(16), 4 },

sys/net80211/ieee80211_phy.c

223

[29] = { .phy = HT, 39000, 0x00, N(17), 6 },

sys/net80211/ieee80211_phy.c

224

[30] = { .phy = HT, 58500, 0x00, N(18), 6 },

sys/net80211/ieee80211_phy.c

225

[31] = { .phy = HT, 78000, 0x00, N(19), 8 },

sys/net80211/ieee80211_phy.c

226

[32] = { .phy = HT, 117000, 0x00, N(20), 8 },

sys/net80211/ieee80211_phy.c

227

[33] = { .phy = HT, 156000, 0x00, N(21), 8 },

sys/net80211/ieee80211_phy.c

228

[34] = { .phy = HT, 175500, 0x00, N(22), 8 },

sys/net80211/ieee80211_phy.c

229

[35] = { .phy = HT, 195000, 0x00, N(23), 8 },

sys/net80211/ieee80211_phy.c

239

[0] = { .phy = OFDM, 6000, 0x00, B(12), 0 },

sys/net80211/ieee80211_phy.c

240

[1] = { .phy = OFDM, 9000, 0x00, 18, 0 },

sys/net80211/ieee80211_phy.c

241

[2] = { .phy = OFDM, 12000, 0x00, B(24), 2 },

sys/net80211/ieee80211_phy.c

242

[3] = { .phy = OFDM, 18000, 0x00, 36, 2 },

sys/net80211/ieee80211_phy.c

243

[4] = { .phy = OFDM, 24000, 0x00, B(48), 4 },

sys/net80211/ieee80211_phy.c

244

[5] = { .phy = OFDM, 36000, 0x00, 72, 4 },

sys/net80211/ieee80211_phy.c

245

[6] = { .phy = OFDM, 48000, 0x00, 96, 4 },

sys/net80211/ieee80211_phy.c

246

[7] = { .phy = OFDM, 54000, 0x00, 108, 4 },

sys/net80211/ieee80211_phy.c

248

[8] = { .phy = HT, 6500, 0x00, N(0), 0 },

sys/net80211/ieee80211_phy.c

249

[9] = { .phy = HT, 13000, 0x00, N(1), 2 },

sys/net80211/ieee80211_phy.c

250

[10] = { .phy = HT, 19500, 0x00, N(2), 2 },

sys/net80211/ieee80211_phy.c

251

[11] = { .phy = HT, 26000, 0x00, N(3), 4 },

sys/net80211/ieee80211_phy.c

252

[12] = { .phy = HT, 39000, 0x00, N(4), 4 },

sys/net80211/ieee80211_phy.c

253

[13] = { .phy = HT, 52000, 0x00, N(5), 4 },

sys/net80211/ieee80211_phy.c

254

[14] = { .phy = HT, 58500, 0x00, N(6), 4 },

sys/net80211/ieee80211_phy.c

255

[15] = { .phy = HT, 65000, 0x00, N(7), 4 },

sys/net80211/ieee80211_phy.c

257

[16] = { .phy = HT, 13000, 0x00, N(8), 0 },

sys/net80211/ieee80211_phy.c

258

[17] = { .phy = HT, 26000, 0x00, N(9), 2 },

sys/net80211/ieee80211_phy.c

259

[18] = { .phy = HT, 39000, 0x00, N(10), 2 },

sys/net80211/ieee80211_phy.c

260

[19] = { .phy = HT, 52000, 0x00, N(11), 4 },

sys/net80211/ieee80211_phy.c

261

[20] = { .phy = HT, 78000, 0x00, N(12), 4 },

sys/net80211/ieee80211_phy.c

262

[21] = { .phy = HT, 104000, 0x00, N(13), 4 },

sys/net80211/ieee80211_phy.c

263

[22] = { .phy = HT, 117000, 0x00, N(14), 4 },

sys/net80211/ieee80211_phy.c

264

[23] = { .phy = HT, 130000, 0x00, N(15), 4 },

sys/net80211/ieee80211_phy.c

266

[24] = { .phy = HT, 19500, 0x00, N(16), 0 },

sys/net80211/ieee80211_phy.c

267

[25] = { .phy = HT, 39000, 0x00, N(17), 2 },

sys/net80211/ieee80211_phy.c

268

[26] = { .phy = HT, 58500, 0x00, N(18), 2 },

sys/net80211/ieee80211_phy.c

269

[27] = { .phy = HT, 78000, 0x00, N(19), 4 },

sys/net80211/ieee80211_phy.c

270

[28] = { .phy = HT, 117000, 0x00, N(20), 4 },

sys/net80211/ieee80211_phy.c

271

[29] = { .phy = HT, 156000, 0x00, N(21), 4 },

sys/net80211/ieee80211_phy.c

272

[30] = { .phy = HT, 175500, 0x00, N(22), 4 },

sys/net80211/ieee80211_phy.c

273

[31] = { .phy = HT, 195000, 0x00, N(23), 4 },

sys/net80211/ieee80211_phy.c

322

if (rt->info[i].phy == IEEE80211_T_HT) {

sys/net80211/ieee80211_phy.c

514

switch (rt->info[rix].phy) {

sys/net80211/ieee80211_phy.c

565

rt->info[rix].phy, rate);

sys/net80211/ieee80211_phy.c

79

[0] = { .phy = CCK, 1000, 0x00, B(2), 0 },/* 1 Mb */

sys/net80211/ieee80211_phy.c

80

[1] = { .phy = CCK, 2000, 0x04, B(4), 1 },/* 2 Mb */

sys/net80211/ieee80211_phy.c

81

[2] = { .phy = CCK, 5500, 0x04, B(11), 1 },/* 5.5 Mb */

sys/net80211/ieee80211_phy.c

82

[3] = { .phy = CCK, 11000, 0x04, B(22), 1 },/* 11 Mb */

sys/net80211/ieee80211_phy.c

83

[4] = { .phy = PBCC, 22000, 0x04, 44, 3 } /* 22 Mb */

sys/net80211/ieee80211_phy.c

92

[0] = { .phy = CCK, 1000, 0x00, B(2), 0 },

sys/net80211/ieee80211_phy.c

93

[1] = { .phy = CCK, 2000, 0x04, B(4), 1 },

sys/net80211/ieee80211_phy.c

94

[2] = { .phy = CCK, 5500, 0x04, B(11), 2 },

sys/net80211/ieee80211_phy.c

95

[3] = { .phy = CCK, 11000, 0x04, B(22), 3 },

sys/net80211/ieee80211_phy.c

96

[4] = { .phy = OFDM, 6000, 0x00, 12, 4 },

sys/net80211/ieee80211_phy.c

97

[5] = { .phy = OFDM, 9000, 0x00, 18, 4 },

sys/net80211/ieee80211_phy.c

98

[6] = { .phy = OFDM, 12000, 0x00, 24, 6 },

sys/net80211/ieee80211_phy.c

99

[7] = { .phy = OFDM, 18000, 0x00, 36, 6 },

sys/net80211/ieee80211_phy.h

146

return rt->info[rix].phy;

sys/net80211/ieee80211_phy.h

88

uint8_t phy; /* CCK/OFDM/TURBO */

sys/net80211/ieee80211_proto.c

1491

_setifsparams(struct wmeParams *wmep, const paramType *phy)

sys/net80211/ieee80211_proto.c

1493

wmep->wmep_aifsn = phy->aifsn;

sys/net80211/ieee80211_proto.c

1494

wmep->wmep_logcwmin = phy->logcwmin;

sys/net80211/ieee80211_proto.c

1495

wmep->wmep_logcwmax = phy->logcwmax;

sys/net80211/ieee80211_proto.c

1496

wmep->wmep_txopLimit = phy->txopLimit;

sys/net80211/ieee80211_proto.c

1501

struct wmeParams *wmep, const paramType *phy)

sys/net80211/ieee80211_proto.c

1503

wmep->wmep_acm = phy->acm;

sys/net80211/ieee80211_proto.c

1504

_setifsparams(wmep, phy);

sys/riscv/sifive/fu740_pci_dw.c

111

fupci_phy_read(struct fupci_softc *sc, int phy, uint32_t reg, uint32_t *val)

sys/riscv/sifive/fu740_pci_dw.c

116

FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ADDR), reg);

sys/riscv/sifive/fu740_pci_dw.c

117

FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, READ_EN), 1);

sys/riscv/sifive/fu740_pci_dw.c

121

ack = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ACK));

sys/riscv/sifive/fu740_pci_dw.c

132

*val = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, READ_DATA));

sys/riscv/sifive/fu740_pci_dw.c

133

FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, READ_EN), 0);

sys/riscv/sifive/fu740_pci_dw.c

137

ack = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ACK));

sys/riscv/sifive/fu740_pci_dw.c

152

fupci_phy_write(struct fupci_softc *sc, int phy, uint32_t reg, uint32_t val)

sys/riscv/sifive/fu740_pci_dw.c

157

FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ADDR), reg);

sys/riscv/sifive/fu740_pci_dw.c

158

FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, WRITE_DATA), val);

sys/riscv/sifive/fu740_pci_dw.c

159

FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, WRITE_EN), 1);

sys/riscv/sifive/fu740_pci_dw.c

163

ack = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ACK));

sys/riscv/sifive/fu740_pci_dw.c

174

FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, WRITE_EN), 0);

sys/riscv/sifive/fu740_pci_dw.c

178

ack = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ACK));

sys/riscv/sifive/fu740_pci_dw.c

196

int error, phy, lane;

sys/riscv/sifive/fu740_pci_dw.c

244

for (phy = 0; phy < FUDW_PHYS; ++phy)

sys/riscv/sifive/fu740_pci_dw.c

245

FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, SEL), 1);

sys/riscv/sifive/fu740_pci_dw.c

251

for (phy = 0; phy < FUDW_PHYS; ++phy) {

sys/riscv/sifive/fu740_pci_dw.c

253

fupci_phy_write(sc, phy, FUDW_MGMT_PHY_LANE(lane),

tools/tools/net80211/wlantxtime/wlantxtime.c

102

[0] = { .phy = CCK, 1000, 0x00, B(2), 0 },/* 1 Mb */

tools/tools/net80211/wlantxtime/wlantxtime.c

103

[1] = { .phy = CCK, 2000, 0x04, B(4), 1 },/* 2 Mb */

tools/tools/net80211/wlantxtime/wlantxtime.c

104

[2] = { .phy = CCK, 5500, 0x04, B(11), 1 },/* 5.5 Mb */

tools/tools/net80211/wlantxtime/wlantxtime.c

105

[3] = { .phy = CCK, 11000, 0x04, B(22), 1 },/* 11 Mb */

tools/tools/net80211/wlantxtime/wlantxtime.c

106

[4] = { .phy = PBCC, 22000, 0x04, 44, 3 } /* 22 Mb */

tools/tools/net80211/wlantxtime/wlantxtime.c

115

[0] = { .phy = CCK, 1000, 0x00, B(2), 0 },

tools/tools/net80211/wlantxtime/wlantxtime.c

116

[1] = { .phy = CCK, 2000, 0x04, B(4), 1 },

tools/tools/net80211/wlantxtime/wlantxtime.c

117

[2] = { .phy = CCK, 5500, 0x04, B(11), 2 },

tools/tools/net80211/wlantxtime/wlantxtime.c

118

[3] = { .phy = CCK, 11000, 0x04, B(22), 3 },

tools/tools/net80211/wlantxtime/wlantxtime.c

119

[4] = { .phy = OFDM, 6000, 0x00, 12, 4 },

tools/tools/net80211/wlantxtime/wlantxtime.c

120

[5] = { .phy = OFDM, 9000, 0x00, 18, 4 },

tools/tools/net80211/wlantxtime/wlantxtime.c

121

[6] = { .phy = OFDM, 12000, 0x00, 24, 6 },

tools/tools/net80211/wlantxtime/wlantxtime.c

122

[7] = { .phy = OFDM, 18000, 0x00, 36, 6 },

tools/tools/net80211/wlantxtime/wlantxtime.c

123

[8] = { .phy = OFDM, 24000, 0x00, 48, 8 },

tools/tools/net80211/wlantxtime/wlantxtime.c

124

[9] = { .phy = OFDM, 36000, 0x00, 72, 8 },

tools/tools/net80211/wlantxtime/wlantxtime.c

125

[10] = { .phy = OFDM, 48000, 0x00, 96, 8 },

tools/tools/net80211/wlantxtime/wlantxtime.c

126

[11] = { .phy = OFDM, 54000, 0x00, 108, 8 }

tools/tools/net80211/wlantxtime/wlantxtime.c

135

[0] = { .phy = OFDM, 6000, 0x00, B(12), 0 },

tools/tools/net80211/wlantxtime/wlantxtime.c

136

[1] = { .phy = OFDM, 9000, 0x00, 18, 0 },

tools/tools/net80211/wlantxtime/wlantxtime.c

137

[2] = { .phy = OFDM, 12000, 0x00, B(24), 2 },

tools/tools/net80211/wlantxtime/wlantxtime.c

138

[3] = { .phy = OFDM, 18000, 0x00, 36, 2 },

tools/tools/net80211/wlantxtime/wlantxtime.c

139

[4] = { .phy = OFDM, 24000, 0x00, B(48), 4 },

tools/tools/net80211/wlantxtime/wlantxtime.c

140

[5] = { .phy = OFDM, 36000, 0x00, 72, 4 },

tools/tools/net80211/wlantxtime/wlantxtime.c

141

[6] = { .phy = OFDM, 48000, 0x00, 96, 4 },

tools/tools/net80211/wlantxtime/wlantxtime.c

142

[7] = { .phy = OFDM, 54000, 0x00, 108, 4 }

tools/tools/net80211/wlantxtime/wlantxtime.c

151

[0] = { .phy = HALF, 3000, 0x00, B(6), 0 },

tools/tools/net80211/wlantxtime/wlantxtime.c

152

[1] = { .phy = HALF, 4500, 0x00, 9, 0 },

tools/tools/net80211/wlantxtime/wlantxtime.c

153

[2] = { .phy = HALF, 6000, 0x00, B(12), 2 },

tools/tools/net80211/wlantxtime/wlantxtime.c

154

[3] = { .phy = HALF, 9000, 0x00, 18, 2 },

tools/tools/net80211/wlantxtime/wlantxtime.c

155

[4] = { .phy = HALF, 12000, 0x00, B(24), 4 },

tools/tools/net80211/wlantxtime/wlantxtime.c

156

[5] = { .phy = HALF, 18000, 0x00, 36, 4 },

tools/tools/net80211/wlantxtime/wlantxtime.c

157

[6] = { .phy = HALF, 24000, 0x00, 48, 4 },

tools/tools/net80211/wlantxtime/wlantxtime.c

158

[7] = { .phy = HALF, 27000, 0x00, 54, 4 }

tools/tools/net80211/wlantxtime/wlantxtime.c

167

[0] = { .phy = QUART, 1500, 0x00, B(3), 0 },

tools/tools/net80211/wlantxtime/wlantxtime.c

168

[1] = { .phy = QUART, 2250, 0x00, 4, 0 },

tools/tools/net80211/wlantxtime/wlantxtime.c

169

[2] = { .phy = QUART, 3000, 0x00, B(9), 2 },

tools/tools/net80211/wlantxtime/wlantxtime.c

170

[3] = { .phy = QUART, 4500, 0x00, 9, 2 },

tools/tools/net80211/wlantxtime/wlantxtime.c

171

[4] = { .phy = QUART, 6000, 0x00, B(12), 4 },

tools/tools/net80211/wlantxtime/wlantxtime.c

172

[5] = { .phy = QUART, 9000, 0x00, 18, 4 },

tools/tools/net80211/wlantxtime/wlantxtime.c

173

[6] = { .phy = QUART, 12000, 0x00, 24, 4 },

tools/tools/net80211/wlantxtime/wlantxtime.c

174

[7] = { .phy = QUART, 13500, 0x00, 27, 4 }

tools/tools/net80211/wlantxtime/wlantxtime.c

183

[0] = { .phy = TURBO, 12000, 0x00, B(12), 0 },

tools/tools/net80211/wlantxtime/wlantxtime.c

184

[1] = { .phy = TURBO, 24000, 0x00, B(24), 1 },

tools/tools/net80211/wlantxtime/wlantxtime.c

185

[2] = { .phy = TURBO, 36000, 0x00, 36, 1 },

tools/tools/net80211/wlantxtime/wlantxtime.c

186

[3] = { .phy = TURBO, 48000, 0x00, B(48), 3 },

tools/tools/net80211/wlantxtime/wlantxtime.c

187

[4] = { .phy = TURBO, 72000, 0x00, 72, 3 },

tools/tools/net80211/wlantxtime/wlantxtime.c

188

[5] = { .phy = TURBO, 96000, 0x00, 96, 3 },

tools/tools/net80211/wlantxtime/wlantxtime.c

189

[6] = { .phy = TURBO, 108000, 0x00, 108, 3 }

tools/tools/net80211/wlantxtime/wlantxtime.c

198

[0] = { .phy = TURBO, 12000, 0x00, B(12), 0 },

tools/tools/net80211/wlantxtime/wlantxtime.c

199

[1] = { .phy = TURBO, 18000, 0x00, 18, 0 },

tools/tools/net80211/wlantxtime/wlantxtime.c

200

[2] = { .phy = TURBO, 24000, 0x00, B(24), 2 },

tools/tools/net80211/wlantxtime/wlantxtime.c

201

[3] = { .phy = TURBO, 36000, 0x00, 36, 2 },

tools/tools/net80211/wlantxtime/wlantxtime.c

202

[4] = { .phy = TURBO, 48000, 0x00, B(48), 4 },

tools/tools/net80211/wlantxtime/wlantxtime.c

203

[5] = { .phy = TURBO, 72000, 0x00, 72, 4 },

tools/tools/net80211/wlantxtime/wlantxtime.c

204

[6] = { .phy = TURBO, 96000, 0x00, 96, 4 },

tools/tools/net80211/wlantxtime/wlantxtime.c

205

[7] = { .phy = TURBO, 108000, 0x00, 108, 4 }

tools/tools/net80211/wlantxtime/wlantxtime.c

339

switch (rt->info[rix].phy) {

tools/tools/net80211/wlantxtime/wlantxtime.c

390

rt->info[rix].phy, rate);

tools/tools/net80211/wlantxtime/wlantxtime.c

471

if (rt->info[rix].phy != IEEE80211_T_CCK) {

tools/tools/net80211/wlantxtime/wlantxtime.c

51

uint8_t phy; /* CCK/OFDM/TURBO */

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

1033

uint32_t phy;

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

1047

rparam = wlan_get_next_roam_param(&val->var, sub, &wif, &phy);

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

1050

wlan_append_phy_index(&val->var, sub, wif->wname, phy);

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

1080

uint32_t phy;

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

1089

txparam = wlan_get_tx_param(&val->var, sub, &wif, &phy);

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

1095

txparam = wlan_get_next_tx_param(&val->var, sub, &wif, &phy);

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

1098

wlan_append_phy_index(&val->var, sub, wif->wname, phy);

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

1102

txparam = wlan_get_tx_param(&val->var, sub, &wif, &phy);

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

1125

if (wlan_set_tx_params(wif, phy) < 0)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

1133

txparam = wlan_get_tx_param(&val->var, sub, &wif, &phy);

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

1152

if (wlan_set_tx_params(wif, phy) < 0)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3198

uint32_t *phy)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3209

*phy = oid->subs[sub + oid->subs[sub] + 1];

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3214

wlan_append_phy_index(struct asn_oid *oid, uint sub, char *wname, uint32_t phy)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3222

oid->subs[sub + strlen(wname) + 1] = phy;

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3524

uint32_t phy;

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3527

if (wlan_phy_index_decode(oid, sub, wname, &phy) < 0)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3533

if (phy == 0 || phy > IEEE80211_MODE_MAX)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3536

return ((*wif)->roamparams.params + phy - 1);

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3541

struct wlan_iface **wif, uint32_t *phy)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3550

*phy = 1;

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3556

if (wlan_phy_index_decode(oid, sub, wname, phy) < 0)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3559

if (*phy == 0 || (*wif = wlan_find_interface(wname)) == NULL)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3562

if (++(*phy) <= IEEE80211_MODE_MAX)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3563

return ((*wif)->roamparams.params + *phy - 1);

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3565

*phy = 1;

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3596

uint32_t *phy)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3600

if (wlan_phy_index_decode(oid, sub, wname, phy) < 0)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3606

if (*phy == 0 || *phy > IEEE80211_MODE_MAX)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3609

return ((*wif)->txparams.params + *phy - 1);

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3614

struct wlan_iface **wif, uint32_t *phy)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3623

*phy = 1;

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3629

if (wlan_phy_index_decode(oid, sub, wname, phy) < 0)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3632

if (*phy == 0 || (*wif = wlan_find_interface(wname)) == NULL)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3635

if (++(*phy) <= IEEE80211_MODE_MAX)

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3636

return ((*wif)->txparams.params + *phy - 1);

usr.sbin/bsnmpd/modules/snmp_wlan/wlan_snmp.c

3638

*phy = 1;

usr.sbin/config/main.cc

273

struct stat lg, phy;

usr.sbin/config/main.cc

289

if (stat(pwd, &lg) != -1 && stat(srcdir, &phy) != -1 &&

usr.sbin/config/main.cc

290

lg.st_dev == phy.st_dev && lg.st_ino == phy.st_ino)