sys/arm/nvidia/tegra124/tegra124_clk_per.c

418

CLK_8_1(0, "pc_i2s1", mux_a_N_audio1_N_p_N_clkm, CLK_SOURCE_I2S1, DCF_HAVE_ENA),

sys/arm/nvidia/tegra124/tegra124_clk_per.c

419

CLK_8_1(0, "pc_i2s2", mux_a_N_audio2_N_p_N_clkm, CLK_SOURCE_I2S2, DCF_HAVE_ENA),

sys/arm/nvidia/tegra124/tegra124_clk_per.c

461

CLK_8_1(0, "pc_i2s3", mux_a_N_audio3_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA),

sys/arm/nvidia/tegra124/tegra124_clk_per.c

462

CLK_8_1(0, "pc_i2s4", mux_a_N_audio4_N_p_N_clkm, CLK_SOURCE_I2S4, DCF_HAVE_ENA),

sys/arm/nvidia/tegra124/tegra124_clk_per.c

497

CLK_8_1(0, "pc_dvfs_ref", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_REF, DCF_HAVE_ENA),

sys/arm/nvidia/tegra124/tegra124_clk_per.c

498

CLK_8_1(0, "pc_dvfs_soc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_SOC, DCF_HAVE_ENA),

sys/arm/nvidia/tegra124/tegra124_clk_per.c

500

CLK_8_1(0, "pc_adx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX, DCF_HAVE_ENA),

sys/arm/nvidia/tegra124/tegra124_clk_per.c

501

CLK_8_1(0, "pc_amx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX, DCF_HAVE_ENA),

sys/arm/nvidia/tegra124/tegra124_clk_per.c

509

CLK_8_1(0, "pc_adx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX1, DCF_HAVE_ENA),

sys/arm/nvidia/tegra124/tegra124_clk_per.c

510

CLK_8_1(0, "pc_amx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX1, DCF_HAVE_ENA),

sys/arm/nvidia/tegra124/tegra124_clk_per.c

553

if (sc->flags & DCF_HAVE_ENA)

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

530

CLK_8_1(0, "pc_i2s2", mux_a_N_audio1_N_p_N_clkm, CLK_SOURCE_I2S2, DCF_HAVE_ENA),

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

531

CLK_8_1(0, "pc_i2s3", mux_a_N_audio2_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA),

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

565

CLK_8_1(0, "pc_i2s4", mux_a_N_audio3_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA),

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

566

CLK_8_1(0, "pc_i2s5", mux_a_N_audio4_N_p_N_clkm, CLK_SOURCE_I2S4, DCF_HAVE_ENA),

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

598

CLK_8_1(0, "pc_dvfs_ref", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_DVFS_REF, DCF_HAVE_ENA),

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

599

CLK_8_1(0, "pc_dvfs_soc", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_DVFS_SOC, DCF_HAVE_ENA),

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

666

if (sc->flags & DCF_HAVE_ENA)