otus_write
void otus_write(struct otus_softc *, uint32_t, uint32_t);
otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_L, hashes[0]);
otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_H, hashes[1]);
otus_write(sc, AR_MAC_REG_AC0_CW,
otus_write(sc, AR_MAC_REG_AC1_CW,
otus_write(sc, AR_MAC_REG_AC2_CW,
otus_write(sc, AR_MAC_REG_AC3_CW,
otus_write(sc, AR_MAC_REG_AC4_CW, /* Special TXQ. */
otus_write(sc, AR_MAC_REG_AC1_AC0_AIFS,
otus_write(sc, AR_MAC_REG_AC3_AC2_AIFS,
otus_write(sc, AR_MAC_REG_AC1_AC0_TXOP,
otus_write(sc, AR_MAC_REG_AC3_AC2_TXOP,
otus_write(sc, AR_MAC_REG_SLOT_TIME, slottime << 10);
otus_write(sc, AR_MAC_REG_ACK_EXTENSION, 0x40);
otus_write(sc, AR_MAC_REG_RETRY_MAX, 0);
otus_write(sc, AR_MAC_REG_RX_THRESHOLD, 0xc1f80);
otus_write(sc, AR_MAC_REG_RX_PE_DELAY, 0x70);
otus_write(sc, AR_MAC_REG_EIFS_AND_SIFS, 0xa144000);
otus_write(sc, AR_MAC_REG_SLOT_TIME, 9 << 10);
otus_write(sc, AR_MAC_REG_TID_CFACK_CFEND_RATE, 0x19000000);
otus_write(sc, AR_MAC_REG_TXOP_DURATION, 0x201);
otus_write(sc, AR_MAC_REG_BCN_HT1, 0x8000170);
otus_write(sc, AR_MAC_REG_BACKOFF_PROTECT, 0x105);
otus_write(sc, AR_MAC_REG_AMPDU_FACTOR, 0x10000a);
otus_write(sc, AR_MAC_REG_BASIC_RATE, 0x150f);
otus_write(sc, AR_MAC_REG_MANDATORY_RATE, 0x150f);
otus_write(sc, AR_MAC_REG_RTS_CTS_RATE, 0x10b01bb);
otus_write(sc, AR_MAC_REG_ACK_TPC, 0x4003c1e);
otus_write(sc, AR_GPIO_REG_PORT_TYPE, 0x3);
otus_write(sc, AR_GPIO_REG_PORT_DATA, 0x3);
otus_write(sc, 0x1c3600, 0x3);
otus_write(sc, AR_MAC_REG_AMPDU_RX_THRESH, 0xffff);
otus_write(sc, AR_MAC_REG_MISC_680, 0xf00008);
otus_write(sc, AR_MAC_REG_RX_TIMEOUT, 0);
otus_write(sc, 0x1e1110, 0x4);
otus_write(sc, 0x1e1114, 0x80);
otus_write(sc, AR_PWR_REG_CLOCK_SEL, 0x73);
otus_write(sc, AR_MAC_REG_TXRX_MPI, 0x110011);
otus_write(sc, AR_MAC_REG_FCS_SELECT, 0x4);
otus_write(sc, AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141e0f48);
otus_write(sc, AR_MAC_REG_ENCRYPTION, 0x78);
otus_write(sc, AR_PHY_SWITCH_COM, tmp);
otus_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp);
otus_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp);
otus_write(sc, AR_PHY_SETTLING, tmp);
otus_write(sc, AR_PHY_DESIRED_SZ, tmp);
otus_write(sc, AR_PHY_RF_CTL4, tmp);
otus_write(sc, AR_PHY_RF_CTL3, tmp);
otus_write(sc, AR_PHY_CCA, tmp);
otus_write(sc, AR_PHY_RXGAIN, tmp);
otus_write(sc, AR_PHY_RXGAIN + offset, tmp);
otus_write(sc, AR_PHY_GAIN_2GHZ, tmp);
otus_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp);
otus_write(sc, AR_PHY_TIMING_CTRL4, tmp);
otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp);
otus_write(sc, AR_PHY_TPCRG1, tmp);
otus_write(sc, AR_PHY(ar5416_phy_regs[i]), vals[i]);
otus_write(sc, AR_PHY_POWER_TX_RATE_MAX, 0x7f);
otus_write(sc, AR_PHY_POWER_TX_RATE1, 0x3f3f3f3f);
otus_write(sc, AR_PHY_POWER_TX_RATE2, 0x3f3f3f3f);
otus_write(sc, AR_PHY_POWER_TX_RATE3, 0x3f3f3f3f);
otus_write(sc, AR_PHY_POWER_TX_RATE4, 0x3f3f3f3f);
otus_write(sc, AR_PHY_POWER_TX_RATE5, 0x3f3f3f3f);
otus_write(sc, AR_PHY_POWER_TX_RATE6, 0x3f3f3f3f);
otus_write(sc, AR_PHY_POWER_TX_RATE7, 0x3f3f3f3f);
otus_write(sc, AR_PHY_POWER_TX_RATE8, 0x3f3f3f3f);
otus_write(sc, AR_PHY_POWER_TX_RATE9, 0x3f3f3f3f);
otus_write(sc, AR_PWR_REG_PLL_ADDAC, 0x5163);
otus_write(sc, AR_PWR_REG_PLL_ADDAC, 0x5143);
otus_write(sc, AR_PHY(44), data);
otus_write(sc, AR_PHY(58), data);
otus_write(sc, AR_MAC_REG_DYNAMIC_SIFS_ACK, tmp);
otus_write(sc, AR_PHY_HEAVY_CLIP_ENABLE, 0x200);
otus_write(sc, AR_PWR_REG_RESET, sc->bb_reset ? 0x800 : 0x400);
otus_write(sc, AR_PWR_REG_RESET, 0);
otus_write(sc, AR_PHY(ar5416_banks_regs[i]), vals[i]);
otus_write(sc, AR_PHY_TURBO, tmp);
otus_write(sc, AR_MAC_REG_BSSID_L,
otus_write(sc, AR_MAC_REG_BSSID_H,
otus_write(sc, AR_MAC_REG_MAC_ADDR_L,
otus_write(sc, AR_MAC_REG_MAC_ADDR_H,
otus_write(sc, AR_GPIO_REG_PORT_DATA, state);
otus_write(sc, AR_MAC_REG_SNIFFER, sniffer);
otus_write(sc, AR_MAC_REG_CAM_MODE, cam_mode);
otus_write(sc, AR_MAC_REG_ENCRYPTION, enc_mode);
otus_write(sc, AR_MAC_REG_RX_CONTROL, rx_ctrl);
otus_write(sc, AR_MAC_REG_FRAMETYPE_FILTER, 0xff00ffff);
otus_write(sc, AR_MAC_REG_FRAMETYPE_FILTER, 0x0500ffff);
otus_write(sc, AR_MAC_REG_DMA_TRIGGER, 0x100);
otus_write(sc, AR_MAC_REG_DMA_TRIGGER, 0);