AAC_MEM0_SETREG4
AAC_MEM0_SETREG4(sc, AAC_RX_ODBR, ~0);
AAC_MEM0_SETREG4(sc, AAC_RKT_ODBR, ~0);
AAC_MEM0_SETREG4(sc, AAC_RX_IDBR, qbit);
AAC_MEM0_SETREG4(sc, AAC_RKT_IDBR, qbit);
AAC_MEM0_SETREG4(sc, AAC_RX_ODBR, mask);
AAC_MEM0_SETREG4(sc, AAC_RKT_ODBR, mask);
AAC_MEM0_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INT_NEW_COMM);
AAC_MEM0_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INTERRUPTS);
AAC_MEM0_SETREG4(sc, AAC_RX_OIMR, ~0);
AAC_MEM0_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INT_NEW_COMM);
AAC_MEM0_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INTERRUPTS);
AAC_MEM0_SETREG4(sc, AAC_RKT_OIMR, ~0);
AAC_MEM0_SETREG4(sc, AAC_RX_IQUE, index);
AAC_MEM0_SETREG4(sc, AAC_RKT_IQUE, index);
AAC_MEM0_SETREG4(sc, AAC_RX_OQUE, index);
AAC_MEM0_SETREG4(sc, AAC_RKT_OQUE, index);
AAC_MEM0_SETREG4(sc, AAC_RX_OIMR, 0/*~(AAC_DB_COMMAND_READY |
AAC_MEM0_SETREG4(sc, AAC_SRC_ODBR_C, ~0);
AAC_MEM0_SETREG4(sc, AAC_SRC_IDBR, qbit << AAC_SRC_IDR_SHIFT);
AAC_MEM0_SETREG4(sc, AAC_SRC_ODBR_C, mask << AAC_SRC_ODR_SHIFT);
AAC_MEM0_SETREG4(sc, AAC_SRC_MAILBOX, command);
AAC_MEM0_SETREG4(sc, AAC_SRC_MAILBOX + 4, arg0);
AAC_MEM0_SETREG4(sc, AAC_SRC_MAILBOX + 8, arg1);
AAC_MEM0_SETREG4(sc, AAC_SRC_MAILBOX + 12, arg2);
AAC_MEM0_SETREG4(sc, AAC_SRC_MAILBOX + 16, arg3);
AAC_MEM0_SETREG4(sc, AAC_SRCV_MAILBOX, command);
AAC_MEM0_SETREG4(sc, AAC_SRCV_MAILBOX + 4, arg0);
AAC_MEM0_SETREG4(sc, AAC_SRCV_MAILBOX + 8, arg1);
AAC_MEM0_SETREG4(sc, AAC_SRCV_MAILBOX + 12, arg2);
AAC_MEM0_SETREG4(sc, AAC_SRCV_MAILBOX + 16, arg3);
AAC_MEM0_SETREG4(sc, AAC_SRC_OIMR,
AAC_MEM0_SETREG4(sc, AAC_SRC_OIMR, AAC_INT_DISABLE_ALL);
AAC_MEM0_SETREG4(sc, AAC_SRC_IDBR, val);
AAC_MEM0_SETREG4(sc, AAC_SRC_IOAR, val);
AAC_MEM0_SETREG4(sc, AAC_SRC_OIMR,
AAC_MEM0_SETREG4(sc, AAC_SRC_IDBR, val);
AAC_MEM0_SETREG4(sc, AAC_SRC_IDBR, val);
AAC_MEM0_SETREG4(sc, AAC_SRC_IDBR, val);
AAC_MEM0_SETREG4(sc, AAC_SRC_IDBR, val);
AAC_MEM0_SETREG4(sc, AAC_SRC_IOAR, val);
AAC_MEM0_SETREG4(sc, AAC_SRC_OIMR,
AAC_MEM0_SETREG4(sc, AAC_SRC_IQUE64_H, high_addr);
AAC_MEM0_SETREG4(sc, AAC_SRC_IQUE64_L, (u_int32_t)address + fibsize);
AAC_MEM0_SETREG4(sc, AAC_SRC_IQUE32, (u_int32_t)address + fibsize);
AAC_MEM0_SETREG4(sc, AAC_IRCSR, AAC_IRCSR_CORES_RST);
AAC_MEM0_SETREG4(sc, AAC_SRC_IDBR, reset_mask);
AAC_MEM0_SETREG4(sc, AAC_SRC_ODBR_C, bellbits);
AAC_MEM0_SETREG4(sc, AAC_SRC_ODBR_C, bellbits);