pci_dw_dbi_wr4
pci_dw_dbi_wr4(sc->dev, DW_MISC_CONTROL_1, reg);
pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, cause1);
pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, cause2);
pci_dw_dbi_wr4(sc->dev, PCIE_ABSERR, 0x9401);
#define DBI_WR4(sc, reg, val) pci_dw_dbi_wr4((sc)->dev, reg, val)
pci_dw_dbi_wr4(sc->dev, MV_GLOBAL_CONTROL_REG, reg);
pci_dw_dbi_wr4(sc->dev, MV_ARCACHE_TRC_REG, 0x3511);
pci_dw_dbi_wr4(sc->dev, MV_AWCACHE_TRC_REG, 0x5311);
pci_dw_dbi_wr4(sc->dev, MV_ARUSER_REG, 0x0002);
pci_dw_dbi_wr4(sc->dev, MV_AWUSER_REG, 0x0002);
pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, reg);
pci_dw_dbi_wr4(sc->dev, DW_MSI_INTR0_MASK, 0xFFFFFFFF);
pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, 0x0001FE00);
pci_dw_dbi_wr4(sc->dev, MV_INT_MASK2, 0x00000000);
pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, 0xFFFFFFFF);
pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, 0xFFFFFFFF);
pci_dw_dbi_wr4(sc->dev, MV_ERR_INT_MASK, 0);
pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, cause1);
pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, cause2);
pci_dw_dbi_wr4(sc->dev, DW_MISC_CONTROL_1, reg);