sys/arm/arm/debug_monitor.c

1033

dbg_wb_write_reg(DBG_REG_BASE_WVR, i, d->dbg_wvr[i]);

sys/arm/arm/debug_monitor.c

318

wvr = dbg_wb_read_reg(DBG_REG_BASE_WVR, i);

sys/arm/arm/debug_monitor.c

476

addr = dbg_wb_read_reg(DBG_REG_BASE_WVR, i) & DBGWVR_ADDR_MASK;

sys/arm/arm/debug_monitor.c

502

vr = DBG_REG_BASE_WVR;

sys/arm/arm/debug_monitor.c

561

reg_addr = DBG_REG_BASE_WVR;

sys/arm/arm/debug_monitor.c

700

reg_addr = DBG_REG_BASE_WVR;

sys/arm/arm/debug_monitor.c

759

reg_addr = DBG_REG_BASE_WVR;

sys/arm/arm/debug_monitor.c

919

dbg_wb_write_reg(DBG_REG_BASE_WVR, i, 0);

sys/arm64/arm64/debug_monitor.c

168

SWITCH_CASES_READ_WB_REG(DBG_WB_WVR, DBG_REG_BASE_WVR, val);

sys/arm64/arm64/debug_monitor.c

184

SWITCH_CASES_WRITE_WB_REG(DBG_WB_WVR, DBG_REG_BASE_WVR, val);

sys/arm64/arm64/debug_monitor.c

371

addr = dbg_wb_read_reg(DBG_REG_BASE_WVR, i);

sys/arm64/arm64/debug_monitor.c

613

dbg_wb_write_reg(DBG_REG_BASE_WVR, i,

sys/arm64/arm64/debug_monitor.c

656

dbg_wb_write_reg(DBG_REG_BASE_WVR, i, 0);

sys/arm64/arm64/debug_monitor.c

679

dbg_wb_write_reg(DBG_REG_BASE_WVR, i, 0);

sys/arm64/arm64/debug_monitor.c

712

dbg_wb_write_reg(DBG_REG_BASE_WVR, i, 0);

sys/arm64/arm64/debug_monitor.c

99

#define DBG_REG_BASE_WCR (DBG_REG_BASE_WVR + 16)