sys/arm64/nvidia/tegra210/max77620.h

194

struct max77620_reg_sc;

sys/arm64/nvidia/tegra210/max77620.h

209

struct max77620_reg_sc **regs;

sys/arm64/nvidia/tegra210/max77620_regulators.c

358

sizeof(struct max77620_reg_sc), regnode_class);

sys/arm64/nvidia/tegra210/max77620_regulators.c

361

max77620_get_sel(struct max77620_reg_sc *sc, uint8_t *sel)

sys/arm64/nvidia/tegra210/max77620_regulators.c

377

max77620_set_sel(struct max77620_reg_sc *sc, uint8_t sel)

sys/arm64/nvidia/tegra210/max77620_regulators.c

395

max77620_get_fps_src(struct max77620_reg_sc *sc, uint8_t *fps_src)

sys/arm64/nvidia/tegra210/max77620_regulators.c

409

max77620_set_fps_src(struct max77620_reg_sc *sc, uint8_t fps_src)

sys/arm64/nvidia/tegra210/max77620_regulators.c

422

max77620_set_fps_slots(struct max77620_reg_sc *sc, bool suspend)

sys/arm64/nvidia/tegra210/max77620_regulators.c

455

max77620_get_pwr_mode(struct max77620_reg_sc *sc, uint8_t *pwr_mode)

sys/arm64/nvidia/tegra210/max77620_regulators.c

469

max77620_set_pwr_mode(struct max77620_reg_sc *sc, uint8_t pwr_mode)

sys/arm64/nvidia/tegra210/max77620_regulators.c

482

max77620_get_pwr_ramp_delay(struct max77620_reg_sc *sc, int *rate)

sys/arm64/nvidia/tegra210/max77620_regulators.c

514

max77620_set_pwr_ramp_delay(struct max77620_reg_sc *sc, int rate)

sys/arm64/nvidia/tegra210/max77620_regulators.c

547

struct max77620_reg_sc *sc;

sys/arm64/nvidia/tegra210/max77620_regulators.c

695

static struct max77620_reg_sc *

sys/arm64/nvidia/tegra210/max77620_regulators.c

698

struct max77620_reg_sc *reg_sc;

sys/arm64/nvidia/tegra210/max77620_regulators.c

760

struct max77620_reg_sc *reg;

sys/arm64/nvidia/tegra210/max77620_regulators.c

771

sc->regs = malloc(sizeof(struct max77620_reg_sc *) * sc->nregs,

sys/arm64/nvidia/tegra210/max77620_regulators.c

822

struct max77620_reg_sc *sc;

sys/arm64/nvidia/tegra210/max77620_regulators.c

853

struct max77620_reg_sc *sc;

sys/arm64/nvidia/tegra210/max77620_regulators.c

872

struct max77620_reg_sc *sc;