m3_wr_2
m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
m3_wr_2(sc, HOST_INT_CTRL, 0);
m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE);
m3_wr_2(sc, GPIO_MASK, ~gpo);
m3_wr_2(sc, GPIO_DIRECTION, data | gpo);
m3_wr_2(sc, GPIO_DATA, data);
m3_wr_2(sc, GPIO_MASK, ~0);
m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK);
m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT);
m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN);
m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE);
m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97);
m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97);
m3_wr_2(sc, GPIO_DATA, 0);
m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97);
m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97);
m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE |
m3_wr_2(sc, GPIO_MASK, ~0);
m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data);
m3_wr_2(sc, CODEC_DATA, data);
m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);