m3_wr_1
m3_wr_1(sc, HOST_INT_STATUS, 0xff); /* ack the int? */
m3_wr_1(sc, HW_VOL_COUNTER_MASTER, 0x88);
m3_wr_1(sc, ASSP_HOST_INT_STATUS,
m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
m3_wr_1(sc, ASSP_CONTROL_C, 0);
m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state & ~REGB_ENABLE_RESET);
m3_wr_1(sc, ASSP_CONTROL_B, RESET_ASSP);
m3_wr_1(sc, ASSP_CONTROL_A, data);
m3_wr_1(sc, ASSP_CONTROL_B, RUN_ASSP);
m3_wr_1(sc, ASSP_CONTROL_C, data | ASSP_HOST_INT_ENABLE);
m3_wr_1(sc, CODEC_COMMAND, (regno & 0x7f) | 0x80);
m3_wr_1(sc, CODEC_COMMAND, regno & 0x7f);