sys/dev/ae/if_ae.c

1021

eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG);

sys/dev/ae/if_ae.c

1022

eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG);

sys/dev/ae/if_ae.c

1354

val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG);

sys/dev/ae/if_ae.c

1357

val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG);

sys/dev/ae/if_ae.c

1392

AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */

sys/dev/ae/if_ae.c

1605

val = AE_READ_4(sc, AE_MAC_REG);

sys/dev/ae/if_ae.c

1623

val = AE_READ_4(sc, AE_MAC_REG);

sys/dev/ae/if_ae.c

1639

val = AE_READ_4(sc, AE_IDLE_REG);

sys/dev/ae/if_ae.c

1659

val = AE_READ_4(sc, AE_MAC_REG);

sys/dev/ae/if_ae.c

1675

val = AE_READ_4(sc, AE_IDLE_REG);

sys/dev/ae/if_ae.c

1693

val = AE_READ_4(sc, AE_MAC_REG);

sys/dev/ae/if_ae.c

1712

val = AE_READ_4(sc, AE_ISR_REG);

sys/dev/ae/if_ae.c

1738

val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */

sys/dev/ae/if_ae.c

1998

val = AE_READ_4(sc, AE_MAC_REG);

sys/dev/ae/if_ae.c

2029

rxcfg = AE_READ_4(sc, AE_MAC_REG);

sys/dev/ae/if_ae.c

2171

if (AE_READ_4(sc, AE_IDLE_REG) == 0)

sys/dev/ae/if_ae.c

275

chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) &

sys/dev/ae/if_ae.c

493

if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0)

sys/dev/ae/if_ae.c

506

if (AE_READ_4(sc, AE_IDLE_REG) == 0)

sys/dev/ae/if_ae.c

628

val = AE_READ_4(sc, AE_MASTER_REG);

sys/dev/ae/if_ae.c

678

val = AE_READ_4(sc, AE_ISR_REG);

sys/dev/ae/if_ae.c

693

val = AE_READ_4(sc, AE_MASTER_REG);

sys/dev/ae/if_ae.c

722

val = AE_READ_4(sc, AE_MAC_REG);

sys/dev/ae/if_ae.c

809

val = AE_READ_4(sc, AE_MDIO_REG);

sys/dev/ae/if_ae.c

845

aereg = AE_READ_4(sc, AE_MDIO_REG);

sys/dev/ae/if_ae.c

913

val = AE_READ_4(sc, AE_SPICTL_REG);

sys/dev/ae/if_ae.c

938

val = AE_READ_4(sc, AE_VPD_CAP_REG);

sys/dev/ae/if_ae.c

947

*word = AE_READ_4(sc, AE_VPD_DATA_REG);