Symbol: CSR_WRITE_2
sys/dev/age/if_age.c
2642
CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));
sys/dev/age/if_age.c
2653
CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));
sys/dev/alc/if_alc.c
1129
CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
sys/dev/alc/if_alc.c
1175
CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL,
sys/dev/alc/if_alc.c
2980
CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX,
sys/dev/alc/if_alc.c
3576
CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX,
sys/dev/alc/if_alc.c
907
CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET);
sys/dev/alc/if_alc.c
911
CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
sys/dev/ale/if_ale.c
1479
CSR_WRITE_2(sc, ALE_GPHY_CTRL,
sys/dev/ale/if_ale.c
1511
CSR_WRITE_2(sc, ALE_GPHY_CTRL,
sys/dev/ale/if_ale.c
2682
CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
sys/dev/ale/if_ale.c
406
CSR_WRITE_2(sc, ALE_GPHY_CTRL,
sys/dev/ale/if_ale.c
410
CSR_WRITE_2(sc, ALE_GPHY_CTRL,
sys/dev/bwi/bwimac.c
1200
CSR_WRITE_2(sc, ofs, val16);
sys/dev/bwi/bwimac.c
1301
CSR_WRITE_2(sc, BWI_MAC_PRE_TBTT, pre_tbtt);
sys/dev/bwi/bwimac.c
1547
CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
sys/dev/bwi/bwimac.c
1619
CSR_WRITE_2(mac->mac_sc, BWI_MAC_SLOTTIME,
sys/dev/bwi/bwimac.c
217
CSR_WRITE_2(sc, data_reg, v);
sys/dev/bwi/bwimac.c
230
CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16);
sys/dev/bwi/bwimac.c
234
CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff);
sys/dev/bwi/bwimac.c
278
CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
sys/dev/bwi/bwimac.c
349
CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
sys/dev/bwi/bwimac.c
366
CSR_WRITE_2(sc, 0x60e, 0);
sys/dev/bwi/bwimac.c
367
CSR_WRITE_2(sc, 0x610, 0x8000);
sys/dev/bwi/bwimac.c
368
CSR_WRITE_2(sc, 0x604, 0);
sys/dev/bwi/bwimac.c
369
CSR_WRITE_2(sc, 0x606, 0x200);
sys/dev/bwi/bwimac.c
393
CSR_WRITE_2(sc, BWI_MAC_POWERUP_DELAY, sc->sc_pwron_delay);
sys/dev/bwi/bwimac.c
442
CSR_WRITE_2(sc, 0x612, 0x50); /* Force Pre-TBTT to 80? */
sys/dev/bwi/bwimac.c
477
CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
sys/dev/bwi/bwimac.c
720
CSR_WRITE_2(sc, 0x568, 0);
sys/dev/bwi/bwimac.c
721
CSR_WRITE_2(sc, 0x7c0, 0);
sys/dev/bwi/bwimac.c
722
CSR_WRITE_2(sc, 0x50c, val_50c);
sys/dev/bwi/bwimac.c
723
CSR_WRITE_2(sc, 0x508, 0);
sys/dev/bwi/bwimac.c
724
CSR_WRITE_2(sc, 0x50a, 0);
sys/dev/bwi/bwimac.c
725
CSR_WRITE_2(sc, 0x54c, 0);
sys/dev/bwi/bwimac.c
726
CSR_WRITE_2(sc, 0x56a, 0x14);
sys/dev/bwi/bwimac.c
727
CSR_WRITE_2(sc, 0x568, 0x826);
sys/dev/bwi/bwimac.c
728
CSR_WRITE_2(sc, 0x500, 0);
sys/dev/bwi/bwimac.c
729
CSR_WRITE_2(sc, 0x502, 0x30);
sys/dev/bwi/bwiphy.c
139
CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
sys/dev/bwi/bwiphy.c
140
CSR_WRITE_2(sc, BWI_PHY_DATA, data);
sys/dev/bwi/bwiphy.c
148
CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
sys/dev/bwi/bwiphy.c
441
CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
sys/dev/bwi/bwiphy.c
451
CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
sys/dev/bwi/bwiphy.c
488
CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100);
sys/dev/bwi/bwiphy.c
535
CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0);
sys/dev/bwi/bwiphy.c
559
CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
sys/dev/bwi/bwiphy.c
567
CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
sys/dev/bwi/bwiphy.c
721
CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL2);
sys/dev/bwi/bwiphy.c
728
CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC2);
sys/dev/bwi/bwiphy.c
741
CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
sys/dev/bwi/bwirf.c
1282
CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div | 0x8000);
sys/dev/bwi/bwirf.c
1311
CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0);
sys/dev/bwi/bwirf.c
1360
CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
sys/dev/bwi/bwirf.c
1374
CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
sys/dev/bwi/bwirf.c
1675
CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x7f7f);
sys/dev/bwi/bwirf.c
1689
CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x40);
sys/dev/bwi/bwirf.c
1691
CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
sys/dev/bwi/bwirf.c
1715
CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
sys/dev/bwi/bwirf.c
1723
CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
sys/dev/bwi/bwirf.c
201
CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
sys/dev/bwi/bwirf.c
202
CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);
sys/dev/bwi/bwirf.c
2054
CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
sys/dev/bwi/bwirf.c
2055
CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
sys/dev/bwi/bwirf.c
2056
CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
sys/dev/bwi/bwirf.c
220
CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
sys/dev/bwi/bwirf.c
251
CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
sys/dev/bwi/bwirf.c
255
CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
sys/dev/bwi/bwirf.c
2605
CSR_WRITE_2(sc, BWI_PHY_CTRL, 0x3f3f);
sys/dev/bwi/bwirf.c
2682
CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
sys/dev/bwi/bwirf.c
354
CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
sys/dev/bwi/bwirf.c
580
CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));
sys/dev/bwi/bwirf.c
582
CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));
sys/dev/bwi/bwirf.c
584
CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
sys/dev/bwi/bwirf.c
786
CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f);
sys/dev/bwi/bwirf.c
824
CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
sys/dev/bwi/bwirf.c
980
CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
sys/dev/bwi/bwirf.c
982
CSR_WRITE_2(sc, BWI_RF_CHAN_EX, rf_chan_ex);
sys/dev/bwi/bwirf.c
989
CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
sys/dev/bwi/if_bwi.c
1622
CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
sys/dev/bwi/if_bwi.c
2573
CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
sys/dev/bwi/if_bwi.c
2581
CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
sys/dev/bwi/if_bwi.c
3907
CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
sys/dev/bwi/if_bwi.c
3952
CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
sys/dev/bwi/if_bwi.c
3973
CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
sys/dev/bwi/if_bwivar.h
89
CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
sys/dev/bwi/if_bwivar.h
94
CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
sys/dev/bwi/if_bwivar.h
99
CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
sys/dev/fxp/if_fxp.c
1122
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/fxp/if_fxp.c
1124
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
sys/dev/fxp/if_fxp.c
1126
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/fxp/if_fxp.c
1144
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/dev/fxp/if_fxp.c
1158
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/fxp/if_fxp.c
1160
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
sys/dev/fxp/if_fxp.c
1162
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/fxp/if_fxp.c
1177
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
sys/dev/fxp/if_fxp.c
1181
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/fxp/if_fxp.c
1184
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
sys/dev/fxp/if_fxp.c
1198
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/dev/fxp/if_fxp.c
1201
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
sys/dev/fxp/if_fxp.c
1206
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/dev/fxp/if_fxp.c
1210
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
sys/dev/fxp/if_fxp.c
1215
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/dev/fxp/if_fxp.c
1222
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
sys/dev/fxp/if_fxp.c
1227
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
sys/dev/fxp/if_fxp.c
1230
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
sys/dev/ipw/if_ipwreg.h
366
CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
sys/dev/iwi/if_iwireg.h
608
CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
sys/dev/lge/if_lge.c
1281
CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
sys/dev/msk/if_msk.c
1293
CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
sys/dev/msk/if_msk.c
1307
CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
sys/dev/msk/if_msk.c
1309
CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
sys/dev/msk/if_msk.c
1366
CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
sys/dev/msk/if_msk.c
1370
CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
sys/dev/msk/if_msk.c
1375
CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
sys/dev/msk/if_msk.c
1376
CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
sys/dev/msk/if_msk.c
1386
CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR);
sys/dev/msk/if_msk.c
1441
CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON);
sys/dev/msk/if_msk.c
1465
CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
sys/dev/msk/if_msk.c
1466
CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
sys/dev/msk/if_msk.c
1534
CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1);
sys/dev/msk/if_msk.c
1538
CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
sys/dev/msk/if_msk.c
1543
CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);
sys/dev/msk/if_msk.c
1773
CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
sys/dev/msk/if_msk.c
2059
CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF);
sys/dev/msk/if_msk.c
2062
CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
sys/dev/msk/if_msk.c
2922
CSR_WRITE_2(sc_if->msk_softc,
sys/dev/msk/if_msk.c
2976
CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
sys/dev/msk/if_msk.c
3006
CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
sys/dev/msk/if_msk.c
3418
CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
sys/dev/msk/if_msk.c
3425
CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
sys/dev/msk/if_msk.c
3547
CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq,
sys/dev/msk/if_msk.c
3888
CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);
sys/dev/msk/if_msk.c
3900
CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
sys/dev/msk/if_msk.c
3902
CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
sys/dev/msk/if_msk.c
3935
CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
sys/dev/msk/if_msk.c
3940
CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL),
sys/dev/msk/if_msk.c
3959
CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
sys/dev/msk/if_msk.c
4101
CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG),
sys/dev/msk/if_msk.c
686
CSR_WRITE_2(sc_if->msk_softc,
sys/dev/msk/if_msk.c
751
CSR_WRITE_2(sc_if->msk_softc,
sys/dev/msk/if_msk.c
819
CSR_WRITE_2(sc_if->msk_softc,
sys/dev/msk/if_mskreg.h
2162
CSR_WRITE_2((sc_if)->msk_softc, (reg), (val))
sys/dev/msk/if_mskreg.h
2169
CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val))
sys/dev/my/if_my.c
269
CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
sys/dev/re/if_re.c
2541
CSR_WRITE_2(sc, RL_ISR, status);
sys/dev/re/if_re.c
2570
CSR_WRITE_2(sc, RL_IMR, 0);
sys/dev/re/if_re.c
2591
CSR_WRITE_2(sc, RL_ISR, status);
sys/dev/re/if_re.c
2644
CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
sys/dev/re/if_re.c
2665
CSR_WRITE_2(sc, RL_IMR, 0);
sys/dev/re/if_re.c
2673
CSR_WRITE_2(sc, RL_ISR, status);
sys/dev/re/if_re.c
2723
CSR_WRITE_2(sc, RL_IMR, intrs);
sys/dev/re/if_re.c
3168
CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
sys/dev/re/if_re.c
3178
CSR_WRITE_2(sc, 0xe2, 0);
sys/dev/re/if_re.c
3252
CSR_WRITE_2(sc, RL_INTRMOD, 0x5100);
sys/dev/re/if_re.c
3267
CSR_WRITE_2(sc, RL_IMR, 0);
sys/dev/re/if_re.c
3275
CSR_WRITE_2(sc, RL_IMR, 0);
sys/dev/re/if_re.c
3277
CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
sys/dev/re/if_re.c
3278
CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
sys/dev/re/if_re.c
3329
CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
sys/dev/re/if_re.c
3334
CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
sys/dev/re/if_re.c
3339
CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
sys/dev/re/if_re.c
3341
CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
sys/dev/re/if_re.c
3479
CSR_WRITE_2(sc, RL_IMR, 0x0000);
sys/dev/re/if_re.c
3486
CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
sys/dev/re/if_re.c
3661
CSR_WRITE_2(sc, RL_IMR, 0x0000);
sys/dev/re/if_re.c
3662
CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
sys/dev/re/if_re.c
614
CSR_WRITE_2(sc, re8139_reg, data);
sys/dev/re/if_re.c
824
CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
sys/dev/re/if_re.c
841
CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
sys/dev/re/if_re.c
853
CSR_WRITE_2(sc, RL_ISR, status);
sys/dev/rl/if_rl.c
1205
CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
sys/dev/rl/if_rl.c
1316
CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
sys/dev/rl/if_rl.c
1319
CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
sys/dev/rl/if_rl.c
1462
CSR_WRITE_2(sc, RL_ISR, status);
sys/dev/rl/if_rl.c
1501
CSR_WRITE_2(sc, RL_IMR, 0);
sys/dev/rl/if_rl.c
1503
CSR_WRITE_2(sc, RL_ISR, status);
sys/dev/rl/if_rl.c
1527
CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
sys/dev/rl/if_rl.c
1738
CSR_WRITE_2(sc, RL_IMR, 0);
sys/dev/rl/if_rl.c
1742
CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
sys/dev/rl/if_rl.c
1844
CSR_WRITE_2(sc, RL_IMR, 0x0000);
sys/dev/rl/if_rl.c
1855
CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
sys/dev/rl/if_rl.c
1915
CSR_WRITE_2(sc, RL_IMR, 0x0000);
sys/dev/rl/if_rl.c
466
CSR_WRITE_2(sc, rl8139_reg, data);
sys/dev/rl/if_rlreg.h
971
CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
sys/dev/rl/if_rlreg.h
974
CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
sys/dev/sge/if_sge.c
1650
CSR_WRITE_2(sc, RxMPSControl, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN +
sys/dev/sge/if_sge.c
1657
CSR_WRITE_2(sc, RxMacControl, rxfilt);
sys/dev/sge/if_sge.c
479
CSR_WRITE_2(sc, RxMacControl, rxfilt);
sys/dev/sge/if_sge.c
500
CSR_WRITE_2(sc, RxMacControl, rxfilt);
sys/dev/sk/if_sk.c
1162
CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
sys/dev/sk/if_sk.c
1163
CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
sys/dev/sk/if_sk.c
1165
CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
sys/dev/sk/if_sk.c
1168
CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
sys/dev/sk/if_sk.c
1170
CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
sys/dev/sk/if_sk.c
1172
CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
sys/dev/sk/if_sk.c
1719
CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
sys/dev/sk/if_sk.c
2476
CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
sys/dev/sk/if_sk.c
412
CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
sys/dev/sk/if_sk.c
414
CSR_WRITE_2(sc, reg, val);
sys/dev/ste/if_ste.c
1515
CSR_WRITE_2(sc, STE_PAR0 + i,
sys/dev/ste/if_ste.c
1544
CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
sys/dev/ste/if_ste.c
1550
CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
sys/dev/ste/if_ste.c
1578
CSR_WRITE_2(sc, STE_MACCTL0, 0);
sys/dev/ste/if_ste.c
1579
CSR_WRITE_2(sc, STE_MACCTL1, 0);
sys/dev/ste/if_ste.c
1588
CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
sys/dev/ste/if_ste.c
1589
CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
sys/dev/ste/if_ste.c
1593
CSR_WRITE_2(sc, STE_IMR, 0);
sys/dev/ste/if_ste.c
1597
CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
sys/dev/ste/if_ste.c
1625
CSR_WRITE_2(sc, STE_IMR, 0);
sys/dev/ste/if_ste.c
1626
CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
sys/dev/ste/if_ste.c
1642
CSR_WRITE_2(sc, STE_MACCTL1, val);
sys/dev/ste/if_ste.c
1719
CSR_WRITE_2(sc, STE_MACCTL1, mac);
sys/dev/ste/if_ste.c
1782
CSR_WRITE_2(sc, STE_IMR, 0);
sys/dev/ste/if_ste.c
1786
CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
sys/dev/ste/if_ste.c
189
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
sys/dev/ste/if_ste.c
192
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
sys/dev/ste/if_ste.c
296
CSR_WRITE_2(sc, STE_MACCTL0, cfg);
sys/dev/ste/if_ste.c
393
CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
sys/dev/ste/if_ste.c
448
CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
sys/dev/ste/if_ste.c
449
CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
sys/dev/ste/if_ste.c
450
CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
sys/dev/ste/if_ste.c
451
CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
sys/dev/ste/if_ste.c
552
CSR_WRITE_2(sc, STE_COUNTDOWN,
sys/dev/ste/if_ste.c
579
CSR_WRITE_2(sc, STE_IMR, intrs);
sys/dev/ste/if_ste.c
727
CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
sys/dev/stge/if_stge.c
1304
CSR_WRITE_2(sc, STGE_IntEnable, 0);
sys/dev/stge/if_stge.c
1312
CSR_WRITE_2(sc, STGE_IntEnable,
sys/dev/stge/if_stge.c
1501
CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
sys/dev/stge/if_stge.c
2007
CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
sys/dev/stge/if_stge.c
2008
CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
sys/dev/stge/if_stge.c
2009
CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
sys/dev/stge/if_stge.c
2051
CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
sys/dev/stge/if_stge.c
2058
CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
sys/dev/stge/if_stge.c
2083
CSR_WRITE_2(sc, STGE_IntEnable, 0);
sys/dev/stge/if_stge.c
2086
CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
sys/dev/stge/if_stge.c
2099
CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
sys/dev/stge/if_stge.c
2100
CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
sys/dev/stge/if_stge.c
2106
CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
sys/dev/stge/if_stge.c
2122
CSR_WRITE_2(sc, STGE_DebugCtrl,
sys/dev/stge/if_stge.c
2126
CSR_WRITE_2(sc, STGE_DebugCtrl,
sys/dev/stge/if_stge.c
2129
CSR_WRITE_2(sc, STGE_DebugCtrl,
sys/dev/stge/if_stge.c
2210
CSR_WRITE_2(sc, STGE_IntEnable, 0);
sys/dev/stge/if_stge.c
2494
CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
sys/dev/stge/if_stge.c
2529
CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
sys/dev/stge/if_stge.c
2555
CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
sys/dev/stge/if_stge.c
399
CSR_WRITE_2(sc, STGE_EepromCtrl,
sys/dev/vge/if_vge.c
1587
CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT,
sys/dev/vge/if_vge.c
1995
CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
sys/dev/vge/if_vge.c
2077
CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1);
sys/dev/vge/if_vge.c
2081
CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1);
sys/dev/vge/if_vge.c
2082
CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT);
sys/dev/vge/if_vge.c
2092
CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0);
sys/dev/vge/if_vge.c
2102
CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF);
sys/dev/vge/if_vge.c
2404
CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF);
sys/dev/vge/if_vge.c
405
CSR_WRITE_2(sc, VGE_MIIDATA, data);
sys/dev/vge/if_vgevar.h
233
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
sys/dev/vge/if_vgevar.h
240
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
sys/dev/vr/if_vr.c
1610
CSR_WRITE_2(sc, VR_ISR, status);
sys/dev/vr/if_vr.c
1674
CSR_WRITE_2(sc, VR_IMR, 0x0000);
sys/dev/vr/if_vr.c
1705
CSR_WRITE_2(sc, VR_IMR, 0);
sys/dev/vr/if_vr.c
1706
CSR_WRITE_2(sc, VR_ISR, status);
sys/dev/vr/if_vr.c
1711
CSR_WRITE_2(sc, VR_ISR, status);
sys/dev/vr/if_vr.c
1737
CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
sys/dev/vr/if_vr.c
1753
CSR_WRITE_2(sc, VR_IMR, 0);
sys/dev/vr/if_vr.c
2133
CSR_WRITE_2(sc, VR_PAUSETIMER, 0xffff);
sys/dev/vr/if_vr.c
2140
CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
sys/dev/vr/if_vr.c
2146
CSR_WRITE_2(sc, VR_IMR, 0);
sys/dev/vr/if_vr.c
2152
CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
sys/dev/vr/if_vr.c
2154
CSR_WRITE_2(sc, VR_MII_IMR, 0);
sys/dev/vr/if_vr.c
2262
CSR_WRITE_2(sc, VR_IMR, 0x0000);
sys/dev/vr/if_vr.c
2269
CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
sys/dev/vr/if_vr.c
2444
CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
sys/dev/vr/if_vr.c
2445
CSR_WRITE_2(sc, VR_IMR, 0x0000);
sys/dev/vr/if_vr.c
272
CSR_WRITE_2(sc, VR_MIIDATA, data);
sys/dev/vr/if_vr.c
733
CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
sys/dev/vr/if_vr.c
734
CSR_WRITE_2(sc, VR_IMR, 0);
sys/dev/vr/if_vr.c
736
CSR_WRITE_2(sc, VR_MII_IMR, 0);
sys/dev/vr/if_vrreg.h
759
#define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
sys/dev/vr/if_vrreg.h
760
#define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
sys/dev/vte/if_vte.c
1147
CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
sys/dev/vte/if_vte.c
1243
CSR_WRITE_2(sc, VTE_MCR0, mcr);
sys/dev/vte/if_vte.c
1344
CSR_WRITE_2(sc, VTE_MIER, 0);
sys/dev/vte/if_vte.c
1365
CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
sys/dev/vte/if_vte.c
1564
CSR_WRITE_2(sc, VTE_MRDCR, prog |
sys/dev/vte/if_vte.c
1597
CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
sys/dev/vte/if_vte.c
1610
CSR_WRITE_2(sc, VTE_MACSM, 0x0002);
sys/dev/vte/if_vte.c
1611
CSR_WRITE_2(sc, VTE_MACSM, 0);
sys/dev/vte/if_vte.c
1620
CSR_WRITE_2(sc, VTE_MDCSC, mdcsc);
sys/dev/vte/if_vte.c
1676
CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]);
sys/dev/vte/if_vte.c
1677
CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]);
sys/dev/vte/if_vte.c
1678
CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]);
sys/dev/vte/if_vte.c
1682
CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16);
sys/dev/vte/if_vte.c
1683
CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF);
sys/dev/vte/if_vte.c
1686
CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16);
sys/dev/vte/if_vte.c
1687
CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF);
sys/dev/vte/if_vte.c
1694
CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) |
sys/dev/vte/if_vte.c
1707
CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX);
sys/dev/vte/if_vte.c
1710
CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 |
sys/dev/vte/if_vte.c
1721
CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT);
sys/dev/vte/if_vte.c
1728
CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 |
sys/dev/vte/if_vte.c
1735
CSR_WRITE_2(sc, VTE_MRICR, 0);
sys/dev/vte/if_vte.c
1736
CSR_WRITE_2(sc, VTE_MTICR, 0);
sys/dev/vte/if_vte.c
1739
CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS);
sys/dev/vte/if_vte.c
1744
CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
sys/dev/vte/if_vte.c
1745
CSR_WRITE_2(sc, VTE_MISR, 0);
sys/dev/vte/if_vte.c
175
CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
sys/dev/vte/if_vte.c
1776
CSR_WRITE_2(sc, VTE_MIER, 0);
sys/dev/vte/if_vte.c
1777
CSR_WRITE_2(sc, VTE_MECIER, 0);
sys/dev/vte/if_vte.c
1831
CSR_WRITE_2(sc, VTE_MCR0, mcr);
sys/dev/vte/if_vte.c
1857
CSR_WRITE_2(sc, VTE_MCR0, mcr);
sys/dev/vte/if_vte.c
199
CSR_WRITE_2(sc, VTE_MMWD, val);
sys/dev/vte/if_vte.c
200
CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
sys/dev/vte/if_vte.c
2029
CSR_WRITE_2(sc, VTE_MAR0, ctx.mchash[0]);
sys/dev/vte/if_vte.c
2030
CSR_WRITE_2(sc, VTE_MAR1, ctx.mchash[1]);
sys/dev/vte/if_vte.c
2031
CSR_WRITE_2(sc, VTE_MAR2, ctx.mchash[2]);
sys/dev/vte/if_vte.c
2032
CSR_WRITE_2(sc, VTE_MAR3, ctx.mchash[3]);
sys/dev/vte/if_vte.c
2035
CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0,
sys/dev/vte/if_vte.c
2037
CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2,
sys/dev/vte/if_vte.c
2039
CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4,
sys/dev/vte/if_vte.c
2042
CSR_WRITE_2(sc, VTE_MCR0, mcr);
sys/dev/vte/if_vte.c
256
CSR_WRITE_2(sc, VTE_MRICR, val);
sys/dev/vte/if_vte.c
264
CSR_WRITE_2(sc, VTE_MTICR, val);
sys/dev/xl/if_xl.c
1456
CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
sys/dev/xl/if_xl.c
1945
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
sys/dev/xl/if_xl.c
1949
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
sys/dev/xl/if_xl.c
2017
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
sys/dev/xl/if_xl.c
2081
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
sys/dev/xl/if_xl.c
2113
CSR_WRITE_2(sc, XL_COMMAND,
sys/dev/xl/if_xl.c
2116
CSR_WRITE_2(sc, XL_COMMAND,
sys/dev/xl/if_xl.c
2119
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
sys/dev/xl/if_xl.c
2120
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
sys/dev/xl/if_xl.c
2122
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
sys/dev/xl/if_xl.c
2123
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
sys/dev/xl/if_xl.c
2153
CSR_WRITE_2(sc, XL_COMMAND,
sys/dev/xl/if_xl.c
2239
CSR_WRITE_2(sc, XL_COMMAND,
sys/dev/xl/if_xl.c
2518
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
sys/dev/xl/if_xl.c
2537
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
sys/dev/xl/if_xl.c
2679
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
sys/dev/xl/if_xl.c
2682
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
sys/dev/xl/if_xl.c
2696
CSR_WRITE_2(sc, XL_W7_BM_PME, 0);
sys/dev/xl/if_xl.c
2707
CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
sys/dev/xl/if_xl.c
2710
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
sys/dev/xl/if_xl.c
2712
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
sys/dev/xl/if_xl.c
2745
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
sys/dev/xl/if_xl.c
2757
CSR_WRITE_2(sc, XL_COMMAND,
sys/dev/xl/if_xl.c
2774
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
sys/dev/xl/if_xl.c
2777
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
sys/dev/xl/if_xl.c
2784
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
sys/dev/xl/if_xl.c
2788
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
sys/dev/xl/if_xl.c
2798
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
sys/dev/xl/if_xl.c
2800
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
sys/dev/xl/if_xl.c
2810
CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
sys/dev/xl/if_xl.c
2819
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
sys/dev/xl/if_xl.c
2822
CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
sys/dev/xl/if_xl.c
2823
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
sys/dev/xl/if_xl.c
2828
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
sys/dev/xl/if_xl.c
2829
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
sys/dev/xl/if_xl.c
2833
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
sys/dev/xl/if_xl.c
2836
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
sys/dev/xl/if_xl.c
2841
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
sys/dev/xl/if_xl.c
2845
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
sys/dev/xl/if_xl.c
2847
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
sys/dev/xl/if_xl.c
3038
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
sys/dev/xl/if_xl.c
3045
CSR_WRITE_2(sc, XL_COMMAND,
sys/dev/xl/if_xl.c
3047
CSR_WRITE_2(sc, XL_COMMAND,
sys/dev/xl/if_xl.c
3147
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
sys/dev/xl/if_xl.c
3148
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
sys/dev/xl/if_xl.c
3149
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
sys/dev/xl/if_xl.c
3150
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
sys/dev/xl/if_xl.c
3152
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
sys/dev/xl/if_xl.c
3153
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
sys/dev/xl/if_xl.c
3157
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
sys/dev/xl/if_xl.c
3159
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
sys/dev/xl/if_xl.c
3163
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
sys/dev/xl/if_xl.c
3164
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
sys/dev/xl/if_xl.c
3165
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
sys/dev/xl/if_xl.c
3269
CSR_WRITE_2(sc, XL_W7_BM_PME, cfg);
sys/dev/xl/if_xl.c
3272
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
sys/dev/xl/if_xl.c
406
CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val);
sys/dev/xl/if_xl.c
571
CSR_WRITE_2(sc, XL_W0_EE_CMD,
sys/dev/xl/if_xl.c
574
CSR_WRITE_2(sc, XL_W0_EE_CMD,
sys/dev/xl/if_xl.c
644
CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
sys/dev/xl/if_xl.c
668
CSR_WRITE_2(sc, XL_COMMAND, h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
sys/dev/xl/if_xl.c
705
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
sys/dev/xl/if_xl.c
712
CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
sys/dev/xl/if_xl.c
733
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
sys/dev/xl/if_xl.c
818
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
sys/dev/xl/if_xl.c
820
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
sys/dev/xl/if_xl.c
824
CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
sys/dev/xl/if_xl.c
840
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
sys/dev/xl/if_xl.c
870
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
sys/dev/xl/if_xl.c
873
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
sys/dev/xl/if_xl.c
879
CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
sys/dev/xl/if_xlreg.h
671
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x); \