sys/dev/mgb/if_mgb.c

1014

CSR_WRITE_REG(sc, MGB_DMA_TX_TAIL(txqid), rdata->last_tail);

sys/dev/mgb/if_mgb.c

1178

CSR_WRITE_REG(sc, MGB_DMA_RX_TAIL(rxqid), sc->rx_ring_data.last_tail);

sys/dev/mgb/if_mgb.c

1263

CSR_WRITE_REG(sc, MGB_DMA_RX_BASE_H(channel),

sys/dev/mgb/if_mgb.c

1265

CSR_WRITE_REG(sc, MGB_DMA_RX_BASE_L(channel),

sys/dev/mgb/if_mgb.c

1273

CSR_WRITE_REG(sc, MGB_DMA_RX_HEAD_WB_H(channel),

sys/dev/mgb/if_mgb.c

1275

CSR_WRITE_REG(sc, MGB_DMA_RX_HEAD_WB_L(channel),

sys/dev/mgb/if_mgb.c

1279

CSR_WRITE_REG(sc, MGB_DMA_RX_CONFIG0(channel), MGB_DMA_HEAD_WB_ENBL);

sys/dev/mgb/if_mgb.c

1289

CSR_WRITE_REG(sc, MGB_DMA_RX_CONFIG1(channel), ring_config);

sys/dev/mgb/if_mgb.c

1339

CSR_WRITE_REG(sc, MGB_DMA_TX_BASE_H(channel),

sys/dev/mgb/if_mgb.c

1341

CSR_WRITE_REG(sc, MGB_DMA_TX_BASE_L(channel),

sys/dev/mgb/if_mgb.c

1348

CSR_WRITE_REG(sc, MGB_DMA_TX_CONFIG1(channel), ring_config);

sys/dev/mgb/if_mgb.c

1352

CSR_WRITE_REG(sc, MGB_DMA_TX_CONFIG0(channel), ring_config);

sys/dev/mgb/if_mgb.c

1359

CSR_WRITE_REG(sc, MGB_DMA_TX_HEAD_WB_H(channel),

sys/dev/mgb/if_mgb.c

1361

CSR_WRITE_REG(sc, MGB_DMA_TX_HEAD_WB_L(channel),

sys/dev/mgb/if_mgb.c

1367

CSR_WRITE_REG(sc, MGB_DMA_TX_TAIL(channel), rdata->last_tail);

sys/dev/mgb/if_mgb.c

1384

CSR_WRITE_REG(sc, MGB_DMAC_CMD,

sys/dev/mgb/if_mgb.c

1398

CSR_WRITE_REG(sc, MGB_DMAC_CMD,

sys/dev/mgb/if_mgb.c

1403

CSR_WRITE_REG(sc, MGB_DMAC_CMD,

sys/dev/mgb/if_mgb.c

1420

CSR_WRITE_REG(sc, reg, MGB_FCT_RESET(channel));

sys/dev/mgb/if_mgb.c

1423

CSR_WRITE_REG(sc, reg, MGB_FCT_ENBL(channel));

sys/dev/mgb/if_mgb.c

1426

CSR_WRITE_REG(sc, reg, MGB_FCT_DSBL(channel));

sys/dev/mgb/if_mgb.c

1507

CSR_WRITE_REG(sc, MGB_DMAC_CMD, MGB_DMAC_RESET);

sys/dev/mgb/if_mgb.c

1553

CSR_WRITE_REG(sc, MGB_MII_ACCESS, mii_access);

sys/dev/mgb/if_mgb.c

1574

CSR_WRITE_REG(sc, MGB_MII_DATA, data);

sys/dev/mgb/if_mgb.c

1575

CSR_WRITE_REG(sc, MGB_MII_ACCESS, mii_access);

sys/dev/mgb/if_mgb.c

446

CSR_WRITE_REG(sc, MGB_INTR_VEC_RX_MAP, 0);

sys/dev/mgb/if_mgb.c

447

CSR_WRITE_REG(sc, MGB_INTR_VEC_TX_MAP, 0);

sys/dev/mgb/if_mgb.c

448

CSR_WRITE_REG(sc, MGB_INTR_VEC_OTHER_MAP, 0);

sys/dev/mgb/if_mgb.c

693

CSR_WRITE_REG(sc, 0x24, 0xF); // DP_SEL & TX_RAM_0

sys/dev/mgb/if_mgb.c

695

CSR_WRITE_REG(sc, 0x2C, i); // DP_ADDR

sys/dev/mgb/if_mgb.c

697

CSR_WRITE_REG(sc, 0x28, 0); // DP_CMD

sys/dev/mgb/if_mgb.c

756

CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR,

sys/dev/mgb/if_mgb.c

758

CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_RX(qidx));

sys/dev/mgb/if_mgb.c

784

CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_TEST);

sys/dev/mgb/if_mgb.c

800

CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR,

sys/dev/mgb/if_mgb.c

802

CSR_WRITE_REG(sc, MGB_INTR_STS,

sys/dev/mgb/if_mgb.c

885

CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET, intr_sts);

sys/dev/mgb/if_mgb.c

886

CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_SET, vec_en);

sys/dev/mgb/if_mgb.c

887

CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, dmac_enable);

sys/dev/mgb/if_mgb.c

888

CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_SET, dmac_enable);

sys/dev/mgb/if_mgb.c

897

CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR, UINT32_MAX);

sys/dev/mgb/if_mgb.c

898

CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_CLR, UINT32_MAX);

sys/dev/mgb/if_mgb.c

899

CSR_WRITE_REG(sc, MGB_INTR_STS, UINT32_MAX);

sys/dev/mgb/if_mgb.c

901

CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_CLR, UINT32_MAX);

sys/dev/mgb/if_mgb.c

902

CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, UINT32_MAX);

sys/dev/mgb/if_mgb.c

912

CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_SET, MGB_INTR_RX_VEC_STS(qid));

sys/dev/mgb/if_mgb.c

913

CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET, MGB_INTR_STS_RX(qid));

sys/dev/mgb/if_mgb.c

915

CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, MGB_DMAC_RX_INTR_ENBL(qid));

sys/dev/mgb/if_mgb.c

916

CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_SET, MGB_DMAC_RX_INTR_ENBL(qid));

sys/dev/mgb/if_mgb.c

928

CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET, MGB_INTR_STS_TX(qid));

sys/dev/mgb/if_mgb.c

930

CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, MGB_DMAC_TX_INTR_ENBL(qid));

sys/dev/mgb/if_mgb.c

931

CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_SET, MGB_DMAC_TX_INTR_ENBL(qid));

sys/dev/mgb/if_mgb.c

941

CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_TEST);

sys/dev/mgb/if_mgb.c

942

CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_SET, MGB_INTR_STS_ANY);

sys/dev/mgb/if_mgb.c

943

CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET,

sys/dev/mgb/if_mgb.c

945

CSR_WRITE_REG(sc, MGB_INTR_SET, MGB_INTR_STS_TEST);

sys/dev/mgb/if_mgb.c

953

CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR, MGB_INTR_STS_TEST);

sys/dev/mgb/if_mgb.c

954

CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_TEST);

sys/dev/mgb/if_mgb.h

237

CSR_WRITE_REG(sc, reg, CSR_READ_REG(sc, reg) & ~(bits))

sys/dev/mgb/if_mgb.h

240

CSR_WRITE_REG(sc, reg, CSR_READ_REG(sc, reg) | (val))