sys/dev/ale/if_ale.c

2341

CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,

sys/dev/ale/if_ale.c

2646

CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);

sys/dev/ale/if_ale.c

2647

CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);

sys/dev/fxp/if_fxp.c

1007

CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);

sys/dev/fxp/if_fxp.c

1091

CSR_WRITE_1(sc, FXP_CSR_PMDR,

sys/dev/fxp/if_fxp.c

1675

CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);

sys/dev/fxp/if_fxp.c

1721

CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);

sys/dev/fxp/if_fxp.c

2180

CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);

sys/dev/fxp/if_fxp.c

2404

CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1);

sys/dev/fxp/if_fxp.c

2539

CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);

sys/dev/fxp/if_fxp.c

2542

CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);

sys/dev/fxp/if_fxp.c

2868

CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,

sys/dev/fxp/if_fxp.c

2876

CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);

sys/dev/fxp/if_fxp.c

351

CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);

sys/dev/fxp/if_fxp.c

354

CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);

sys/dev/fxp/if_fxp.c

492

CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);

sys/dev/fxp/if_fxp.c

909

CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));

sys/dev/ipw/if_ipw.c

2613

CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap);

sys/dev/ipw/if_ipwreg.h

361

CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \

sys/dev/iwi/if_iwireg.h

603

CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \

sys/dev/msk/if_msk.c

1252

CSR_WRITE_1(sc, B0_POWER_CTRL,

sys/dev/msk/if_msk.c

1268

CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);

sys/dev/msk/if_msk.c

1336

CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);

sys/dev/msk/if_msk.c

1337

CSR_WRITE_1(sc, B0_POWER_CTRL,

sys/dev/msk/if_msk.c

1369

CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);

sys/dev/msk/if_msk.c

1381

CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);

sys/dev/msk/if_msk.c

1418

CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);

sys/dev/msk/if_msk.c

1419

CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);

sys/dev/msk/if_msk.c

1438

CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

sys/dev/msk/if_msk.c

1447

CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP);

sys/dev/msk/if_msk.c

1448

CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ);

sys/dev/msk/if_msk.c

1451

CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP);

sys/dev/msk/if_msk.c

1454

CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);

sys/dev/msk/if_msk.c

1455

CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

sys/dev/msk/if_msk.c

1467

CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),

sys/dev/msk/if_msk.c

1469

CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1),

sys/dev/msk/if_msk.c

1471

CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1),

sys/dev/msk/if_msk.c

1473

CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1),

sys/dev/msk/if_msk.c

1475

CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1),

sys/dev/msk/if_msk.c

1477

CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1),

sys/dev/msk/if_msk.c

1479

CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2),

sys/dev/msk/if_msk.c

1481

CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2),

sys/dev/msk/if_msk.c

1483

CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2),

sys/dev/msk/if_msk.c

1485

CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2),

sys/dev/msk/if_msk.c

1487

CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2),

sys/dev/msk/if_msk.c

1489

CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2),

sys/dev/msk/if_msk.c

1510

CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);

sys/dev/msk/if_msk.c

1513

CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

sys/dev/msk/if_msk.c

1540

CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21);

sys/dev/msk/if_msk.c

1541

CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07);

sys/dev/msk/if_msk.c

1544

CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10);

sys/dev/msk/if_msk.c

1547

CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04);

sys/dev/msk/if_msk.c

1549

CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10);

sys/dev/msk/if_msk.c

1560

CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START);

sys/dev/msk/if_msk.c

1561

CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START);

sys/dev/msk/if_msk.c

1562

CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START);

sys/dev/msk/if_msk.c

3455

CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

sys/dev/msk/if_msk.c

3479

CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);

sys/dev/msk/if_msk.c

3483

CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

sys/dev/msk/if_msk.c

3520

CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);

sys/dev/msk/if_msk.c

3522

CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

sys/dev/msk/if_msk.c

3920

CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL),

sys/dev/msk/if_msk.c

3923

CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB);

sys/dev/msk/if_msk.c

3929

CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET);

sys/dev/msk/if_msk.c

4019

CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START);

sys/dev/msk/if_msk.c

4046

CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);

sys/dev/msk/if_msk.c

4066

CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);

sys/dev/msk/if_msk.c

4070

CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR);

sys/dev/msk/if_msk.c

4080

CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);

sys/dev/msk/if_msk.c

4081

CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);

sys/dev/msk/if_msk.c

4164

CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL),

sys/dev/msk/if_msk.c

4168

CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0);

sys/dev/msk/if_msk.c

4173

CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB);

sys/dev/msk/if_msk.c

4184

CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET);

sys/dev/msk/if_msk.c

4203

CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);

sys/dev/msk/if_msk.c

4218

CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET);

sys/dev/msk/if_msk.c

509

CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),

sys/dev/msk/if_mskreg.h

2164

CSR_WRITE_1((sc_if)->msk_softc, (reg), (val))

sys/dev/netmap/if_re_netmap.h

141

CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);

sys/dev/re/if_re.c

1325

CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);

sys/dev/re/if_re.c

1328

CSR_WRITE_1(sc, RL_CFG2, cfg);

sys/dev/re/if_re.c

1329

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/re/if_re.c

1362

CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);

sys/dev/re/if_re.c

1367

CSR_WRITE_1(sc, RL_CFG2, cfg);

sys/dev/re/if_re.c

1369

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/re/if_re.c

1560

CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);

sys/dev/re/if_re.c

1563

CSR_WRITE_1(sc, sc->rl_cfg1, cfg);

sys/dev/re/if_re.c

1566

CSR_WRITE_1(sc, sc->rl_cfg5, cfg);

sys/dev/re/if_re.c

1567

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/re/if_re.c

1615

CSR_WRITE_1(sc, RL_GPIO,

sys/dev/re/if_re.c

1618

CSR_WRITE_1(sc, RL_GPIO,

sys/dev/re/if_re.c

1624

CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);

sys/dev/re/if_re.c

1626

CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);

sys/dev/re/if_re.c

2544

CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);

sys/dev/re/if_re.c

2619

CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);

sys/dev/re/if_re.c

2711

CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);

sys/dev/re/if_re.c

2949

CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);

sys/dev/re/if_re.c

3006

CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);

sys/dev/re/if_re.c

3035

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);

sys/dev/re/if_re.c

3037

CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |

sys/dev/re/if_re.c

3043

CSR_WRITE_1(sc, sc->rl_cfg4,

sys/dev/re/if_re.c

3047

CSR_WRITE_1(sc, sc->rl_cfg4,

sys/dev/re/if_re.c

3051

CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &

sys/dev/re/if_re.c

3057

CSR_WRITE_1(sc, sc->rl_cfg4,

sys/dev/re/if_re.c

3061

CSR_WRITE_1(sc, sc->rl_cfg4,

sys/dev/re/if_re.c

3065

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/re/if_re.c

3197

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);

sys/dev/re/if_re.c

3200

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/re/if_re.c

3227

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB);

sys/dev/re/if_re.c

3242

CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);

sys/dev/re/if_re.c

3260

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB);

sys/dev/re/if_re.c

3347

CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |

sys/dev/re/if_re.c

360

CSR_WRITE_1(sc, RL_EECMD, \

sys/dev/re/if_re.c

364

CSR_WRITE_1(sc, RL_EECMD, \

sys/dev/re/if_re.c

3643

CSR_WRITE_1(sc, RL_COMMAND, 0x00);

sys/dev/re/if_re.c

3645

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |

sys/dev/re/if_re.c

3659

CSR_WRITE_1(sc, RL_COMMAND, 0x00);

sys/dev/re/if_re.c

3750

CSR_WRITE_1(sc, RL_GPIO,

sys/dev/re/if_re.c

3878

CSR_WRITE_1(sc, RL_GPIO,

sys/dev/re/if_re.c

3891

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);

sys/dev/re/if_re.c

3894

CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);

sys/dev/re/if_re.c

3901

CSR_WRITE_1(sc, sc->rl_cfg1, v);

sys/dev/re/if_re.c

3907

CSR_WRITE_1(sc, sc->rl_cfg3, v);

sys/dev/re/if_re.c

3918

CSR_WRITE_1(sc, sc->rl_cfg5, v);

sys/dev/re/if_re.c

3921

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/re/if_re.c

3925

CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);

sys/dev/re/if_re.c

3948

CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);

sys/dev/re/if_re.c

3952

CSR_WRITE_1(sc, sc->rl_cfg3, v);

sys/dev/re/if_re.c

3955

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/re/if_re.c

3960

CSR_WRITE_1(sc, sc->rl_cfg5, v);

sys/dev/re/if_re.c

739

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);

sys/dev/re/if_re.c

750

CSR_WRITE_1(sc, 0x82, 1);

sys/dev/rl/if_rl.c

1706

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);

sys/dev/rl/if_rl.c

1711

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/rl/if_rl.c

1724

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);

sys/dev/rl/if_rl.c

1751

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);

sys/dev/rl/if_rl.c

1756

CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);

sys/dev/rl/if_rl.c

1914

CSR_WRITE_1(sc, RL_COMMAND, 0x00);

sys/dev/rl/if_rl.c

2037

CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);

sys/dev/rl/if_rl.c

2044

CSR_WRITE_1(sc, sc->rl_cfg1, v);

sys/dev/rl/if_rl.c

2050

CSR_WRITE_1(sc, sc->rl_cfg3, v);

sys/dev/rl/if_rl.c

2061

CSR_WRITE_1(sc, sc->rl_cfg5, v);

sys/dev/rl/if_rl.c

2064

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/rl/if_rl.c

2082

CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);

sys/dev/rl/if_rl.c

2086

CSR_WRITE_1(sc, sc->rl_cfg3, v);

sys/dev/rl/if_rl.c

2089

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/rl/if_rl.c

2094

CSR_WRITE_1(sc, sc->rl_cfg5, v);

sys/dev/rl/if_rl.c

264

CSR_WRITE_1(sc, RL_EECMD, \

sys/dev/rl/if_rl.c

268

CSR_WRITE_1(sc, RL_EECMD, \

sys/dev/rl/if_rl.c

308

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);

sys/dev/rl/if_rl.c

315

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);

sys/dev/rl/if_rl.c

330

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/rl/if_rl.c

382

CSR_WRITE_1(sc, RL_MII, val);

sys/dev/rl/if_rl.c

568

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);

sys/dev/rl/if_rlreg.h

965

CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))

sys/dev/rl/if_rlreg.h

968

CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))

sys/dev/sge/if_sge.c

1654

CSR_WRITE_1(sc, RxMacAddr + i, if_getlladdr(ifp)[i]);

sys/dev/sk/if_sk.c

424

CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);

sys/dev/sk/if_sk.c

426

CSR_WRITE_1(sc, reg, val);

sys/dev/ste/if_ste.c

1529

CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);

sys/dev/ste/if_ste.c

1538

CSR_WRITE_1(sc, STE_WAKE_EVENT, val);

sys/dev/ste/if_ste.c

1541

CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);

sys/dev/ste/if_ste.c

1547

CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));

sys/dev/ste/if_ste.c

1564

CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);

sys/dev/ste/if_ste.c

1633

CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0);

sys/dev/ste/if_ste.c

1634

CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);

sys/dev/ste/if_ste.c

1920

CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);

sys/dev/ste/if_ste.c

195

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))

sys/dev/ste/if_ste.c

198

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))

sys/dev/ste/if_ste.c

2093

CSR_WRITE_1(sc, STE_WAKE_EVENT, 0);

sys/dev/ste/if_ste.c

2103

CSR_WRITE_1(sc, STE_WAKE_EVENT, val);

sys/dev/ste/if_ste.c

228

CSR_WRITE_1(sc, STE_PHYCTL, val);

sys/dev/ste/if_ste.c

452

CSR_WRITE_1(sc, STE_RX_MODE, rxcfg);

sys/dev/stge/if_stge.c

1028

CSR_WRITE_1(sc, STGE_WakeEvent, v);

sys/dev/stge/if_stge.c

1950

CSR_WRITE_1(sc, STGE_PhySet, v);

sys/dev/stge/if_stge.c

2045

CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);

sys/dev/stge/if_stge.c

2048

CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);

sys/dev/stge/if_stge.c

2054

CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);

sys/dev/stge/if_stge.c

2055

CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);

sys/dev/stge/if_stge.c

2061

CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);

sys/dev/stge/if_stge.c

2062

CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);

sys/dev/stge/if_stge.c

2275

CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);

sys/dev/stge/if_stge.c

2297

CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);

sys/dev/stge/if_stge.c

273

CSR_WRITE_1(sc, STGE_PhyCtrl, val);

sys/dev/stge/if_stge.c

985

CSR_WRITE_1(sc, STGE_WakeEvent, v);

sys/dev/vge/if_vge.c

1056

CSR_WRITE_1(sc, VGE_EECSR, VGE_EECSR_RELOAD);

sys/dev/vge/if_vge.c

1669

CSR_WRITE_1(sc, VGE_CRC2, VGE_CR2_FDX_TXFLOWCTL_ENABLE |

sys/dev/vge/if_vge.c

1673

CSR_WRITE_1(sc, VGE_CRS2,

sys/dev/vge/if_vge.c

1676

CSR_WRITE_1(sc, VGE_CRS2,

sys/dev/vge/if_vge.c

1727

CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);

sys/dev/vge/if_vge.c

1728

CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);

sys/dev/vge/if_vge.c

1766

CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);

sys/dev/vge/if_vge.c

1777

CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);

sys/dev/vge/if_vge.c

1778

CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);

sys/dev/vge/if_vge.c

1795

CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);

sys/dev/vge/if_vge.c

2045

CSR_WRITE_1(sc, VGE_PAR0 + i, if_getlladdr(sc->vge_ifp)[i]);

sys/dev/vge/if_vge.c

2088

CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);

sys/dev/vge/if_vge.c

2089

CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);

sys/dev/vge/if_vge.c

2109

CSR_WRITE_1(sc, VGE_CRC2, 0xFF);

sys/dev/vge/if_vge.c

2110

CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_XON_ENABLE | 0x0B);

sys/dev/vge/if_vge.c

2115

CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP);

sys/dev/vge/if_vge.c

2116

CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL);

sys/dev/vge/if_vge.c

2117

CSR_WRITE_1(sc, VGE_CRS0,

sys/dev/vge/if_vge.c

2135

CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);

sys/dev/vge/if_vge.c

2306

CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);

sys/dev/vge/if_vge.c

2315

CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);

sys/dev/vge/if_vge.c

2401

CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);

sys/dev/vge/if_vge.c

2402

CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP);

sys/dev/vge/if_vge.c

2405

CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF);

sys/dev/vge/if_vge.c

251

CSR_WRITE_1(sc, VGE_EEADDR, addr);

sys/dev/vge/if_vge.c

2597

CSR_WRITE_1(sc, VGE_MIBCSR,

sys/dev/vge/if_vge.c

2599

CSR_WRITE_1(sc, VGE_MIBCSR,

sys/dev/vge/if_vge.c

2608

CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) &

sys/dev/vge/if_vge.c

2625

CSR_WRITE_1(sc, VGE_MIBCSR,

sys/dev/vge/if_vge.c

2641

CSR_WRITE_1(sc, VGE_MIBCSR,

sys/dev/vge/if_vge.c

2730

CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_TXSUPPTHR);

sys/dev/vge/if_vge.c

2731

CSR_WRITE_1(sc, VGE_TXSUPPTHR, sc->vge_tx_coal_pkt);

sys/dev/vge/if_vge.c

2734

CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR);

sys/dev/vge/if_vge.c

2735

CSR_WRITE_1(sc, VGE_RXSUPPTHR, sc->vge_rx_coal_pkt);

sys/dev/vge/if_vge.c

2748

CSR_WRITE_1(sc, VGE_INTCTL1, intctl);

sys/dev/vge/if_vge.c

2749

CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_HOLDOFF);

sys/dev/vge/if_vge.c

2752

CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF);

sys/dev/vge/if_vge.c

2753

CSR_WRITE_1(sc, VGE_INTHOLDOFF,

sys/dev/vge/if_vge.c

2756

CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF);

sys/dev/vge/if_vge.c

2841

CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL);

sys/dev/vge/if_vge.c

2843

CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F);

sys/dev/vge/if_vge.c

2844

CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM |

sys/dev/vge/if_vge.c

2853

CSR_WRITE_1(sc, VGE_WOLCR1S, val);

sys/dev/vge/if_vge.c

2857

CSR_WRITE_1(sc, VGE_WOLCFGS, val | VGE_WOLCFG_PMEOVR);

sys/dev/vge/if_vge.c

2866

CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF);

sys/dev/vge/if_vge.c

2867

CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF);

sys/dev/vge/if_vge.c

2871

CSR_WRITE_1(sc, VGE_PWRSTAT, val);

sys/dev/vge/if_vge.c

2875

CSR_WRITE_1(sc, VGE_PWRSTAT, val);

sys/dev/vge/if_vge.c

2888

CSR_WRITE_1(sc, VGE_PWRSTAT, val);

sys/dev/vge/if_vge.c

2892

CSR_WRITE_1(sc, VGE_PWRSTAT, val);

sys/dev/vge/if_vge.c

2898

CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL);

sys/dev/vge/if_vge.c

2900

CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F);

sys/dev/vge/if_vge.c

2901

CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM |

sys/dev/vge/if_vge.c

2904

CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF);

sys/dev/vge/if_vge.c

2905

CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF);

sys/dev/vge/if_vge.c

308

CSR_WRITE_1(sc, VGE_MIICMD, 0);

sys/dev/vge/if_vge.c

327

CSR_WRITE_1(sc, VGE_MIICMD, 0);

sys/dev/vge/if_vge.c

328

CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);

sys/dev/vge/if_vge.c

343

CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);

sys/dev/vge/if_vge.c

369

CSR_WRITE_1(sc, VGE_MIIADDR, reg);

sys/dev/vge/if_vge.c

402

CSR_WRITE_1(sc, VGE_MIIADDR, reg);

sys/dev/vge/if_vge.c

440

CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);

sys/dev/vge/if_vge.c

442

CSR_WRITE_1(sc, VGE_CAM0 + i, 0);

sys/dev/vge/if_vge.c

446

CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0);

sys/dev/vge/if_vge.c

448

CSR_WRITE_1(sc, VGE_CAM0 + i, 0);

sys/dev/vge/if_vge.c

450

CSR_WRITE_1(sc, VGE_CAMADDR, 0);

sys/dev/vge/if_vge.c

470

CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx);

sys/dev/vge/if_vge.c

474

CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]);

sys/dev/vge/if_vge.c

504

CSR_WRITE_1(sc, VGE_CAMADDR, 0);

sys/dev/vge/if_vge.c

525

CSR_WRITE_1(sc, VGE_RXCFG, cfg);

sys/dev/vge/if_vge.c

611

CSR_WRITE_1(sc, VGE_RXCTL, rxcfg);

sys/dev/vge/if_vge.c

619

CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET);

sys/dev/vge/if_vge.c

629

CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE);

sys/dev/vge/if_vgevar.h

231

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))

sys/dev/vge/if_vgevar.h

238

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))

sys/dev/vr/if_vr.c

1414

CSR_WRITE_1(sc, VR_FLOWCR0, prog);

sys/dev/vr/if_vr.c

2038

CSR_WRITE_1(sc, VR_PAR0 + i, if_getlladdr(sc->vr_ifp)[i]);

sys/dev/vr/if_vr.c

2102

CSR_WRITE_1(sc, VR_CR1, VR_CR1_FULLDUPLEX | VR_CR1_TX_NOPOLL);

sys/dev/vr/if_vr.c

2125

CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT - 1);

sys/dev/vr/if_vr.c

2130

CSR_WRITE_1(sc, VR_FLOWCR1,

sys/dev/vr/if_vr.c

2137

CSR_WRITE_1(sc, VR_CR0,

sys/dev/vr/if_vr.c

2350

CSR_WRITE_1(sc, VR_CR0, cmd);

sys/dev/vr/if_vr.c

2369

CSR_WRITE_1(sc, VR_CR0, cmd);

sys/dev/vr/if_vr.c

2371

CSR_WRITE_1(sc, VR_CR0, cmd | VR_CR0_RX_GO);

sys/dev/vr/if_vr.c

2383

CSR_WRITE_1(sc, VR_CR0, cmd);

sys/dev/vr/if_vr.c

2405

CSR_WRITE_1(sc, VR_CR0, cmd);

sys/dev/vr/if_vr.c

2438

CSR_WRITE_1(sc, VR_CR0, VR_CR0_STOP);

sys/dev/vr/if_vr.c

248

CSR_WRITE_1(sc, VR_MIIADDR, reg);

sys/dev/vr/if_vr.c

2539

CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF);

sys/dev/vr/if_vr.c

2540

CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_SAB | VR_WOLCFG_SAM);

sys/dev/vr/if_vr.c

2541

CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF);

sys/dev/vr/if_vr.c

2542

CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN);

sys/dev/vr/if_vr.c

2545

CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE);

sys/dev/vr/if_vr.c

2546

CSR_WRITE_1(sc, VR_TESTREG_CLR, 3);

sys/dev/vr/if_vr.c

2547

CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3);

sys/dev/vr/if_vr.c

2550

CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_UCAST);

sys/dev/vr/if_vr.c

2552

CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_MAGIC);

sys/dev/vr/if_vr.c

2560

CSR_WRITE_1(sc, VR_WOLCFG_SET, VR_WOLCFG_SAB | VR_WOLCFG_SAM);

sys/dev/vr/if_vr.c

2562

CSR_WRITE_1(sc, VR_STICKHW, v | VR_STICKHW_WOL_ENB);

sys/dev/vr/if_vr.c

2563

CSR_WRITE_1(sc, VR_PWRCFG_SET, VR_PWRCFG_WOLEN);

sys/dev/vr/if_vr.c

2569

CSR_WRITE_1(sc, VR_STICKHW, v);

sys/dev/vr/if_vr.c

2589

CSR_WRITE_1(sc, VR_STICKHW, v);

sys/dev/vr/if_vr.c

2592

CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF);

sys/dev/vr/if_vr.c

2593

CSR_WRITE_1(sc, VR_WOLCFG_CLR,

sys/dev/vr/if_vr.c

2595

CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF);

sys/dev/vr/if_vr.c

2596

CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN);

sys/dev/vr/if_vr.c

2599

CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE);

sys/dev/vr/if_vr.c

2600

CSR_WRITE_1(sc, VR_TESTREG_CLR, 3);

sys/dev/vr/if_vr.c

2601

CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3);

sys/dev/vr/if_vr.c

271

CSR_WRITE_1(sc, VR_MIIADDR, reg);

sys/dev/vr/if_vr.c

342

CSR_WRITE_1(sc, VR_CR1, cr1);

sys/dev/vr/if_vr.c

357

CSR_WRITE_1(sc, VR_FLOWCR1, fc);

sys/dev/vr/if_vr.c

365

CSR_WRITE_1(sc, VR_MISC_CR0, fc);

sys/dev/vr/if_vr.c

384

CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);

sys/dev/vr/if_vr.c

386

CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);

sys/dev/vr/if_vr.c

388

CSR_WRITE_1(sc, VR_CAMCTL, 0);

sys/dev/vr/if_vr.c

399

CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);

sys/dev/vr/if_vr.c

401

CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);

sys/dev/vr/if_vr.c

404

CSR_WRITE_1(sc, VR_CAMADDR, idx);

sys/dev/vr/if_vr.c

408

CSR_WRITE_1(sc, VR_MCAM0 + i, mac[i]);

sys/dev/vr/if_vr.c

410

CSR_WRITE_1(sc, VR_VCAM0, mac[0]);

sys/dev/vr/if_vr.c

411

CSR_WRITE_1(sc, VR_VCAM1, mac[1]);

sys/dev/vr/if_vr.c

415

CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_WRITE);

sys/dev/vr/if_vr.c

425

CSR_WRITE_1(sc, VR_CAMCTL, 0);

sys/dev/vr/if_vr.c

491

CSR_WRITE_1(sc, VR_RXCFG, rxfilt);

sys/dev/vr/if_vr.c

527

CSR_WRITE_1(sc, VR_RXCFG, rxfilt);

sys/dev/vr/if_vr.c

537

CSR_WRITE_1(sc, VR_CR1, VR_CR1_RESET);

sys/dev/vr/if_vrreg.h

756

#define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))

sys/dev/vr/if_vrreg.h

757

#define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))

sys/dev/xl/if_xl.c

2092

CSR_WRITE_1(sc, XL_DOWN_POLL, 64);

sys/dev/xl/if_xl.c

2106

CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);

sys/dev/xl/if_xl.c

2129

CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);

sys/dev/xl/if_xl.c

2701

CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,

sys/dev/xl/if_xl.c

2742

CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);

sys/dev/xl/if_xl.c

2782

CSR_WRITE_1(sc, XL_DOWN_POLL, 64);

sys/dev/xl/if_xl.c

2815

CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);

sys/dev/xl/if_xl.c

468

CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);

sys/dev/xl/if_xl.c

809

CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);

sys/dev/xl/if_xl.c

813

CSR_WRITE_1(sc, XL_W3_MAC_CTRL,