sys/dev/mgb/if_mgb.c

1187

id_rev = CSR_READ_REG(sc, 0);

sys/dev/mgb/if_mgb.c

1281

ring_config = CSR_READ_REG(sc, MGB_DMA_RX_CONFIG1(channel));

sys/dev/mgb/if_mgb.c

1291

rdata->last_head = CSR_READ_REG(sc, MGB_DMA_RX_HEAD(channel));

sys/dev/mgb/if_mgb.c

1345

ring_config = CSR_READ_REG(sc, MGB_DMA_TX_CONFIG1(channel));

sys/dev/mgb/if_mgb.c

1364

rdata->last_head = CSR_READ_REG(sc, MGB_DMA_TX_HEAD(channel));

sys/dev/mgb/if_mgb.c

1523

val = CSR_READ_REG(sc, reg);

sys/dev/mgb/if_mgb.c

629

if (CSR_READ_REG(sc, i) != 0)

sys/dev/mgb/if_mgb.c

631

CSR_READ_REG(sc, i));

sys/dev/mgb/if_mgb.c

681

CSR_READ_REG(sc, stats[i - 1]));

sys/dev/mgb/if_mgb.c

699

while ((CSR_READ_REG(sc, 0x24) & 0x80000000) == 0) // DP_SEL & READY

sys/dev/mgb/if_mgb.c

703

CSR_READ_REG(sc, 0x30)); // DP_DATA

sys/dev/mgb/if_mgb.c

750

intr_sts = CSR_READ_REG(sc, MGB_INTR_STS);

sys/dev/mgb/if_mgb.c

751

intr_en = CSR_READ_REG(sc, MGB_INTR_ENBL_SET);

sys/dev/mgb/if_mgb.c

775

intr_sts = CSR_READ_REG(sc, MGB_INTR_STS);

sys/dev/mgb/if_mgb.c

776

intr_en = CSR_READ_REG(sc, MGB_INTR_ENBL_SET);

sys/dev/mgb/if_mgb.h

112

CSR_READ_REG(sc, MGB_DMAC_CMD) & MGB_DMAC_CMD_START(_s, _ch), \

sys/dev/mgb/if_mgb.h

113

CSR_READ_REG(sc, MGB_DMAC_CMD) & MGB_DMAC_CMD_STOP(_s, _ch)))

sys/dev/mgb/if_mgb.h

237

CSR_WRITE_REG(sc, reg, CSR_READ_REG(sc, reg) & ~(bits))

sys/dev/mgb/if_mgb.h

240

CSR_WRITE_REG(sc, reg, CSR_READ_REG(sc, reg) | (val))