CSR_READ_4 - FreeBSD

sys/dev/age/if_age.c

1404

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

1859

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

1913

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

1979

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

1981

CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |

sys/dev/age/if_age.c

2097

status = CSR_READ_4(sc, AGE_INTR_STATUS);

sys/dev/age/if_age.c

219

v = CSR_READ_4(sc, AGE_MDIO);

sys/dev/age/if_age.c

249

v = CSR_READ_4(sc, AGE_MDIO);

sys/dev/age/if_age.c

2512

CSR_READ_4(sc, AGE_MASTER_CFG);

sys/dev/age/if_age.c

2515

if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)

sys/dev/age/if_age.c

2524

CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);

sys/dev/age/if_age.c

2643

reg = CSR_READ_4(sc, AGE_MASTER_CFG);

sys/dev/age/if_age.c

2684

CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);

sys/dev/age/if_age.c

2704

reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);

sys/dev/age/if_age.c

2711

reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);

sys/dev/age/if_age.c

2799

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

2851

CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));

sys/dev/age/if_age.c

2854

CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);

sys/dev/age/if_age.c

2856

CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);

sys/dev/age/if_age.c

2858

if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)

sys/dev/age/if_age.c

2905

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

2911

reg = CSR_READ_4(sc, AGE_DMA_CFG);

sys/dev/age/if_age.c

2917

if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &

sys/dev/age/if_age.c

2934

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

2940

reg = CSR_READ_4(sc, AGE_DMA_CFG);

sys/dev/age/if_age.c

2946

if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &

sys/dev/age/if_age.c

3107

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

3137

rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

340

reg = CSR_READ_4(sc, AGE_SPI_CTRL);

sys/dev/age/if_age.c

352

CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |

sys/dev/age/if_age.c

356

reg = CSR_READ_4(sc, AGE_TWSI_CTRL);

sys/dev/age/if_age.c

369

ea[0] = CSR_READ_4(sc, AGE_PAR0);

sys/dev/age/if_age.c

370

ea[1] = CSR_READ_4(sc, AGE_PAR1);

sys/dev/age/if_age.c

496

sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>

sys/dev/age/if_age.c

520

CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),

sys/dev/age/if_age.c

521

CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));

sys/dev/alc/if_alc.c

1020

val = CSR_READ_4(sc, ALC_GPHY_CFG);

sys/dev/alc/if_alc.c

1052

val = CSR_READ_4(sc, ALC_LPI_CTL);

sys/dev/alc/if_alc.c

1101

gphy = CSR_READ_4(sc, ALC_GPHY_CFG);

sys/dev/alc/if_alc.c

1156

pmcfg = CSR_READ_4(sc, ALC_PM_CFG);

sys/dev/alc/if_alc.c

1240

pmcfg = CSR_READ_4(sc, ALC_PM_CFG);

sys/dev/alc/if_alc.c

1278

val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);

sys/dev/alc/if_alc.c

1284

CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);

sys/dev/alc/if_alc.c

1286

CSR_READ_4(sc, ALC_PCIE_PHYMISC) |

sys/dev/alc/if_alc.c

1290

val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);

sys/dev/alc/if_alc.c

1322

val = CSR_READ_4(sc, ALC_PDLL_TRNS1);

sys/dev/alc/if_alc.c

1325

val = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/alc/if_alc.c

1357

ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER);

sys/dev/alc/if_alc.c

1450

if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC)

sys/dev/alc/if_alc.c

1477

sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>

sys/dev/alc/if_alc.c

1489

CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,

sys/dev/alc/if_alc.c

1490

CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);

sys/dev/alc/if_alc.c

2540

reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);

sys/dev/alc/if_alc.c

2546

CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);

sys/dev/alc/if_alc.c

2554

CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS);

sys/dev/alc/if_alc.c

2561

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/alc/if_alc.c

2570

reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);

sys/dev/alc/if_alc.c

2577

CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);

sys/dev/alc/if_alc.c

2593

master = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/alc/if_alc.c

2595

gphy = CSR_READ_4(sc, ALC_GPHY_CFG);

sys/dev/alc/if_alc.c

2602

mac = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/alc/if_alc.c

2613

mac = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/alc/if_alc.c

2625

reg = CSR_READ_4(sc, ALC_MISC);

sys/dev/alc/if_alc.c

2633

reg = CSR_READ_4(sc, ALC_PDLL_TRNS1);

sys/dev/alc/if_alc.c

307

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/alc/if_alc.c

3139

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/alc/if_alc.c

3187

CSR_READ_4(sc, ALC_RX_MIB_BASE + i);

sys/dev/alc/if_alc.c

3193

CSR_READ_4(sc, ALC_TX_MIB_BASE + i);

sys/dev/alc/if_alc.c

3224

*reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);

sys/dev/alc/if_alc.c

3230

*reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);

sys/dev/alc/if_alc.c

3328

status = CSR_READ_4(sc, ALC_INTR_STATUS);

sys/dev/alc/if_alc.c

334

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/alc/if_alc.c

3349

status = CSR_READ_4(sc, ALC_INTR_STATUS);

sys/dev/alc/if_alc.c

3396

(CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) {

sys/dev/alc/if_alc.c

3436

prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);

sys/dev/alc/if_alc.c

372

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/alc/if_alc.c

3776

reg = CSR_READ_4(sc, ALC_MISC3);

sys/dev/alc/if_alc.c

3781

reg = CSR_READ_4(sc, ALC_MISC);

sys/dev/alc/if_alc.c

3792

reg = CSR_READ_4(sc, ALC_MISC2);

sys/dev/alc/if_alc.c

3822

pmcfg = CSR_READ_4(sc, ALC_PM_CFG);

sys/dev/alc/if_alc.c

3831

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/alc/if_alc.c

3838

if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0)

sys/dev/alc/if_alc.c

3846

if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)

sys/dev/alc/if_alc.c

3853

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/alc/if_alc.c

3865

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/alc/if_alc.c

3875

reg = CSR_READ_4(sc, ALC_MISC3);

sys/dev/alc/if_alc.c

3879

reg = CSR_READ_4(sc, ALC_MISC);

sys/dev/alc/if_alc.c

3890

CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |

sys/dev/alc/if_alc.c

3960

CSR_READ_4(sc, ALC_WOL_CFG);

sys/dev/alc/if_alc.c

398

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/alc/if_alc.c

4044

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/alc/if_alc.c

4169

reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);

sys/dev/alc/if_alc.c

4185

reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);

sys/dev/alc/if_alc.c

4319

reg = CSR_READ_4(sc, ALC_DMA_CFG);

sys/dev/alc/if_alc.c

4369

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/alc/if_alc.c

4375

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/alc/if_alc.c

4400

cfg = CSR_READ_4(sc, ALC_RXQ_CFG);

sys/dev/alc/if_alc.c

4408

cfg = CSR_READ_4(sc, ALC_TXQ_CFG);

sys/dev/alc/if_alc.c

4420

reg = CSR_READ_4(sc, ALC_RXQ_CFG);

sys/dev/alc/if_alc.c

4433

reg = CSR_READ_4(sc, ALC_TXQ_CFG);

sys/dev/alc/if_alc.c

4440

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/alc/if_alc.c

449

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/alc/if_alc.c

4560

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/alc/if_alc.c

4592

rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/alc/if_alc.c

493

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/alc/if_alc.c

524

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/alc/if_alc.c

707

opt = CSR_READ_4(sc, ALC_OPT_CFG);

sys/dev/alc/if_alc.c

708

if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&

sys/dev/alc/if_alc.c

709

(CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {

sys/dev/alc/if_alc.c

721

CSR_READ_4(sc, ALC_OPT_CFG);

sys/dev/alc/if_alc.c

746

CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);

sys/dev/alc/if_alc.c

748

CSR_READ_4(sc, ALC_WOL_CFG);

sys/dev/alc/if_alc.c

750

CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |

sys/dev/alc/if_alc.c

754

if ((CSR_READ_4(sc, ALC_TWSI_CFG) &

sys/dev/alc/if_alc.c

772

CSR_READ_4(sc, ALC_OPT_CFG);

sys/dev/alc/if_alc.c

809

reg = CSR_READ_4(sc, ALC_SLD);

sys/dev/alc/if_alc.c

818

reg = CSR_READ_4(sc, ALC_SLD);

sys/dev/alc/if_alc.c

831

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/alc/if_alc.c

835

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/alc/if_alc.c

846

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/alc/if_alc.c

864

ea[0] = CSR_READ_4(sc, ALC_PAR0);

sys/dev/alc/if_alc.c

865

ea[1] = CSR_READ_4(sc, ALC_PAR1);

sys/dev/alc/if_alc.c

881

pmcfg = CSR_READ_4(sc, ALC_PM_CFG);

sys/dev/ale/if_ale.c

1475

reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);

sys/dev/ale/if_ale.c

1497

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/ale/if_ale.c

1508

reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);

sys/dev/ale/if_ale.c

2041

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/ale/if_ale.c

2072

CSR_READ_4(sc, ALE_RX_MIB_BASE + i);

sys/dev/ale/if_ale.c

2077

CSR_READ_4(sc, ALE_TX_MIB_BASE + i);

sys/dev/ale/if_ale.c

2099

*reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);

sys/dev/ale/if_ale.c

2104

*reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);

sys/dev/ale/if_ale.c

213

v = CSR_READ_4(sc, ALE_MDIO);

sys/dev/ale/if_ale.c

2188

status = CSR_READ_4(sc, ALE_INTR_STATUS);

sys/dev/ale/if_ale.c

2208

status = CSR_READ_4(sc, ALE_INTR_STATUS);

sys/dev/ale/if_ale.c

2249

(CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) {

sys/dev/ale/if_ale.c

240

v = CSR_READ_4(sc, ALE_MDIO);

sys/dev/ale/if_ale.c

2553

CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);

sys/dev/ale/if_ale.c

2558

if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)

sys/dev/ale/if_ale.c

2565

if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)

sys/dev/ale/if_ale.c

2622

CSR_READ_4(sc, ALE_WOL_CFG);

sys/dev/ale/if_ale.c

2674

reg = CSR_READ_4(sc, ALE_MASTER_CFG);

sys/dev/ale/if_ale.c

2736

reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);

sys/dev/ale/if_ale.c

2838

reg = CSR_READ_4(sc, ALE_TXQ_CFG);

sys/dev/ale/if_ale.c

2841

reg = CSR_READ_4(sc, ALE_RXQ_CFG);

sys/dev/ale/if_ale.c

2844

reg = CSR_READ_4(sc, ALE_DMA_CFG);

sys/dev/ale/if_ale.c

2877

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/ale/if_ale.c

2884

reg = CSR_READ_4(sc, ALE_IDLE_STATUS);

sys/dev/ale/if_ale.c

290

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/ale/if_ale.c

2955

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/ale/if_ale.c

2984

rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/ale/if_ale.c

363

reg = CSR_READ_4(sc, ALE_SPI_CTRL);

sys/dev/ale/if_ale.c

374

CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |

sys/dev/ale/if_ale.c

378

reg = CSR_READ_4(sc, ALE_TWSI_CTRL);

sys/dev/ale/if_ale.c

391

ea[0] = CSR_READ_4(sc, ALE_PAR0);

sys/dev/ale/if_ale.c

392

ea[1] = CSR_READ_4(sc, ALE_PAR1);

sys/dev/ale/if_ale.c

492

if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {

sys/dev/ale/if_ale.c

518

sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>

sys/dev/ale/if_ale.c

526

txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);

sys/dev/ale/if_ale.c

527

rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);

sys/dev/bfe/if_bfe.c

1001

if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)

sys/dev/bfe/if_bfe.c

1013

CSR_READ_4(sc, BFE_SBTMSLOW);

sys/dev/bfe/if_bfe.c

1030

CSR_READ_4(sc, BFE_SBTMSLOW);

sys/dev/bfe/if_bfe.c

1034

if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)

sys/dev/bfe/if_bfe.c

1036

val = CSR_READ_4(sc, BFE_SBIMSTATE);

sys/dev/bfe/if_bfe.c

1042

CSR_READ_4(sc, BFE_SBTMSLOW);

sys/dev/bfe/if_bfe.c

1047

CSR_READ_4(sc, BFE_SBTMSLOW);

sys/dev/bfe/if_bfe.c

1088

val = CSR_READ_4(sc, BFE_RXCONF);

sys/dev/bfe/if_bfe.c

1153

ptr[i/2] = CSR_READ_4(sc, 4096 + i);

sys/dev/bfe/if_bfe.c

1163

u_int32_t val = CSR_READ_4(sc, reg);

sys/dev/bfe/if_bfe.c

1193

*val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;

sys/dev/bfe/if_bfe.c

1249

*val++ = CSR_READ_4(sc, reg);

sys/dev/bfe/if_bfe.c

1251

*val++ = CSR_READ_4(sc, reg);

sys/dev/bfe/if_bfe.c

1335

chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;

sys/dev/bfe/if_bfe.c

1380

status = CSR_READ_4(sc, BFE_DMARX_STAT);

sys/dev/bfe/if_bfe.c

1444

istat = CSR_READ_4(sc, BFE_ISTAT);

sys/dev/bfe/if_bfe.c

1453

CSR_READ_4(sc, BFE_ISTAT);

sys/dev/bfe/if_bfe.c

664

val = CSR_READ_4(sc, BFE_TX_CTRL);

sys/dev/bfe/if_bfe.c

669

flow = CSR_READ_4(sc, BFE_RXCONF);

sys/dev/bfe/if_bfe.c

679

flow = CSR_READ_4(sc, BFE_MAC_FLOW);

sys/dev/bfe/if_bfe.c

859

val = CSR_READ_4(sc, BFE_SBINTVEC);

sys/dev/bfe/if_bfe.c

863

val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);

sys/dev/bfe/if_bfe.c

879

CSR_READ_4(sc, reg);

sys/dev/bfe/if_bfe.c

881

CSR_READ_4(sc, reg);

sys/dev/bfe/if_bfe.c

905

CSR_READ_4(sc, BFE_IMASK);

sys/dev/bfe/if_bfe.c

926

val = CSR_READ_4(sc, BFE_SBTMSLOW) &

sys/dev/bfe/if_bfe.c

934

if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)

sys/dev/bfe/if_bfe.c

953

val = CSR_READ_4(sc, BFE_DEVCTRL);

sys/dev/bfe/if_bfe.c

956

else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {

sys/dev/bfe/if_bfereg.h

449

CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val)

sys/dev/bfe/if_bfereg.h

452

CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val)

sys/dev/bge/if_bge.c

1001

CSR_READ_4(sc, BGE_NVRAM_SWARB);

sys/dev/bge/if_bge.c

1057

if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)

sys/dev/bge/if_bge.c

1067

byte = CSR_READ_4(sc, BGE_EE_DATA);

sys/dev/bge/if_bge.c

1118

val = CSR_READ_4(sc, BGE_MI_COMM);

sys/dev/bge/if_bge.c

1121

val = CSR_READ_4(sc, BGE_MI_COMM);

sys/dev/bge/if_bge.c

1174

if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {

sys/dev/bge/if_bge.c

1176

CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */

sys/dev/bge/if_bge.c

1240

mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &

sys/dev/bge/if_bge.c

1242

tx_mode = CSR_READ_4(sc, BGE_TX_MODE);

sys/dev/bge/if_bge.c

1243

rx_mode = CSR_READ_4(sc, BGE_RX_MODE);

sys/dev/bge/if_bge.c

1704

CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);

sys/dev/bge/if_bge.c

1707

if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &

sys/dev/bge/if_bge.c

1776

CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |

sys/dev/bge/if_bge.c

1823

tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;

sys/dev/bge/if_bge.c

1870

mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &

sys/dev/bge/if_bge.c

1911

CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */

sys/dev/bge/if_bge.c

1995

if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)

sys/dev/bge/if_bge.c

2011

if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)

sys/dev/bge/if_bge.c

2156

(CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);

sys/dev/bge/if_bge.c

2282

val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &

sys/dev/bge/if_bge.c

2308

if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))

sys/dev/bge/if_bge.c

2447

val |= CSR_READ_4(sc, BGE_RDMA_MODE) &

sys/dev/bge/if_bge.c

2465

dmactl = CSR_READ_4(sc, rdmareg);

sys/dev/bge/if_bge.c

2490

CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |

sys/dev/bge/if_bge.c

2499

CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |

sys/dev/bge/if_bge.c

2504

CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |

sys/dev/bge/if_bge.c

2514

val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);

sys/dev/bge/if_bge.c

2521

val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);

sys/dev/bge/if_bge.c

3247

cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;

sys/dev/bge/if_bge.c

3251

clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;

sys/dev/bge/if_bge.c

3353

if (CSR_READ_4(sc, BGE_SGDIG_STS) &

sys/dev/bge/if_bge.c

3359

if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &

sys/dev/bge/if_bge.c

3501

misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;

sys/dev/bge/if_bge.c

3901

CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &

sys/dev/bge/if_bge.c

4021

mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;

sys/dev/bge/if_bge.c

4036

if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &

sys/dev/bge/if_bge.c

4078

if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */

sys/dev/bge/if_bge.c

4089

val = CSR_READ_4(sc, BGE_VCPU_STATUS);

sys/dev/bge/if_bge.c

4092

val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);

sys/dev/bge/if_bge.c

4179

val = CSR_READ_4(sc, BGE_MSI_MODE);

sys/dev/bge/if_bge.c

4183

val = CSR_READ_4(sc, BGE_MARB_MODE);

sys/dev/bge/if_bge.c

4191

val = CSR_READ_4(sc, BGE_MAC_MODE);

sys/dev/bge/if_bge.c

4200

val = CSR_READ_4(sc, BGE_VCPU_STATUS);

sys/dev/bge/if_bge.c

4239

val = CSR_READ_4(sc, BGE_SERDES_CFG);

sys/dev/bge/if_bge.c

4250

val = CSR_READ_4(sc, 0x7C00);

sys/dev/bge/if_bge.c

4439

if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));

sys/dev/bge/if_bge.c

4696

statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;

sys/dev/bge/if_bge.c

4746

CSR_READ_4(sc, BGE_RX_CPU_EVENT) |

sys/dev/bge/if_bge.c

4816

CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);

sys/dev/bge/if_bge.c

4818

CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);

sys/dev/bge/if_bge.c

4820

CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);

sys/dev/bge/if_bge.c

4822

CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);

sys/dev/bge/if_bge.c

4824

CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);

sys/dev/bge/if_bge.c

4826

CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);

sys/dev/bge/if_bge.c

4828

CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);

sys/dev/bge/if_bge.c

4830

CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);

sys/dev/bge/if_bge.c

4832

CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);

sys/dev/bge/if_bge.c

4834

CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);

sys/dev/bge/if_bge.c

4836

CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);

sys/dev/bge/if_bge.c

4838

CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);

sys/dev/bge/if_bge.c

4840

CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);

sys/dev/bge/if_bge.c

4843

CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);

sys/dev/bge/if_bge.c

4845

CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);

sys/dev/bge/if_bge.c

4847

CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);

sys/dev/bge/if_bge.c

4849

CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);

sys/dev/bge/if_bge.c

4851

CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);

sys/dev/bge/if_bge.c

4853

CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);

sys/dev/bge/if_bge.c

4855

CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);

sys/dev/bge/if_bge.c

4857

CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);

sys/dev/bge/if_bge.c

4859

CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);

sys/dev/bge/if_bge.c

4861

CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);

sys/dev/bge/if_bge.c

4863

CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);

sys/dev/bge/if_bge.c

4865

CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);

sys/dev/bge/if_bge.c

4867

CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);

sys/dev/bge/if_bge.c

4869

CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);

sys/dev/bge/if_bge.c

4872

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);

sys/dev/bge/if_bge.c

4874

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);

sys/dev/bge/if_bge.c

4876

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);

sys/dev/bge/if_bge.c

4878

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);

sys/dev/bge/if_bge.c

4902

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);

sys/dev/bge/if_bge.c

4904

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);

sys/dev/bge/if_bge.c

4906

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);

sys/dev/bge/if_bge.c

4916

val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);

sys/dev/bge/if_bge.c

4931

CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);

sys/dev/bge/if_bge.c

4932

CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);

sys/dev/bge/if_bge.c

4933

CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);

sys/dev/bge/if_bge.c

4934

CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);

sys/dev/bge/if_bge.c

4935

CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);

sys/dev/bge/if_bge.c

4936

CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);

sys/dev/bge/if_bge.c

4937

CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);

sys/dev/bge/if_bge.c

4938

CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);

sys/dev/bge/if_bge.c

4939

CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);

sys/dev/bge/if_bge.c

4940

CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);

sys/dev/bge/if_bge.c

4941

CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);

sys/dev/bge/if_bge.c

4942

CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);

sys/dev/bge/if_bge.c

4943

CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);

sys/dev/bge/if_bge.c

4945

CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);

sys/dev/bge/if_bge.c

4946

CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);

sys/dev/bge/if_bge.c

4947

CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);

sys/dev/bge/if_bge.c

4948

CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);

sys/dev/bge/if_bge.c

4949

CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);

sys/dev/bge/if_bge.c

4950

CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);

sys/dev/bge/if_bge.c

4951

CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);

sys/dev/bge/if_bge.c

4952

CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);

sys/dev/bge/if_bge.c

4953

CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);

sys/dev/bge/if_bge.c

4954

CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);

sys/dev/bge/if_bge.c

4955

CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);

sys/dev/bge/if_bge.c

4956

CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);

sys/dev/bge/if_bge.c

4957

CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);

sys/dev/bge/if_bge.c

4958

CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);

sys/dev/bge/if_bge.c

4960

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);

sys/dev/bge/if_bge.c

4961

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);

sys/dev/bge/if_bge.c

4962

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);

sys/dev/bge/if_bge.c

4963

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);

sys/dev/bge/if_bge.c

4964

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);

sys/dev/bge/if_bge.c

4965

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);

sys/dev/bge/if_bge.c

4966

CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);

sys/dev/bge/if_bge.c

4981

CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))

sys/dev/bge/if_bge.c

5522

mode = CSR_READ_4(sc, BGE_TX_MODE);

sys/dev/bge/if_bge.c

5528

mode |= CSR_READ_4(sc, BGE_TX_MODE) &

sys/dev/bge/if_bge.c

5536

mode = CSR_READ_4(sc, BGE_RX_MODE);

sys/dev/bge/if_bge.c

5637

sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);

sys/dev/bge/if_bge.c

5640

sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);

sys/dev/bge/if_bge.c

5712

if (CSR_READ_4(sc, BGE_MAC_STS) &

sys/dev/bge/if_bge.c

5721

if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)

sys/dev/bge/if_bge.c

5908

if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {

sys/dev/bge/if_bge.c

5909

status = CSR_READ_4(sc, BGE_RX_STS);

sys/dev/bge/if_bge.c

5952

if ((CSR_READ_4(sc, reg) & bit) == 0)

sys/dev/bge/if_bge.c

6135

status = CSR_READ_4(sc, BGE_MAC_STS);

sys/dev/bge/if_bge.c

6165

status = CSR_READ_4(sc, BGE_MAC_STS);

sys/dev/bge/if_bge.c

6192

link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;

sys/dev/bge/if_bge.c

623

CSR_READ_4(sc, off);

sys/dev/bge/if_bge.c

6538

result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +

sys/dev/bge/if_bge.c

6582

printf(" %08x", CSR_READ_4(sc, i));

sys/dev/bge/if_bge.c

6632

val = CSR_READ_4(sc, result);

sys/dev/bge/if_bge.c

965

if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)

sys/dev/bge/if_bge.c

973

access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);

sys/dev/bge/if_bge.c

980

if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {

sys/dev/bge/if_bge.c

992

byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);

sys/dev/bge/if_bgereg.h

2207

val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \

sys/dev/bge/if_bgereg.h

2810

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))

sys/dev/bge/if_bgereg.h

2812

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))

sys/dev/bwi/bwimac.c

1054

intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);

sys/dev/bwi/bwimac.c

1067

CSR_READ_4(sc, BWI_MAC_INTR_STATUS); /* dummy read */

sys/dev/bwi/bwimac.c

1252

mac_status = CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/bwi/bwimac.c

1449

CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/bwi/bwimac.c

1450

CSR_READ_4(sc, BWI_MAC_INTR_STATUS);

sys/dev/bwi/bwimac.c

1468

CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/bwi/bwimac.c

1472

if (CSR_READ_4(sc, BWI_MAC_INTR_STATUS) & BWI_INTR_READY)

sys/dev/bwi/bwimac.c

1491

status = CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/bwi/bwimac.c

1498

CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/bwi/bwimac.c

1563

val = CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/bwi/bwimac.c

1575

val = CSR_READ_4(sc, BWI_STATE_HI);

sys/dev/bwi/bwimac.c

1586

if (CSR_READ_4(sc, txrx_reg) & BWI_TXRX32_CTRL_ADDRHI_MASK) {

sys/dev/bwi/bwimac.c

1932

CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/bwi/bwimac.c

198

return CSR_READ_4(sc, BWI_MOBJ_DATA);

sys/dev/bwi/bwimac.c

247

CSR_READ_4(mac->mac_sc, BWI_STATE_HI); /* dummy read */

sys/dev/bwi/bwimac.c

462

state_lo = CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/bwi/bwimac.c

468

CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/bwi/bwimac.c

474

CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/bwi/bwimac.c

479

status = CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/bwi/bwimac.c

569

val = CSR_READ_4(sc, BWI_MAC_STATUS);

sys/dev/bwi/bwimac.c

576

val = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);

sys/dev/bwi/bwimac.c

718

CSR_READ_4(sc, BWI_MAC_STATUS); /* dummy read */

sys/dev/bwi/bwiphy.c

247

CSR_READ_4(mac->mac_sc, BWI_MAC_STATUS);

sys/dev/bwi/if_bwi.c

1069

val = CSR_READ_4(sc, BWI_CLOCK_CTRL);

sys/dev/bwi/if_bwi.c

1082

val = CSR_READ_4(sc, BWI_CLOCK_INFO);

sys/dev/bwi/if_bwi.c

1130

clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);

sys/dev/bwi/if_bwi.c

1253

if ((CSR_READ_4(sc, BWI_TXSTATUS0) &

sys/dev/bwi/if_bwi.c

1256

CSR_READ_4(sc, BWI_TXSTATUS1);

sys/dev/bwi/if_bwi.c

1478

CSR_READ_4(sc, BWI_MAC_INTR_MASK);

sys/dev/bwi/if_bwi.c

1526

intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);

sys/dev/bwi/if_bwi.c

1534

intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);

sys/dev/bwi/if_bwi.c

1555

CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;

sys/dev/bwi/if_bwi.c

1619

if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)

sys/dev/bwi/if_bwi.c

2691

val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);

sys/dev/bwi/if_bwi.c

2722

status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);

sys/dev/bwi/if_bwi.c

2778

val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);

sys/dev/bwi/if_bwi.c

2795

val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);

sys/dev/bwi/if_bwi.c

3278

val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);

sys/dev/bwi/if_bwi.c

3395

tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);

sys/dev/bwi/if_bwi.c

3398

tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);

sys/dev/bwi/if_bwi.c

3448

val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);

sys/dev/bwi/if_bwi.c

3499

busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);

sys/dev/bwi/if_bwi.c

3517

val = CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/bwi/if_bwi.c

3538

state_lo = CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/bwi/if_bwi.c

3562

state_lo = CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/bwi/if_bwi.c

3575

state_hi = CSR_READ_4(sc, BWI_STATE_HI);

sys/dev/bwi/if_bwi.c

3595

CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/bwi/if_bwi.c

3604

CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/bwi/if_bwi.c

3623

CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/bwi/if_bwi.c

3626

state_hi = CSR_READ_4(sc, BWI_STATE_HI);

sys/dev/bwi/if_bwi.c

3630

imstate = CSR_READ_4(sc, BWI_IMSTATE);

sys/dev/bwi/if_bwi.c

3643

CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/bwi/if_bwi.c

3652

CSR_READ_4(sc, BWI_STATE_LO);

sys/dev/bwi/if_bwi.c

757

val = CSR_READ_4(sc, BWI_ID_HI);

sys/dev/bwi/if_bwi.c

791

info = CSR_READ_4(sc, BWI_INFO);

sys/dev/bwi/if_bwi.c

796

sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);

sys/dev/bwi/if_bwi.c

923

val = CSR_READ_4(sc, BWI_FLAGS);

sys/dev/bwi/if_bwi.c

980

CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */

sys/dev/bwi/if_bwi.c

982

CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */

sys/dev/bwi/if_bwivar.h

87

CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))

sys/dev/bwi/if_bwivar.h

92

CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))

sys/dev/bwi/if_bwivar.h

97

CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))

sys/dev/dc/dcphy.c

206

mode = CSR_READ_4(dc_sc, DC_NETCFG);

sys/dev/dc/dcphy.c

261

reg = CSR_READ_4(dc_sc, DC_10BTSTAT);

sys/dev/dc/dcphy.c

307

tstat = CSR_READ_4(dc_sc, DC_10BTSTAT);

sys/dev/dc/dcphy.c

311

if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) {

sys/dev/dc/dcphy.c

364

if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL)

sys/dev/dc/dcphy.c

368

if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)

sys/dev/dc/dcphy.c

75

CSR_READ_4(sc, reg) | x)

sys/dev/dc/dcphy.c

79

CSR_READ_4(sc, reg) & ~x)

sys/dev/dc/if_dc.c

1224

filter = CSR_READ_4(sc, DC_NETCFG);

sys/dev/dc/if_dc.c

1369

isr = CSR_READ_4(sc, DC_ISR);

sys/dev/dc/if_dc.c

1401

if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {

sys/dev/dc/if_dc.c

1413

watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);

sys/dev/dc/if_dc.c

1446

watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);

sys/dev/dc/if_dc.c

1521

if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))

sys/dev/dc/if_dc.c

2293

reg = CSR_READ_4(sc, DC_AL_PAR0);

sys/dev/dc/if_dc.c

2299

reg = CSR_READ_4(sc, DC_AL_PAR1);

sys/dev/dc/if_dc.c

2336

mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL);

sys/dev/dc/if_dc.c

3100

r = CSR_READ_4(sc, DC_10BTSTAT);

sys/dev/dc/if_dc.c

3118

if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc,

sys/dev/dc/if_dc.c

3165

netcfg = CSR_READ_4(sc, DC_NETCFG);

sys/dev/dc/if_dc.c

3187

isr = CSR_READ_4(sc, DC_ISR);

sys/dev/dc/if_dc.c

3240

status = CSR_READ_4(sc, DC_ISR);

sys/dev/dc/if_dc.c

3252

uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);

sys/dev/dc/if_dc.c

3290

status = CSR_READ_4(sc, DC_ISR);

sys/dev/dc/if_dc.c

3334

r = CSR_READ_4(sc, DC_FRAMESDISCARDED);

sys/dev/dc/if_dc.c

3351

status = CSR_READ_4(sc, DC_ISR);

sys/dev/dc/if_dc.c

357

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/dc/if_dc.c

360

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/dc/if_dc.c

371

CSR_READ_4(sc, DC_BUSCTL);

sys/dev/dc/if_dc.c

3760

CSR_READ_4(sc, DC_FRAMESDISCARDED);

sys/dev/dc/if_dc.c

3969

netcfg = CSR_READ_4(sc, DC_NETCFG);

sys/dev/dc/if_dc.c

407

if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {

sys/dev/dc/if_dc.c

519

r = CSR_READ_4(sc, DC_SIO);

sys/dev/dc/if_dc.c

540

*dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff;

sys/dev/dc/if_dc.c

543

*dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;

sys/dev/dc/if_dc.c

581

if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)

sys/dev/dc/if_dc.c

644

val = CSR_READ_4(sc, DC_SIO);

sys/dev/dc/if_dc.c

688

rval = CSR_READ_4(sc, DC_PN_MII);

sys/dev/dc/if_dc.c

704

rval = CSR_READ_4(sc, DC_ROM);

sys/dev/dc/if_dc.c

743

rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;

sys/dev/dc/if_dc.c

750

phy_reg = CSR_READ_4(sc, DC_NETCFG);

sys/dev/dc/if_dc.c

772

if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))

sys/dev/dc/if_dc.c

823

phy_reg = CSR_READ_4(sc, DC_NETCFG);

sys/dev/dc/pnphy.c

207

reg = CSR_READ_4(dc_sc, DC_ISR);

sys/dev/dc/pnphy.c

210

reg = CSR_READ_4(dc_sc, DC_NETCFG);

sys/dev/et/if_et.c

1178

status = CSR_READ_4(sc, ET_INTR_STATUS);

sys/dev/et/if_et.c

1473

if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) {

sys/dev/et/if_et.c

1581

pktfilt = CSR_READ_4(sc, ET_PKTFILT);

sys/dev/et/if_et.c

1582

rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL);

sys/dev/et/if_et.c

2005

if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) {

sys/dev/et/if_et.c

2260

tx_done = CSR_READ_4(sc, ET_TX_DONE_POS);

sys/dev/et/if_et.c

2615

stats->pkts_64 += CSR_READ_4(sc, ET_STAT_PKTS_64);

sys/dev/et/if_et.c

2616

stats->pkts_65 += CSR_READ_4(sc, ET_STAT_PKTS_65_127);

sys/dev/et/if_et.c

2617

stats->pkts_128 += CSR_READ_4(sc, ET_STAT_PKTS_128_255);

sys/dev/et/if_et.c

2618

stats->pkts_256 += CSR_READ_4(sc, ET_STAT_PKTS_256_511);

sys/dev/et/if_et.c

2619

stats->pkts_512 += CSR_READ_4(sc, ET_STAT_PKTS_512_1023);

sys/dev/et/if_et.c

2620

stats->pkts_1024 += CSR_READ_4(sc, ET_STAT_PKTS_1024_1518);

sys/dev/et/if_et.c

2621

stats->pkts_1519 += CSR_READ_4(sc, ET_STAT_PKTS_1519_1522);

sys/dev/et/if_et.c

2623

stats->rx_bytes += CSR_READ_4(sc, ET_STAT_RX_BYTES);

sys/dev/et/if_et.c

2624

stats->rx_frames += CSR_READ_4(sc, ET_STAT_RX_FRAMES);

sys/dev/et/if_et.c

2625

stats->rx_crcerrs += CSR_READ_4(sc, ET_STAT_RX_CRC_ERR);

sys/dev/et/if_et.c

2626

stats->rx_mcast += CSR_READ_4(sc, ET_STAT_RX_MCAST);

sys/dev/et/if_et.c

2627

stats->rx_bcast += CSR_READ_4(sc, ET_STAT_RX_BCAST);

sys/dev/et/if_et.c

2628

stats->rx_control += CSR_READ_4(sc, ET_STAT_RX_CTL);

sys/dev/et/if_et.c

2629

stats->rx_pause += CSR_READ_4(sc, ET_STAT_RX_PAUSE);

sys/dev/et/if_et.c

2630

stats->rx_unknown_control += CSR_READ_4(sc, ET_STAT_RX_UNKNOWN_CTL);

sys/dev/et/if_et.c

2631

stats->rx_alignerrs += CSR_READ_4(sc, ET_STAT_RX_ALIGN_ERR);

sys/dev/et/if_et.c

2632

stats->rx_lenerrs += CSR_READ_4(sc, ET_STAT_RX_LEN_ERR);

sys/dev/et/if_et.c

2633

stats->rx_codeerrs += CSR_READ_4(sc, ET_STAT_RX_CODE_ERR);

sys/dev/et/if_et.c

2634

stats->rx_cserrs += CSR_READ_4(sc, ET_STAT_RX_CS_ERR);

sys/dev/et/if_et.c

2635

stats->rx_runts += CSR_READ_4(sc, ET_STAT_RX_RUNT);

sys/dev/et/if_et.c

2636

stats->rx_oversize += CSR_READ_4(sc, ET_STAT_RX_OVERSIZE);

sys/dev/et/if_et.c

2637

stats->rx_fragments += CSR_READ_4(sc, ET_STAT_RX_FRAG);

sys/dev/et/if_et.c

2638

stats->rx_jabbers += CSR_READ_4(sc, ET_STAT_RX_JABBER);

sys/dev/et/if_et.c

2639

stats->rx_drop += CSR_READ_4(sc, ET_STAT_RX_DROP);

sys/dev/et/if_et.c

2641

stats->tx_bytes += CSR_READ_4(sc, ET_STAT_TX_BYTES);

sys/dev/et/if_et.c

2642

stats->tx_frames += CSR_READ_4(sc, ET_STAT_TX_FRAMES);

sys/dev/et/if_et.c

2643

stats->tx_mcast += CSR_READ_4(sc, ET_STAT_TX_MCAST);

sys/dev/et/if_et.c

2644

stats->tx_bcast += CSR_READ_4(sc, ET_STAT_TX_BCAST);

sys/dev/et/if_et.c

2645

stats->tx_pause += CSR_READ_4(sc, ET_STAT_TX_PAUSE);

sys/dev/et/if_et.c

2646

stats->tx_deferred += CSR_READ_4(sc, ET_STAT_TX_DEFER);

sys/dev/et/if_et.c

2647

stats->tx_excess_deferred += CSR_READ_4(sc, ET_STAT_TX_EXCESS_DEFER);

sys/dev/et/if_et.c

2648

stats->tx_single_colls += CSR_READ_4(sc, ET_STAT_TX_SINGLE_COL);

sys/dev/et/if_et.c

2649

stats->tx_multi_colls += CSR_READ_4(sc, ET_STAT_TX_MULTI_COL);

sys/dev/et/if_et.c

2650

stats->tx_late_colls += CSR_READ_4(sc, ET_STAT_TX_LATE_COL);

sys/dev/et/if_et.c

2651

stats->tx_excess_colls += CSR_READ_4(sc, ET_STAT_TX_EXCESS_COL);

sys/dev/et/if_et.c

2652

stats->tx_total_colls += CSR_READ_4(sc, ET_STAT_TX_TOTAL_COL);

sys/dev/et/if_et.c

2653

stats->tx_pause_honored += CSR_READ_4(sc, ET_STAT_TX_PAUSE_HONOR);

sys/dev/et/if_et.c

2654

stats->tx_drop += CSR_READ_4(sc, ET_STAT_TX_DROP);

sys/dev/et/if_et.c

2655

stats->tx_jabbers += CSR_READ_4(sc, ET_STAT_TX_JABBER);

sys/dev/et/if_et.c

2656

stats->tx_crcerrs += CSR_READ_4(sc, ET_STAT_TX_CRC_ERR);

sys/dev/et/if_et.c

2657

stats->tx_control += CSR_READ_4(sc, ET_STAT_TX_CTL);

sys/dev/et/if_et.c

2658

stats->tx_oversize += CSR_READ_4(sc, ET_STAT_TX_OVERSIZE);

sys/dev/et/if_et.c

2659

stats->tx_undersize += CSR_READ_4(sc, ET_STAT_TX_UNDERSIZE);

sys/dev/et/if_et.c

2660

stats->tx_fragments += CSR_READ_4(sc, ET_STAT_TX_FRAG);

sys/dev/et/if_et.c

2703

pmcfg = CSR_READ_4(sc, ET_PM);

sys/dev/et/if_et.c

429

val = CSR_READ_4(sc, ET_MII_IND);

sys/dev/et/if_et.c

443

val = CSR_READ_4(sc, ET_MII_STAT);

sys/dev/et/if_et.c

474

val = CSR_READ_4(sc, ET_MII_IND);

sys/dev/et/if_et.c

529

ctrl = CSR_READ_4(sc, ET_MAC_CTRL);

sys/dev/et/if_et.c

531

cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);

sys/dev/et/if_et.c

534

cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);

sys/dev/et/if_et.c

578

cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);

sys/dev/et/if_et.c

651

CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~(

sys/dev/fxp/if_fxp.c

2744

while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0

sys/dev/fxp/if_fxp.c

2764

while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&

sys/dev/ipw/if_ipw.c

1253

r = CSR_READ_4(sc, IPW_CSR_RX_READ);

sys/dev/ipw/if_ipw.c

1346

r = CSR_READ_4(sc, IPW_CSR_TX_READ);

sys/dev/ipw/if_ipw.c

1383

r = CSR_READ_4(sc, IPW_CSR_INTR);

sys/dev/ipw/if_ipw.c

1807

if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED)

sys/dev/ipw/if_ipw.c

1814

tmp = CSR_READ_4(sc, IPW_CSR_RST);

sys/dev/ipw/if_ipw.c

1830

tmp = CSR_READ_4(sc, IPW_CSR_CTL);

sys/dev/ipw/if_ipw.c

1835

if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY)

sys/dev/ipw/if_ipw.c

1842

tmp = CSR_READ_4(sc, IPW_CSR_RST);

sys/dev/ipw/if_ipw.c

1847

tmp = CSR_READ_4(sc, IPW_CSR_CTL);

sys/dev/ipw/if_ipw.c

1989

tmp = CSR_READ_4(sc, IPW_CSR_CTL);

sys/dev/ipw/if_ipw.c

1999

tmp = CSR_READ_4(sc, IPW_CSR_IO);

sys/dev/ipw/if_ipw.c

2380

sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE);

sys/dev/ipw/if_ipw.c

2381

sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE);

sys/dev/ipw/if_ipw.c

2538

size = min(CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA), 256);

sys/dev/ipw/if_ipw.c

2540

buf[i] = MEM_READ_4(sc, CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA));

sys/dev/ipw/if_ipw.c

2552

(CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED));

sys/dev/ipw/if_ipwreg.h

357

CSR_READ_4((sc), IPW_CSR_INDIRECT_DATA))

sys/dev/iwi/if_iwi.c

1572

hw = CSR_READ_4(sc, IWI_CSR_RX_RIDX);

sys/dev/iwi/if_iwi.c

1614

hw = CSR_READ_4(sc, txq->csr_ridx);

sys/dev/iwi/if_iwi.c

1666

if ((r = CSR_READ_4(sc, IWI_CSR_INTR)) == 0 || r == 0xffffffff) {

sys/dev/iwi/if_iwi.c

2088

if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED)

sys/dev/iwi/if_iwi.c

2095

tmp = CSR_READ_4(sc, IWI_CSR_RST);

sys/dev/iwi/if_iwi.c

2109

tmp = CSR_READ_4(sc, IWI_CSR_CTL);

sys/dev/iwi/if_iwi.c

2116

if (CSR_READ_4(sc, IWI_CSR_CTL) & IWI_CTL_CLOCK_READY)

sys/dev/iwi/if_iwi.c

2126

tmp = CSR_READ_4(sc, IWI_CSR_RST);

sys/dev/iwi/if_iwi.c

2131

tmp = CSR_READ_4(sc, IWI_CSR_CTL);

sys/dev/iwi/if_iwi.c

2348

CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) |

sys/dev/iwi/if_iwi.c

2351

if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED)

sys/dev/iwi/if_iwi.c

2364

tmp = CSR_READ_4(sc, IWI_CSR_RST);

sys/dev/iwi/if_iwi.c

2464

sentinel = CSR_READ_4(sc, IWI_CSR_AUTOINC_ADDR);

sys/dev/iwi/if_iwi.c

2467

tmp = CSR_READ_4(sc, IWI_CSR_RST);

sys/dev/iwi/if_iwi.c

2498

tmp = CSR_READ_4(sc, IWI_CSR_CTL);

sys/dev/iwi/if_iwi.c

258

return CSR_READ_4(sc, IWI_CSR_INDIRECT_DATA);

sys/dev/iwi/if_iwi.c

3248

return (CSR_READ_4(sc, IWI_CSR_IO) & IWI_IO_RADIO_ENABLED) == 0;

sys/dev/iwi/if_iwi.c

3310

size = min(CSR_READ_4(sc, IWI_CSR_TABLE0_SIZE), 128 - 1);

sys/dev/iwi/if_iwi.c

3457

txrate = CSR_READ_4(sc, IWI_CSR_CURRENT_TX_RATE);

sys/dev/iwi/if_iwi.c

933

iwi_cvtrate(CSR_READ_4(sc, IWI_CSR_CURRENT_TX_RATE)));

sys/dev/jme/if_jme.c

1570

CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &

sys/dev/jme/if_jme.c

1575

CSR_READ_4(sc, JME_GPREG1) | GPREG1_RX_MAC_CLK_DIS);

sys/dev/jme/if_jme.c

1582

gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;

sys/dev/jme/if_jme.c

1583

pmcs = CSR_READ_4(sc, JME_PMCS);

sys/dev/jme/if_jme.c

1598

CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &

sys/dev/jme/if_jme.c

2025

reg = CSR_READ_4(sc, JME_RXMAC);

sys/dev/jme/if_jme.c

2082

rxmac = CSR_READ_4(sc, JME_RXMAC);

sys/dev/jme/if_jme.c

2084

txmac = CSR_READ_4(sc, JME_TXMAC);

sys/dev/jme/if_jme.c

2086

txpause = CSR_READ_4(sc, JME_TXPFC);

sys/dev/jme/if_jme.c

2099

CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &

sys/dev/jme/if_jme.c

2105

CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |

sys/dev/jme/if_jme.c

2135

gpreg = CSR_READ_4(sc, JME_GPREG1);

sys/dev/jme/if_jme.c

228

if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)

sys/dev/jme/if_jme.c

2287

CSR_READ_4(sc, JME_GHC) & ~GHC_TX_MAC_CLK_DIS);

sys/dev/jme/if_jme.c

2290

CSR_READ_4(sc, JME_GPREG1) & ~GPREG1_RX_MAC_CLK_DIS);

sys/dev/jme/if_jme.c

2312

status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);

sys/dev/jme/if_jme.c

2334

status = CSR_READ_4(sc, JME_INTR_STATUS);

sys/dev/jme/if_jme.c

2372

if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) {

sys/dev/jme/if_jme.c

260

if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)

sys/dev/jme/if_jme.c

2681

CSR_READ_4(sc, JME_GHC);

sys/dev/jme/if_jme.c

2692

gpreg = CSR_READ_4(sc, JME_GPREG1);

sys/dev/jme/if_jme.c

2694

gpreg = CSR_READ_4(sc, JME_GPREG1);

sys/dev/jme/if_jme.c

2697

ghc = CSR_READ_4(sc, JME_GHC);

sys/dev/jme/if_jme.c

2703

CSR_READ_4(sc, JME_GPREG1);

sys/dev/jme/if_jme.c

2710

CSR_READ_4(sc, JME_GHC);

sys/dev/jme/if_jme.c

2848

reg = CSR_READ_4(sc, JME_PMCS);

sys/dev/jme/if_jme.c

2852

reg = CSR_READ_4(sc, JME_RXMAC);

sys/dev/jme/if_jme.c

2864

reg = CSR_READ_4(sc, JME_GPREG0);

sys/dev/jme/if_jme.c

2991

CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);

sys/dev/jme/if_jme.c

3039

reg = CSR_READ_4(sc, JME_TXCSR);

sys/dev/jme/if_jme.c

3046

if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)

sys/dev/jme/if_jme.c

3059

reg = CSR_READ_4(sc, JME_RXCSR);

sys/dev/jme/if_jme.c

3066

if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)

sys/dev/jme/if_jme.c

3194

reg = CSR_READ_4(sc, JME_RXMAC);

sys/dev/jme/if_jme.c

3228

rxcfg = CSR_READ_4(sc, JME_RXMAC);

sys/dev/jme/if_jme.c

3275

CSR_READ_4(sc, JME_STATCSR);

sys/dev/jme/if_jme.c

3305

stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD);

sys/dev/jme/if_jme.c

3306

stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD);

sys/dev/jme/if_jme.c

3307

reg = CSR_READ_4(sc, JME_STAT_CRCMII);

sys/dev/jme/if_jme.c

3312

reg = CSR_READ_4(sc, JME_STAT_RXERR);

sys/dev/jme/if_jme.c

3317

reg = CSR_READ_4(sc, JME_STAT_FAIL);

sys/dev/jme/if_jme.c

3339

reg = CSR_READ_4(sc, JME_PHYPOWDN);

sys/dev/jme/if_jme.c

3359

reg = CSR_READ_4(sc, JME_PHYPOWDN);

sys/dev/jme/if_jme.c

356

reg = CSR_READ_4(sc, JME_SMBCSR);

sys/dev/jme/if_jme.c

371

reg = CSR_READ_4(sc, JME_SMBINTF);

sys/dev/jme/if_jme.c

381

reg = CSR_READ_4(sc, JME_SMBINTF);

sys/dev/jme/if_jme.c

489

par0 = CSR_READ_4(sc, JME_PAR0);

sys/dev/jme/if_jme.c

490

par1 = CSR_READ_4(sc, JME_PAR1);

sys/dev/jme/if_jme.c

708

reg = CSR_READ_4(sc, JME_CHIPMODE);

sys/dev/jme/if_jme.c

751

reg = CSR_READ_4(sc, JME_SMBCSR);

sys/dev/jme/if_jme.c

767

sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &

sys/dev/lge/if_lge.c

1001

if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL));

sys/dev/lge/if_lge.c

1049

status = CSR_READ_4(sc, LGE_ISR);

sys/dev/lge/if_lge.c

196

CSR_READ_4(sc, reg) | (x))

sys/dev/lge/if_lge.c

200

CSR_READ_4(sc, reg) & ~(x))

sys/dev/lge/if_lge.c

203

CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)

sys/dev/lge/if_lge.c

206

CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)

sys/dev/lge/if_lge.c

221

if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))

sys/dev/lge/if_lge.c

229

val = CSR_READ_4(sc, LGE_EEDATA);

sys/dev/lge/if_lge.c

279

if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))

sys/dev/lge/if_lge.c

287

return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);

sys/dev/lge/if_lge.c

302

if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))

sys/dev/lge/if_lge.c

405

if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))

sys/dev/lge/if_lge.c

525

if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)

sys/dev/lge/if_lge.c

649

CSR_READ_4(sc, LGE_ISR);

sys/dev/lge/if_lge.c

999

if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL));

sys/dev/msk/if_msk.c

1298

val = CSR_READ_4(sc, B2_GP_IO);

sys/dev/msk/if_msk.c

1301

CSR_READ_4(sc, B2_GP_IO);

sys/dev/msk/if_msk.c

1495

CSR_READ_4(sc, B0_HWE_IMSK);

sys/dev/msk/if_msk.c

1497

CSR_READ_4(sc, B0_IMSK);

sys/dev/msk/if_msk.c

2054

CSR_READ_4(sc, B0_IMSK);

sys/dev/msk/if_msk.c

2056

CSR_READ_4(sc, B0_HWE_IMSK);

sys/dev/msk/if_msk.c

2999

CSR_READ_4(sc, B0_IMSK);

sys/dev/msk/if_msk.c

3001

CSR_READ_4(sc, B0_HWE_IMSK);

sys/dev/msk/if_msk.c

3452

status = CSR_READ_4(sc, B0_HWE_ISRC);

sys/dev/msk/if_msk.c

3516

CSR_READ_4(sc, B0_HWE_IMSK);

sys/dev/msk/if_msk.c

3664

status = CSR_READ_4(sc, B0_Y2_SP_ISRC2);

sys/dev/msk/if_msk.c

3693

CSR_READ_4(sc, B0_IMSK);

sys/dev/msk/if_msk.c

3699

CSR_READ_4(sc, B0_IMSK);

sys/dev/msk/if_msk.c

3911

reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));

sys/dev/msk/if_msk.c

4022

CSR_READ_4(sc, B0_HWE_IMSK);

sys/dev/msk/if_msk.c

4024

CSR_READ_4(sc, B0_IMSK);

sys/dev/msk/if_msk.c

4107

CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG));

sys/dev/msk/if_msk.c

4137

CSR_READ_4(sc, B0_HWE_IMSK);

sys/dev/msk/if_msk.c

4139

CSR_READ_4(sc, B0_IMSK);

sys/dev/msk/if_msk.c

4152

val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));

sys/dev/msk/if_msk.c

4157

val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));

sys/dev/msk/if_mskreg.h

2153

CSR_READ_4((sc_if)->msk_softc, (reg))

sys/dev/my/if_my.c

1194

if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {

sys/dev/my/if_my.c

1215

if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {

sys/dev/my/if_my.c

1216

if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (CSR_READ_4(sc, MY_TSR) & MY_NCRMask));

sys/dev/my/if_my.c

1265

status = CSR_READ_4(sc, MY_ISR);

sys/dev/my/if_my.c

140

#define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/my/if_my.c

141

#define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/my/if_my.c

175

miir = CSR_READ_4(sc, MY_MANAGEMENT);

sys/dev/my/if_my.c

239

miir = CSR_READ_4(sc, MY_MANAGEMENT);

sys/dev/my/if_my.c

327

rxfilt = CSR_READ_4(sc, MY_TCRRCR);

sys/dev/my/if_my.c

714

if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {

sys/dev/my/if_my.c

719

if (!(CSR_READ_4(sc, MY_TCRRCR) &

sys/dev/my/if_my.c

751

if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))

sys/dev/nge/if_nge.c

1697

CSR_READ_4(sc, NGE_MIB_RXERRPKT) & 0xFFFF;

sys/dev/nge/if_nge.c

1699

CSR_READ_4(sc, NGE_MIB_RXERRFCS) & 0xFFFF;

sys/dev/nge/if_nge.c

1701

CSR_READ_4(sc, NGE_MIB_RXERRMISSEDPKT) & 0xFFFF;

sys/dev/nge/if_nge.c

1703

CSR_READ_4(sc, NGE_MIB_RXERRALIGN) & 0xFFFF;

sys/dev/nge/if_nge.c

1705

CSR_READ_4(sc, NGE_MIB_RXERRSYM) & 0xFFFF;

sys/dev/nge/if_nge.c

1707

CSR_READ_4(sc, NGE_MIB_RXERRGIANT) & 0xFFFF;

sys/dev/nge/if_nge.c

1709

CSR_READ_4(sc, NGE_MIB_RXERRRANGLEN) & 0xFFFF;

sys/dev/nge/if_nge.c

1711

CSR_READ_4(sc, NGE_MIB_RXBADOPCODE) & 0xFFFF;

sys/dev/nge/if_nge.c

1713

CSR_READ_4(sc, NGE_MIB_RXPAUSEPKTS) & 0xFFFF;

sys/dev/nge/if_nge.c

1715

CSR_READ_4(sc, NGE_MIB_TXPAUSEPKTS) & 0xFFFF;

sys/dev/nge/if_nge.c

1717

CSR_READ_4(sc, NGE_MIB_TXERRSQE) & 0xFF;

sys/dev/nge/if_nge.c

1774

status = CSR_READ_4(sc, NGE_ISR);

sys/dev/nge/if_nge.c

1808

status = CSR_READ_4(sc, NGE_ISR);

sys/dev/nge/if_nge.c

1824

CSR_READ_4(sc, NGE_GPIO) | NGE_GPIO_GP3_OUT);

sys/dev/nge/if_nge.c

1844

status = CSR_READ_4(sc, NGE_ISR);

sys/dev/nge/if_nge.c

1856

CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT);

sys/dev/nge/if_nge.c

2183

reg = CSR_READ_4(sc, NGE_MIBCTL);

sys/dev/nge/if_nge.c

2425

reg = CSR_READ_4(sc, NGE_CSR);

sys/dev/nge/if_nge.c

2432

if ((CSR_READ_4(sc, NGE_CSR) &

sys/dev/nge/if_nge.c

246

CSR_READ_4(sc, reg) | (x))

sys/dev/nge/if_nge.c

250

CSR_READ_4(sc, reg) & ~(x))

sys/dev/nge/if_nge.c

253

CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))

sys/dev/nge/if_nge.c

2551

reg = CSR_READ_4(sc, NGE_CLKRUN);

sys/dev/nge/if_nge.c

256

CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))

sys/dev/nge/if_nge.c

264

CSR_READ_4(sc, NGE_CSR);

sys/dev/nge/if_nge.c

348

if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)

sys/dev/nge/if_nge.c

388

val = CSR_READ_4(sc, NGE_MEAR);

sys/dev/nge/if_nge.c

428

reg = CSR_READ_4(sc, NGE_TBI_BMSR);

sys/dev/nge/if_nge.c

454

return (CSR_READ_4(sc, reg));

sys/dev/nge/if_nge.c

588

reg = CSR_READ_4(sc, NGE_CFG);

sys/dev/nge/if_nge.c

603

reg = CSR_READ_4(sc, NGE_CSR);

sys/dev/nge/if_nge.c

610

status = CSR_READ_4(sc, NGE_ISR);

sys/dev/nge/if_nge.c

641

reg = CSR_READ_4(sc, NGE_CSR);

sys/dev/nge/if_nge.c

645

if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RX_ENABLE) != 0)

sys/dev/nge/if_nge.c

657

CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT);

sys/dev/nge/if_nge.c

692

rxfilt = CSR_READ_4(sc, NGE_RXFILT_CTL);

sys/dev/nge/if_nge.c

757

if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))

sys/dev/nge/if_nge.c

783

v = CSR_READ_4(sc, NGE_CFG);

sys/dev/nge/if_nge.c

922

if ((CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) != 0) {

sys/dev/nge/if_nge.c

926

CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)

sys/dev/re/if_re.c

1392

hwrev = CSR_READ_4(sc, RL_TXCFG);

sys/dev/re/if_re.c

3218

CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) &

sys/dev/re/if_re.c

3623

CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) &

sys/dev/re/if_re.c

3629

CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) |

sys/dev/re/if_re.c

3649

if ((CSR_READ_4(sc, RL_TXCFG) &

sys/dev/re/if_re.c

3884

CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) &

sys/dev/re/if_re.c

4027

if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) &

sys/dev/re/if_re.c

467

rval = CSR_READ_4(sc, RL_PHYAR);

sys/dev/re/if_re.c

499

rval = CSR_READ_4(sc, RL_PHYAR);

sys/dev/rl/if_rl.c

1242

txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));

sys/dev/rl/if_rl.c

535

rxfilt = CSR_READ_4(sc, RL_RXCFG);

sys/dev/rl/if_rl.c

807

hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;

sys/dev/rl/if_rlreg.h

977

CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))

sys/dev/rl/if_rlreg.h

980

CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))

sys/dev/sge/if_sge.c

1330

status = CSR_READ_4(sc, IntrStatus);

sys/dev/sge/if_sge.c

1361

status = CSR_READ_4(sc, IntrStatus);

sys/dev/sge/if_sge.c

1882

CSR_READ_4(sc, IntrMask);

sys/dev/sge/if_sge.c

219

val = CSR_READ_4(sc, ROMInterface);

sys/dev/sge/if_sge.c

340

val = CSR_READ_4(sc, GMIIControl);

sys/dev/sge/if_sge.c

365

val = CSR_READ_4(sc, GMIIControl);

sys/dev/sge/if_sge.c

415

ctl = CSR_READ_4(sc, StationControl);

sys/dev/sge/if_sge.c

512

CSR_READ_4(sc, IntrControl);

sys/dev/sis/if_sis.c

1032

if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {

sys/dev/sis/if_sis.c

1665

status = CSR_READ_4(sc, SIS_ISR);

sys/dev/sis/if_sis.c

1703

status = CSR_READ_4(sc, SIS_ISR);

sys/dev/sis/if_sis.c

1737

status = CSR_READ_4(sc, SIS_ISR);

sys/dev/sis/if_sis.c

196

CSR_READ_4(sc, reg) | (x))

sys/dev/sis/if_sis.c

200

CSR_READ_4(sc, reg) & ~(x))

sys/dev/sis/if_sis.c

203

CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)

sys/dev/sis/if_sis.c

2030

if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {

sys/dev/sis/if_sis.c

206

CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)

sys/dev/sis/if_sis.c

2231

CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */

sys/dev/sis/if_sis.c

229

CSR_READ_4(sc, SIS_CSR);

sys/dev/sis/if_sis.c

2324

CSR_READ_4(sc, NS_WCSR);

sys/dev/sis/if_sis.c

2334

val = CSR_READ_4(sc, NS_CLKRUN);

sys/dev/sis/if_sis.c

313

if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)

sys/dev/sis/if_sis.c

415

filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);

sys/dev/sis/if_sis.c

416

csrsave = CSR_READ_4(sc, SIS_CSR);

sys/dev/sis/if_sis.c

446

val = CSR_READ_4(sc, SIS_EECTL);

sys/dev/sis/if_sis.c

487

if (!CSR_READ_4(sc, NS_BMSR))

sys/dev/sis/if_sis.c

489

return CSR_READ_4(sc, NS_BMCR + (reg * 4));

sys/dev/sis/if_sis.c

509

if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))

sys/dev/sis/if_sis.c

519

val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;

sys/dev/sis/if_sis.c

561

if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))

sys/dev/sis/if_sis.c

643

reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;

sys/dev/sis/if_sis.c

646

reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;

sys/dev/sis/if_sis.c

720

filter = CSR_READ_4(sc, SIS_RXFILT_CTL);

sys/dev/sis/if_sis.c

726

CSR_READ_4(sc, SIS_RXFILT_CTL);

sys/dev/sis/if_sis.c

765

CSR_READ_4(sc, SIS_RXFILT_CTL);

sys/dev/sis/if_sis.c

800

filter = CSR_READ_4(sc, SIS_RXFILT_CTL);

sys/dev/sis/if_sis.c

803

CSR_READ_4(sc, SIS_RXFILT_CTL);

sys/dev/sis/if_sis.c

834

CSR_READ_4(sc, SIS_RXFILT_CTL);

sys/dev/sis/if_sis.c

845

if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))

sys/dev/sis/if_sis.c

945

sc->sis_srr = CSR_READ_4(sc, NS_SRR);

sys/dev/sk/if_sk.c

2980

status = CSR_READ_4(sc, SK_ISSR);

sys/dev/sk/if_sk.c

3046

status = CSR_READ_4(sc, SK_ISSR);

sys/dev/sk/if_sk.c

345

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)

sys/dev/sk/if_sk.c

348

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)

sys/dev/sk/if_sk.c

3513

CSR_READ_4(sc, SK_ISSR);

sys/dev/sk/if_sk.c

3588

val = CSR_READ_4(sc, sc_if->sk_tx_bmu);

sys/dev/sk/if_sk.c

367

return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));

sys/dev/sk/if_sk.c

369

return(CSR_READ_4(sc, reg));

sys/dev/ste/if_ste.c

1628

val = CSR_READ_4(sc, STE_DMACTL);

sys/dev/ste/if_ste.c

1686

ctl = CSR_READ_4(sc, STE_ASICCTL);

sys/dev/ste/if_ste.c

1693

CSR_READ_4(sc, STE_ASICCTL);

sys/dev/ste/if_ste.c

1701

if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))

sys/dev/ste/if_ste.c

183

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/ste/if_ste.c

186

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/ste/if_ste.c

345

if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))

sys/dev/stge/if_stge.c

1046

if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)

sys/dev/stge/if_stge.c

1379

v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;

sys/dev/stge/if_stge.c

1385

ac = CSR_READ_4(sc, STGE_AsicCtrl);

sys/dev/stge/if_stge.c

1390

if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)

sys/dev/stge/if_stge.c

1406

txstat = CSR_READ_4(sc, STGE_TxStatus);

sys/dev/stge/if_stge.c

1428

(CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |

sys/dev/stge/if_stge.c

1863

CSR_READ_4(sc,STGE_OctetRcvOk);

sys/dev/stge/if_stge.c

1865

if_inc_counter(ifp, IFCOUNTER_IPACKETS, CSR_READ_4(sc, STGE_FramesRcvdOk));

sys/dev/stge/if_stge.c

1869

CSR_READ_4(sc, STGE_OctetXmtdOk);

sys/dev/stge/if_stge.c

1871

if_inc_counter(ifp, IFCOUNTER_OPACKETS, CSR_READ_4(sc, STGE_FramesXmtdOk));

sys/dev/stge/if_stge.c

1874

CSR_READ_4(sc, STGE_LateCollisions) +

sys/dev/stge/if_stge.c

1875

CSR_READ_4(sc, STGE_MultiColFrames) +

sys/dev/stge/if_stge.c

1876

CSR_READ_4(sc, STGE_SingleColFrames));

sys/dev/stge/if_stge.c

1898

ac = CSR_READ_4(sc, STGE_AsicCtrl);

sys/dev/stge/if_stge.c

1927

if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)

sys/dev/stge/if_stge.c

1936

ac = CSR_READ_4(sc, STGE_AsicCtrl);