sys/dev/fxp/if_fxp.c

1092

CSR_READ_1(sc, FXP_CSR_PMDR));

sys/dev/fxp/if_fxp.c

1667

tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);

sys/dev/fxp/if_fxp.c

1706

while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {

sys/dev/fxp/if_fxp.c

2134

if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {

sys/dev/fxp/if_fxp.c

3012

while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=

sys/dev/fxp/if_fxp.c

334

while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)

sys/dev/fxp/if_fxp.c

337

flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);

sys/dev/fxp/if_fxp.c

338

flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);

sys/dev/fxp/if_fxp.c

340

CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),

sys/dev/fxp/if_fxp.c

341

CSR_READ_1(sc, FXP_CSR_SCB_STATACK),

sys/dev/fxp/if_fxp.c

342

CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);

sys/dev/fxp/if_fxp.c

909

CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));

sys/dev/ipw/if_ipw.c

2602

*datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3));

sys/dev/ipw/if_ipwreg.h

353

CSR_READ_1((sc), IPW_CSR_INDIRECT_DATA))

sys/dev/iwi/if_iwi.c

251

return CSR_READ_1(sc, IWI_CSR_INDIRECT_DATA);

sys/dev/lge/if_lge.c

1161

if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)

sys/dev/lge/if_lge.c

642

if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)

sys/dev/lge/if_lge.c

962

txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);

sys/dev/msk/if_msk.c

1206

sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4;

sys/dev/msk/if_msk.c

1660

eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i);

sys/dev/msk/if_msk.c

1774

sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);

sys/dev/msk/if_msk.c

1775

sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;

sys/dev/msk/if_msk.c

1813

sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);

sys/dev/msk/if_msk.c

1816

if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==

sys/dev/msk/if_msk.c

1818

if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))

sys/dev/msk/if_msk.c

3384

status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));

sys/dev/msk/if_msk.c

3812

CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));

sys/dev/msk/if_msk.c

4067

CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL));

sys/dev/msk/if_msk.c

4082

CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL));

sys/dev/msk/if_msk.c

4205

if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) ==

sys/dev/msk/if_msk.c

4206

CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL)))

sys/dev/msk/if_mskreg.h

2157

CSR_READ_1((sc_if)->msk_softc, (reg))

sys/dev/my/if_my.c

853

eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);

sys/dev/re/if_re.c

1326

cfg = CSR_READ_1(sc, RL_CFG2);

sys/dev/re/if_re.c

1363

cfg = CSR_READ_1(sc, RL_CFG2);

sys/dev/re/if_re.c

1561

cfg = CSR_READ_1(sc, sc->rl_cfg1);

sys/dev/re/if_re.c

1564

cfg = CSR_READ_1(sc, sc->rl_cfg5);

sys/dev/re/if_re.c

1575

eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);

sys/dev/re/if_re.c

1614

if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)

sys/dev/re/if_re.c

1616

CSR_READ_1(sc, RL_GPIO) | 0x01);

sys/dev/re/if_re.c

1619

CSR_READ_1(sc, RL_GPIO) & ~0x01);

sys/dev/re/if_re.c

1624

CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);

sys/dev/re/if_re.c

1626

CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);

sys/dev/re/if_re.c

3037

CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |

sys/dev/re/if_re.c

3044

CSR_READ_1(sc, sc->rl_cfg4) | 0x01);

sys/dev/re/if_re.c

3048

CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1);

sys/dev/re/if_re.c

3051

CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &

sys/dev/re/if_re.c

3058

CSR_READ_1(sc, sc->rl_cfg4) & ~0x01);

sys/dev/re/if_re.c

3062

CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1);

sys/dev/re/if_re.c

3172

if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0)

sys/dev/re/if_re.c

3347

CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |

sys/dev/re/if_re.c

361

CSR_READ_1(sc, RL_EECMD) | x)

sys/dev/re/if_re.c

3635

if ((CSR_READ_1(sc, sc->rl_txstart) &

sys/dev/re/if_re.c

365

CSR_READ_1(sc, RL_EECMD) & ~x)

sys/dev/re/if_re.c

3749

if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)

sys/dev/re/if_re.c

3751

CSR_READ_1(sc, RL_GPIO) | 0x01);

sys/dev/re/if_re.c

3877

if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)

sys/dev/re/if_re.c

3879

CSR_READ_1(sc, RL_GPIO) & ~0x01);

sys/dev/re/if_re.c

3897

v = CSR_READ_1(sc, sc->rl_cfg1);

sys/dev/re/if_re.c

3903

v = CSR_READ_1(sc, sc->rl_cfg3);

sys/dev/re/if_re.c

3909

v = CSR_READ_1(sc, sc->rl_cfg5);

sys/dev/re/if_re.c

3925

CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);

sys/dev/re/if_re.c

3950

v = CSR_READ_1(sc, sc->rl_cfg3);

sys/dev/re/if_re.c

3957

v = CSR_READ_1(sc, sc->rl_cfg5);

sys/dev/re/if_re.c

415

if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)

sys/dev/re/if_re.c

460

rval = CSR_READ_1(sc, RL_GMEDIASTAT);

sys/dev/re/if_re.c

558

rval = CSR_READ_1(sc, RL_MEDIASTAT);

sys/dev/re/if_re.c

743

if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))

sys/dev/rl/if_rl.c

1133

while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {

sys/dev/rl/if_rl.c

1918

if ((CSR_READ_1(sc, RL_COMMAND) &

sys/dev/rl/if_rl.c

2040

v = CSR_READ_1(sc, sc->rl_cfg1);

sys/dev/rl/if_rl.c

2046

v = CSR_READ_1(sc, sc->rl_cfg3);

sys/dev/rl/if_rl.c

2052

v = CSR_READ_1(sc, sc->rl_cfg5);

sys/dev/rl/if_rl.c

2084

v = CSR_READ_1(sc, sc->rl_cfg3);

sys/dev/rl/if_rl.c

2091

v = CSR_READ_1(sc, sc->rl_cfg5);

sys/dev/rl/if_rl.c

265

CSR_READ_1(sc, RL_EECMD) | x)

sys/dev/rl/if_rl.c

269

CSR_READ_1(sc, RL_EECMD) & ~x)

sys/dev/rl/if_rl.c

323

if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)

sys/dev/rl/if_rl.c

365

val = CSR_READ_1(sc, RL_MII);

sys/dev/rl/if_rl.c

422

return (CSR_READ_1(sc, RL_MEDIASTAT));

sys/dev/rl/if_rl.c

572

if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))

sys/dev/rl/if_rl.c

776

eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);

sys/dev/rl/if_rlreg.h

965

CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))

sys/dev/rl/if_rlreg.h

968

CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))

sys/dev/sk/if_sk.c

389

return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));

sys/dev/sk/if_sk.c

391

return(CSR_READ_1(sc, reg));

sys/dev/ste/if_ste.c

1535

val = CSR_READ_1(sc, STE_WAKE_EVENT);

sys/dev/ste/if_ste.c

195

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))

sys/dev/ste/if_ste.c

198

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))

sys/dev/ste/if_ste.c

2092

CSR_READ_1(sc, STE_WAKE_EVENT);

sys/dev/ste/if_ste.c

2098

val = CSR_READ_1(sc, STE_WAKE_EVENT);

sys/dev/ste/if_ste.c

211

val = CSR_READ_1(sc, STE_PHYCTL);

sys/dev/ste/if_ste.c

429

rxcfg = CSR_READ_1(sc, STE_RX_MODE);

sys/dev/ste/if_ste.c

453

CSR_READ_1(sc, STE_RX_MODE);

sys/dev/ste/if_ste.c

814

CSR_READ_1(sc, STE_STAT_RX_BCAST);

sys/dev/ste/if_ste.c

815

CSR_READ_1(sc, STE_STAT_RX_MCAST);

sys/dev/ste/if_ste.c

816

CSR_READ_1(sc, STE_STAT_RX_LOST);

sys/dev/ste/if_ste.c

821

CSR_READ_1(sc, STE_STAT_TX_BCAST);

sys/dev/ste/if_ste.c

822

CSR_READ_1(sc, STE_STAT_TX_MCAST);

sys/dev/ste/if_ste.c

823

CSR_READ_1(sc, STE_STAT_CARRIER_ERR);

sys/dev/ste/if_ste.c

824

CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);

sys/dev/ste/if_ste.c

825

CSR_READ_1(sc, STE_STAT_MULTI_COLLS);

sys/dev/ste/if_ste.c

826

CSR_READ_1(sc, STE_STAT_LATE_COLLS);

sys/dev/ste/if_ste.c

827

CSR_READ_1(sc, STE_STAT_TX_DEFER);

sys/dev/ste/if_ste.c

828

CSR_READ_1(sc, STE_STAT_TX_EXDEFER);

sys/dev/ste/if_ste.c

829

CSR_READ_1(sc, STE_STAT_TX_ABORT);

sys/dev/ste/if_ste.c

849

stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST);

sys/dev/ste/if_ste.c

850

stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST);

sys/dev/ste/if_ste.c

851

stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST);

sys/dev/ste/if_ste.c

858

stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST);

sys/dev/ste/if_ste.c

859

stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST);

sys/dev/ste/if_ste.c

860

stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR);

sys/dev/ste/if_ste.c

861

val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);

sys/dev/ste/if_ste.c

864

val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS);

sys/dev/ste/if_ste.c

867

val += CSR_READ_1(sc, STE_STAT_LATE_COLLS);

sys/dev/ste/if_ste.c

870

stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER);

sys/dev/ste/if_ste.c

871

stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER);

sys/dev/ste/if_ste.c

872

stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT);

sys/dev/stge/if_stge.c

1025

v = CSR_READ_1(sc, STGE_WakeEvent);

sys/dev/stge/if_stge.c

1947

v = CSR_READ_1(sc, STGE_PhySet);

sys/dev/stge/if_stge.c

255

val = CSR_READ_1(sc, STGE_PhyCtrl);

sys/dev/stge/if_stge.c

294

error = CSR_READ_1(sc, STGE_PhyCtrl);

sys/dev/stge/if_stge.c

585

sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &

sys/dev/stge/if_stge.c

979

v = CSR_READ_1(sc, STGE_WakeEvent);

sys/dev/vge/if_vge.c

1059

if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0)

sys/dev/vge/if_vge.c

1084

sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) &

sys/dev/vge/if_vge.c

1659

physts = CSR_READ_1(sc, VGE_PHYSTS0);

sys/dev/vge/if_vge.c

258

if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)

sys/dev/vge/if_vge.c

2598

CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FREEZE);

sys/dev/vge/if_vge.c

2600

CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_CLR);

sys/dev/vge/if_vge.c

2603

if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_CLR) == 0)

sys/dev/vge/if_vge.c

2608

CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) &

sys/dev/vge/if_vge.c

2626

CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FLUSH);

sys/dev/vge/if_vge.c

2629

if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_FLUSH) == 0)

sys/dev/vge/if_vge.c

2642

CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_RINI);

sys/dev/vge/if_vge.c

2737

intctl = CSR_READ_1(sc, VGE_INTCTL1);

sys/dev/vge/if_vge.c

2869

val = CSR_READ_1(sc, VGE_PWRSTAT);

sys/dev/vge/if_vge.c

2873

val = CSR_READ_1(sc, VGE_PWRSTAT);

sys/dev/vge/if_vge.c

2886

val = CSR_READ_1(sc, VGE_PWRSTAT);

sys/dev/vge/if_vge.c

2890

val = CSR_READ_1(sc, VGE_PWRSTAT);

sys/dev/vge/if_vge.c

299

dest[i] = CSR_READ_1(sc, VGE_PAR0 + i);

sys/dev/vge/if_vge.c

312

if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)

sys/dev/vge/if_vge.c

332

if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)

sys/dev/vge/if_vge.c

349

if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)

sys/dev/vge/if_vge.c

377

if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)

sys/dev/vge/if_vge.c

413

if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)

sys/dev/vge/if_vge.c

482

if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)

sys/dev/vge/if_vge.c

520

cfg = CSR_READ_1(sc, VGE_RXCFG);

sys/dev/vge/if_vge.c

573

rxcfg = CSR_READ_1(sc, VGE_RXCTL);

sys/dev/vge/if_vge.c

623

if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0)

sys/dev/vge/if_vgevar.h

231

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))

sys/dev/vge/if_vgevar.h

238

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))

sys/dev/vr/if_vr.c

2345

cmd = CSR_READ_1(sc, VR_CR0);

sys/dev/vr/if_vr.c

2364

cmd = CSR_READ_1(sc, VR_CR0);

sys/dev/vr/if_vr.c

2380

cmd = CSR_READ_1(sc, VR_CR0);

sys/dev/vr/if_vr.c

2386

cmd = CSR_READ_1(sc, VR_CR0);

sys/dev/vr/if_vr.c

2402

cmd = CSR_READ_1(sc, VR_CR0);

sys/dev/vr/if_vr.c

2408

cmd = CSR_READ_1(sc, VR_CR0);

sys/dev/vr/if_vr.c

253

if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)

sys/dev/vr/if_vr.c

2561

v = CSR_READ_1(sc, VR_STICKHW);

sys/dev/vr/if_vr.c

2567

v = CSR_READ_1(sc, VR_STICKHW);

sys/dev/vr/if_vr.c

2587

v = CSR_READ_1(sc, VR_STICKHW);

sys/dev/vr/if_vr.c

277

if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)

sys/dev/vr/if_vr.c

322

cr0 = CSR_READ_1(sc, VR_CR0);

sys/dev/vr/if_vr.c

323

cr1 = CSR_READ_1(sc, VR_CR1);

sys/dev/vr/if_vr.c

347

fc = CSR_READ_1(sc, VR_FLOWCR1);

sys/dev/vr/if_vr.c

360

fc = CSR_READ_1(sc, VR_MISC_CR0);

sys/dev/vr/if_vr.c

418

if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0)

sys/dev/vr/if_vr.c

482

rxfilt = CSR_READ_1(sc, VR_RXCFG);

sys/dev/vr/if_vr.c

544

if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET))

sys/dev/vr/if_vr.c

722

if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0)

sys/dev/vr/if_vr.c

728

eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);

sys/dev/vr/if_vr.c

775

phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK;

sys/dev/vr/if_vrreg.h

756

#define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))

sys/dev/vr/if_vrreg.h

757

#define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))

sys/dev/xl/if_xl.c

2075

while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {

sys/dev/xl/if_xl.c

2298

*p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);

sys/dev/xl/if_xl.c

2314

CSR_READ_1(sc, XL_W4_BADSSD);

sys/dev/xl/if_xl.c

2813

macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);

sys/dev/xl/if_xl.c

2939

if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)

sys/dev/xl/if_xl.c

2948

if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)

sys/dev/xl/if_xl.c

453

macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);

sys/dev/xl/if_xl.c

625

rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);

sys/dev/xl/if_xl.c

685

rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);

sys/dev/xl/if_xl.c

814

(CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));