intel_ntb_reg_read
reg = intel_ntb_reg_read(8, XEON_GEN3_REG_IMINT_STATUS);
reg = intel_ntb_reg_read(8, XEON_GEN4_REG_IMINT_STATUS);
return (intel_ntb_reg_read(8, regoff));
return (intel_ntb_reg_read(2, regoff));
return (intel_ntb_reg_read(8, XEON_GEN3_REG_IMINT_STATUS));
intel_ntb_reg_read(8, XEON_GEN3_REG_IMINT_STATUS));
intel_ntb_reg_read(8, XEON_GEN4_REG_IMINT_STATUS));
ppd1 = intel_ntb_reg_read(4, XEON_GEN4_REG_PPD1);
lnkctl = intel_ntb_reg_read(2, XEON_GEN4_REG_LINK_CTRL);
reg_val = intel_ntb_reg_read(4, base_reg);
reg_val = intel_ntb_reg_read(4, lmt_reg);
reg_val = intel_ntb_reg_read(8, base_reg);
reg_val = intel_ntb_reg_read(8, lmt_reg);
base_addr = intel_ntb_reg_read(4, bar->pbarxlat_off);
base_addr = intel_ntb_reg_read(8, bar->pbarxlat_off);
ntb->msix_xlat = intel_ntb_reg_read(8, xlat_reg);
ntb->msix_xlat = intel_ntb_reg_read(4, xlat_reg);
(void)intel_ntb_reg_read(8, XEON_SBAR2XLAT_OFFSET);
(void)intel_ntb_reg_read(8, XEON_SBAR4XLAT_OFFSET);
reg = intel_ntb_reg_read(8, XEON_GEN3_REG_EMBAR1XBASE);
reg = intel_ntb_reg_read(8, XEON_GEN3_REG_EMBAR2XBASE);
status = intel_ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET);
status = intel_ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET);
status = intel_ntb_reg_read(4, ATOM_ERRCORSTS_OFFSET);
status = intel_ntb_reg_read(4, ATOM_LTSSMERRSTS0_OFFSET);
status = intel_ntb_reg_read(4, ATOM_DESKEWSTS_OFFSET);
status = intel_ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET);
status = intel_ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET);
lnkctl = intel_ntb_reg_read(2, XEON_GEN4_REG_LINK_CTRL);
ppd0 = intel_ntb_reg_read(4, XEON_GEN4_REG_PPD0);
ppd0 = intel_ntb_reg_read(4, XEON_GEN4_REG_PPD0);
cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl);
cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl);
lnkctl = intel_ntb_reg_read(2, XEON_GEN4_REG_LINK_CTRL);
cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl);
cntl = intel_ntb_reg_read(2, XEON_GEN4_REG_LINK_CTRL);
cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl);
status32 = intel_ntb_reg_read(4, ntb->reg->ntb_ctl);
status32 = intel_ntb_reg_read(4, ntb->reg->lnk_sta);
ntb_cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl);
ntb->lnk_sta = intel_ntb_reg_read(4, ntb->reg->lnk_sta);
reg_val = intel_ntb_reg_read(2, ntb->reg->lnk_sta);
umv = intel_ntb_reg_read(8, reg);
umv = intel_ntb_reg_read(4, reg);
umv = intel_ntb_reg_read(2, reg);
umv = intel_ntb_reg_read(1, reg);
*val = intel_ntb_reg_read(4, ntb->self_reg->spad + idx * 4);
*val = intel_ntb_reg_read(4, ntb->peer_reg->spad + idx * 4);
base = intel_ntb_reg_read(8, base_reg) & BAR_HIGH_MASK;
reg_val = intel_ntb_reg_read(8, xlat_reg) & BAR_HIGH_MASK;
reg_val = intel_ntb_reg_read(8, limit_reg) & BAR_HIGH_MASK;
base = intel_ntb_reg_read(4, base_reg) & BAR_HIGH_MASK;
reg_val = intel_ntb_reg_read(4, xlat_reg) & BAR_HIGH_MASK;
reg_val = intel_ntb_reg_read(4, limit_reg) & BAR_HIGH_MASK;