is_t4
u32 a_port_cfg = is_t4(adapter) ?
u32 hss_cfg0 = is_t4(adapter) ?
if (!user && is_t4(adapter))
if (is_t4(adapter))
if (is_t4(adapter))
if (is_t4(adap))
if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) ||
if (is_t4(adap)) {
if (is_t4(adap)) {
t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff);
if (is_t4(adap)) {
if (is_t4(adap)) {
if (is_t4(adap) || is_t6(adap))
if (is_t4(adap)) {
if (is_t4(adap)) {
if (is_t4(adap)) {
if (is_t4(adap))
if (is_t4(adap)) {
u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN;
if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 ||
V_TFLENGTH(tp->skip_len) | en | (is_t4(adap) ?
if (is_t4(adap)) {
if (is_t4(adap))
if (is_t4(adap)) {
if (is_t4(adap)) {
if (is_t4(adap))
(is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
if (is_t4(adapter))
if (is_t4(adapter))
if (!is_t4(adapter)) {
if (is_t4(padap))
if (is_t4(padap))
if (!is_t4(padap)) {
if (!is_t4(padap)) {
if (is_t4(sc)) {
if (is_t4(sc) && t->fs.action == FILTER_SWITCH &&
else if (is_t4(sc)) {
if (is_t4(sc))
if (is_t4(sc)) {
if (is_t4(sc) && sc->rdmacaps == 0)
if (is_t4(sc)) {
if (is_t4(sc)) {
if (is_t4(sc)) {
((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
(is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
if (is_t4(sc)) {
MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
if (is_t4(sc))
if (is_t4(sc))
if (is_t4(sc))
if (is_t4(sc))
if (is_t4(sc))
wr = alloc_wrqe(is_t4(sc) ? sizeof(struct cpl_pass_accept_rpl) :
if (is_t4(sc))
if (is_t4(sc)) {