ioread32be
#define ioread32be(addr) ioread32be(addr)
return ioread32be(&dev->iseg->fw_rev) & 0xffff;
return ioread32be(&dev->iseg->fw_rev) >> 16;
return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
return (ioread32be(&dev->iseg->cmdq_addr_l_sz) >> 8) & 7;
cur_cmdq_addr_l_sz = ioread32be(&dev->iseg->cmdq_addr_l_sz);
u32 rfr = ioread32be(&h->rfr) >> MLX5_RFR_OFFSET;
bool err = ioread32be(&h->fw_ver) == 0xffffffff;
supported = (ioread32be(&dev->iseg->initializing) >>
cmdq_addr = ioread32be(&dev->iseg->cmdq_addr_l_sz);
ioread32be(h->assert_var + i));
ioread32be(&h->assert_exit_ptr));
ioread32be(&h->assert_callra));
mlx5_core_info(dev, "hw_id 0x%08x\n", ioread32be(&h->hw_id));
fw = ioread32be(&h->fw_ver);
count = ioread32be(health->health_counter);
count = ioread32be(health->health_counter);
return ioread32be(&dev->iseg->initializing) >> 31;
ioread32be(&dev->iseg->initializing));
hw_h = ioread32be(&iseg->internal_timer_h);
hw_l = ioread32be(&iseg->internal_timer_l);
hw_h1 = ioread32be(&iseg->internal_timer_h);