inb
inb(0x3DA);
inb(0x84);
inb(0x84);
inb(0x84);
inb(0x3DA);
inb(0x3DA);
VGLSavePaletteRed[i] = inb(0x3C9);
inb(0x84);
VGLSavePaletteGreen[i] = inb(0x3C9);
inb(0x84);
VGLSavePaletteBlue[i] = inb(0x3C9);
inb(0x84);
inb(0x3DA);
inb(0x3DA);
inb(0x84);
inb(0x84);
inb(0x84);
inb(0x3DA);
inb(0x3DA);
inb(0x3DA);
inb(0x3DA);
inb(0x3DA);
outb(0x3C4, 0x01); val = inb(0x3C5); outb(0x3C4, 0x01);
bit = (inb(isapnp_readport) == 0xaa) && bit;
if ((inb(isapnp_readport)) & 0x1)
temp = inb(isapnp_readport);
bit = inb(isapnp_readport) == 0x55;
c=inb(port);
if (inb(comc_port + com_lsr) & LSR_TXRDY) {
return (comc_ischar() ? inb(comc_port + com_data) : -1);
return (inb(comc_port + com_lsr) & LSR_RXRDY);
if (inb(comc_port + com_scr) != COMC_TEST) {
inb(comc_port + com_data);
while (inb(comc_port + com_lsr) & LSR_RXRDY && ++tries < TRY_COUNT);
cfcr = inb(comc_port + com_cfcr);
dlbl = inb(comc_port + com_dlbl);
dlbh = inb(comc_port + com_dlbh);
inb(IO_DUMMY);
inb(IO_DUMMY);
inb(IO_DUMMY);
inb(IO_DUMMY);
inb(IO_DUMMY);
inb(IO_DUMMY);
(void)inb(0x84);
while (inb(IO_KBD + KBD_STATUS_PORT) & KBDS_ANY_BUFFER_FULL) {
inb(IO_KBD + KBD_DATA_PORT);
if (((i = inb(IO_KBD + KBD_STATUS_PORT))
inb(IO_KBD + KBD_DATA_PORT);
if (inb(IO_KBD + KBD_STATUS_PORT) & KBDS_ANY_BUFFER_FULL)
i = inb(IO_KBD + KBD_DATA_PORT);
return (inb(reg + index));
(void) inb(reg + VGA_GEN_INPUT_STAT_1);
ret = inb(reg + VGA_AC_READ);
(void) inb(reg + VGA_GEN_INPUT_STAT_1);
(void) inb(reg + VGA_GEN_INPUT_STAT_1);
(void) inb(reg + VGA_GEN_INPUT_STAT_1);
return (inb(reg + datareg));
inb(IO_DUMMY); inb(IO_DUMMY);
inb(IO_DUMMY); inb(IO_DUMMY);
inb(IO_DUMMY); inb(IO_DUMMY);
(void) inb(0x84);
while (inb(IO_KBD + KBD_STATUS_PORT) & KBDS_ANY_BUFFER_FULL) {
inb(IO_KBD + KBD_DATA_PORT);
if (((i = inb(IO_KBD + KBD_STATUS_PORT))
inb(IO_KBD + KBD_DATA_PORT);
if (inb(IO_KBD + KBD_STATUS_PORT) &
i = inb(IO_KBD + KBD_DATA_PORT);
return (inb(port));
mpbiosreason = inb(CMOS_DATA);
return inb(port);
mpbiosreason = inb(CMOS_DATA);
#define iodev_read_1 inb
data = inb(port);
inb(adp->va_crtc_addr + 6); /* reset flip-flop */
inb(adp->va_crtc_addr + 6); /* reset flip-flop */
if (inb(TSREG) & 1)
inb(adp->va_crtc_addr + 6);
inb(adp->va_crtc_addr + 6);
outb(TSIDX, 0x02); buf[0] = inb(TSREG);
outb(TSIDX, 0x04); buf[1] = inb(TSREG);
outb(GDCIDX, 0x04); buf[2] = inb(GDCREG);
outb(GDCIDX, 0x05); buf[3] = inb(GDCREG);
outb(GDCIDX, 0x06); buf[4] = inb(GDCREG);
inb(adp->va_crtc_addr + 6);
outb(ATC, 0x10); buf[5] = inb(ATC + 1);
inb(adp->va_crtc_addr + 6); /* reset flip-flop */
inb(adp->va_crtc_addr + 6); /* reset flip-flop */
inb(adp->va_crtc_addr + 6); /* reset flip-flop */
inb(adp->va_crtc_addr + 6); /* reset flip-flop */
outb(TSIDX, 0x01); val = inb(TSREG); /* disable screen */
outb(TSIDX, 0x01); val = inb(TSREG); /* disable screen */
palette[i] = inb(PALDATA) << bits;
inb(adp->va_crtc_addr + 6); /* reset flip/flop */
r[i] = inb(PALDATA) << bits;
g[i] = inb(PALDATA) << bits;
b[i] = inb(PALDATA) << bits;
inb(adp->va_crtc_addr + 6); /* reset flip/flop */
inb(adp->va_crtc_addr + 6); /* reset flip/flop */
inb(adp->va_crtc_addr + 6); /* reset flip/flop */
inb(adp->va_crtc_addr + 6); /* reset flip-flop */
buf[j++] = inb(TSREG);
buf[9] = inb(MISC + 10); /* dot-clock */
buf[j++] = inb(crtc_addr + 1);
inb(crtc_addr + 6); /* reset flip-flop */
buf[j++] = inb(ATC + 1);
buf[j++] = inb(GDCREG);
inb(crtc_addr + 6); /* reset flip-flop */
outb(crtc_addr + 1, inb(crtc_addr + 1) & 0x7F);
inb(crtc_addr+6); /* reset flip-flop */
inb(crtc_addr + 6); /* reset flip-flop */
off = inb(adp->va_crtc_addr + 1);
off = (off << 8) | inb(adp->va_crtc_addr + 1);
val = inb(TSREG);
val = inb(adp->va_crtc_addr + 1);
val = inb(TSREG);
val = inb(TSREG);
val = inb(adp->va_crtc_addr + 1);
if (inb(adp->va_crtc_addr) == 7) {
HPT_U8 os_inb (void *port) { return inb((unsigned)(HPT_UPTR)port); }
HPT_U8 os_inb (void *port) { return inb((unsigned)(HPT_UPTR)port); }
HPT_U8 os_inb (void *port) { return inb((unsigned)(HPT_UPTR)port); }
int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
struct mlx5_cmd_msg *inb;
inb = alloc_msg(dev, in_size, gfp);
if (IS_ERR(inb)) {
err = PTR_ERR(inb);
err = mlx5_copy_to_msg(inb, in, in_size);
err = mlx5_cmd_invoke(dev, inb, in_size, outb, out, out_size, callback,
free_msg(dev, inb);
int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
memcpy(data, inb, MLX5_FLD_SZ_BYTES(mad_ifc_in, mad));
if ((inb(bank) ^ inb(bank)) == 0)
if (inb(bank) & SM_FLASH_STATUS_DONE)
hefere = inb(efdr) & WINB_HEFERE;
hefras = inb(efdr) & WINB_HEFRAS;
if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
switch (inb(efdr) & WINB_CHIPID) {
printf("0x%x ", inb(efdr));
printf("0x%x ", inb(efdr));
printf("0x%x ", inb(efdr));
printf("0x%x ", inb(efdr));
r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
r |= (inb(efdr) & WINB_PRTMODS2);
outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
outb(efdr, inb(efdr) | WINB_ECP_EPP);
outb(efdr, inb(efdr) | WINB_ECP);
outb(efdr, inb(efdr) | WINB_EPP_SPP);
(void)inb(idport); (void)inb(idport);
(void)inb(idport); (void)inb(idport);
val = inb(idport + 1);
inb(idport + 1) & 0xff);
val = inb(idport + 1);
val = inb(idport + 1);
val = inb(idport + 1) & 0x3;
ptr = inb(idport + 1);
pcr = inb(idport + 1);
ptr = inb(idport + 1);
ptr = inb(idport + 1);
ptr = inb(idport + 1);
ptr = inb(idport + 1);
if (inb(cio) == 0x65) {
if (inb(cio) == 0x66) {
r = inb(cio) & SMC_CR1_ADDR;
inb(cio) & 0xff);
printf(" CR4=0x%x", inb(cio) & 0xff);
if ((inb(cio) & SMC_CR1_MODE) == 0) {
r = (inb(cio) & SMC_CR4_EMODE);
r = inb(cio);
r = inb(cio) & ~SMC_CR4_EMODE;
r = inb(cio);
if (inb(SMC935_DAT) == 0x2)
dest[i] = inb(0x79);
if ((inb(0x79) & 0x80) != 0)
!(inb(crtc_addr + 6) & 0x08))
ret_byte = inb(workport);
while ((inb(stat) & LSR_THRE) == 0 && --limit > 0)
mpbiosreason = inb(CMOS_DATA);
inb(cba + 0x3c), inb(cba + 0x3d));
return inb(port);
#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
mpbiosreason = inb(CMOS_DATA);
return inb(0x23);
#define iodev_read_1 inb
data = inb(port);
header = inb(port);
oldval2 = inb(CONF2_ENABLE_PORT);
mode2res = inb(CONF2_ENABLE_PORT);
bit = inb((pnp_rd_port << 2) | 0x3) == 0x55;
bit = (inb((pnp_rd_port << 2) | 0x3) == 0xaa) && bit;
if ((inb((pnp_rd_port << 2) | 0x3)) & 0x1)
temp = inb((pnp_rd_port << 2) | 0x3);
struct in_addr in, inb;
inb.s_addr = in.s_addr;
(inb.s_addr % np->in_ippip);
inb.s_addr = htonl(in.s_addr);
(u_int)fin->fin_p, fin->fin_dst, inb);
struct in_addr in, inb;
inb.s_addr = htonl(in.s_addr);
fin->fin_dst, inb, (u_32_t)dport);
inb.s_addr = htonl(in.s_addr);
(u_int)fin->fin_p, inb, fin->fin_src);
inb.s_addr = htonl(in.s_addr);
fin->fin_dst, inb, (u_32_t)dport);
inb = in;
(inb.s_addr % np->in_ippip);
#define in8(a) inb(a)
#define in8rb(a) inb(a)
return (inb(handle + offset));
outb(addr2, inb(addr1));
outb(addr2, inb(addr1));
#define ppi_spkr_on() outb(IO_PPI, inb(IO_PPI) | PIT_SPKR)
#define ppi_spkr_off() outb(IO_PPI, inb(IO_PPI) & ~PIT_SPKR)
return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
isr = inb(port);
inb(0x84);
inb(0x84);
return (inb(IO_RTC + 1));
inb(0x84);
inb(0x84);
inb(0x84);
low = inb(TIMER_CNTR0);
high = inb(TIMER_CNTR0);
inb(0x84);
low = inb(TIMER_CNTR0);
high = inb(TIMER_CNTR0);
elcr_status = inb(ELCR_PORT) | inb(ELCR_PORT + 1) << 8;
low1 = inb(waport);
high1 = inb(waport);
low2 = inb(waport);
high2 = inb(waport);
return(inb(DMA1_STATUS) & (1 << chan));
return(inb(DMA2_STATUS) & (1 << (chan & 3)));
int isa_port = inb(0x61);
int eisa_port = inb(0x461);
b = inb(0x92);
inb(0x84);
byte = inb(0x23); /* current contents */
buf[i] = inb(FWCTL_IN);
static int compare(const void * ina, const void * inb) {
PTW_tableentry * b = (PTW_tableentry * )inb;
static int comparedoublesorthelper(const void * ina, const void * inb) {
doublesorthelper * b = (doublesorthelper * )inb;
static int comparesorthelper(const void * ina, const void * inb) {
sorthelper * b = (sorthelper * ) inb;