Symbol: hypctx
sys/arm64/vmm/arm64.h
308
#define __hypctx_vncr_sysreg(hypctx, reg) \
sys/arm64/vmm/arm64.h
309
((uint64_t *)((char *)hypctx->vncr_regs + REG_VNCR_OFFSET(reg)))
sys/arm64/vmm/arm64.h
313
#define __hypctx_va_sysreg(hypctx, reg) \
sys/arm64/vmm/arm64.h
314
(&hypctx->va_regs[reg - VA_REGS_START - 1])
sys/arm64/vmm/arm64.h
320
hypctx_sys_reg(struct hypctx *hypctx, int reg /* enum hypctx_sysreg */)
sys/arm64/vmm/arm64.h
324
return (__hypctx_va_sysreg(hypctx, reg));
sys/arm64/vmm/arm64.h
326
return (__hypctx_vncr_sysreg(hypctx, reg));
sys/arm64/vmm/arm64.h
327
return (&hypctx->sys_regs[reg]);
sys/arm64/vmm/arm64.h
331
hypctx_write_sys_reg(struct hypctx *hypctx, enum hypctx_sysreg reg,
sys/arm64/vmm/arm64.h
334
*hypctx_sys_reg(hypctx, reg) = val;
sys/arm64/vmm/arm64.h
338
hypctx_read_sys_reg(struct hypctx *hypctx, enum hypctx_sysreg reg)
sys/arm64/vmm/arm64.h
340
return (*hypctx_sys_reg(hypctx, reg));
sys/arm64/vmm/arm64.h
355
struct hypctx *ctx[];
sys/arm64/vmm/arm64.h
366
struct hypctx *arm64_get_active_vcpu(void);
sys/arm64/vmm/arm64.h
367
void raise_data_insn_abort(struct hypctx *, uint64_t, bool, int);
sys/arm64/vmm/hyp_genassym.c
34
ASSYM(HYPCTX_GPR_LR, offsetof(struct hypctx, va_regs) + (GPR_LR - VA_REGS_START - 1) * sizeof(uint64_t));
sys/arm64/vmm/hyp_genassym.c
35
ASSYM(HYPCTX_GPR_X0, offsetof(struct hypctx, va_regs) + (GPR_X0 - VA_REGS_START - 1) * sizeof(uint64_t));
sys/arm64/vmm/io/vgic.c
113
vgic_flush_hwstate(struct hypctx *hypctx)
sys/arm64/vmm/io/vgic.c
115
VGIC_FLUSH_HWSTATE(vgic_dev, hypctx);
sys/arm64/vmm/io/vgic.c
119
vgic_sync_hwstate(struct hypctx *hypctx)
sys/arm64/vmm/io/vgic.c
121
VGIC_SYNC_HWSTATE(vgic_dev, hypctx);
sys/arm64/vmm/io/vgic.c
69
vgic_cpuinit(struct hypctx *hypctx)
sys/arm64/vmm/io/vgic.c
71
VGIC_CPUINIT(vgic_dev, hypctx);
sys/arm64/vmm/io/vgic.c
75
vgic_cpucleanup(struct hypctx *hypctx)
sys/arm64/vmm/io/vgic.c
77
VGIC_CPUCLEANUP(vgic_dev, hypctx);
sys/arm64/vmm/io/vgic.c
93
vgic_has_pending_irq(struct hypctx *hypctx)
sys/arm64/vmm/io/vgic.c
95
return (VGIC_HAS_PENDING_IRQ(vgic_dev, hypctx));
sys/arm64/vmm/io/vgic.h
32
struct hypctx;
sys/arm64/vmm/io/vgic.h
42
void vgic_cpuinit(struct hypctx *hypctx);
sys/arm64/vmm/io/vgic.h
43
void vgic_cpucleanup(struct hypctx *hypctx);
sys/arm64/vmm/io/vgic.h
46
bool vgic_has_pending_irq(struct hypctx *hypctx);
sys/arm64/vmm/io/vgic.h
49
void vgic_flush_hwstate(struct hypctx *hypctx);
sys/arm64/vmm/io/vgic.h
50
void vgic_sync_hwstate(struct hypctx *hypctx);
sys/arm64/vmm/io/vgic_v3.c
1001
hyp = hypctx->hyp;
sys/arm64/vmm/io/vgic_v3.c
1013
dist_ctlr_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1020
vgic = hypctx->hyp->vgic;
sys/arm64/vmm/io/vgic_v3.c
1042
dist_typer_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
1057
dist_iidr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1064
dist_setclrspi_nsr_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1072
INJECT_IRQ(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu), irqid,
sys/arm64/vmm/io/vgic_v3.c
1078
dist_isenabler_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1085
*rval = read_enabler(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1089
dist_isenabler_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1099
write_enabler(hypctx, n, true, wval);
sys/arm64/vmm/io/vgic_v3.c
1104
dist_icenabler_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1111
*rval = read_enabler(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1115
dist_icenabler_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1125
write_enabler(hypctx, n, false, wval);
sys/arm64/vmm/io/vgic_v3.c
1130
dist_ispendr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1137
*rval = read_pendr(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1141
dist_ispendr_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1151
write_pendr(hypctx, n, true, wval);
sys/arm64/vmm/io/vgic_v3.c
1156
dist_icpendr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1163
*rval = read_pendr(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1167
dist_icpendr_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1177
write_pendr(hypctx, n, false, wval);
sys/arm64/vmm/io/vgic_v3.c
1183
dist_isactiver_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1190
*rval = read_activer(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1194
dist_isactiver_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1204
write_activer(hypctx, n, true, wval);
sys/arm64/vmm/io/vgic_v3.c
1209
dist_icactiver_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
1217
*rval = read_activer(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1221
dist_icactiver_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1231
write_activer(hypctx, n, false, wval);
sys/arm64/vmm/io/vgic_v3.c
1237
dist_ipriorityr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
1245
*rval = read_priorityr(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1249
dist_ipriorityr_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1257
write_priorityr(hypctx, irq_base, size, wval);
sys/arm64/vmm/io/vgic_v3.c
1262
dist_icfgr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1269
*rval = read_config(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1273
dist_icfgr_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1283
write_config(hypctx, n, wval);
sys/arm64/vmm/io/vgic_v3.c
1288
dist_irouter_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1295
*rval = read_route(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1299
dist_irouter_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1307
write_route(hypctx, n, wval, offset, size);
sys/arm64/vmm/io/vgic_v3.c
1311
vgic_register_read(struct hypctx *hypctx, struct vgic_register *reg_list,
sys/arm64/vmm/io/vgic_v3.c
1321
reg_list[i].read(hypctx, reg, rval, NULL);
sys/arm64/vmm/io/vgic_v3.c
1346
vgic_register_write(struct hypctx *hypctx, struct vgic_register *reg_list,
sys/arm64/vmm/io/vgic_v3.c
1356
reg_list[i].write(hypctx, reg, offset,
sys/arm64/vmm/io/vgic_v3.c
1376
struct hypctx *hypctx;
sys/arm64/vmm/io/vgic_v3.c
1380
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vgic_v3.c
1381
hyp = hypctx->hyp;
sys/arm64/vmm/io/vgic_v3.c
1399
if (vgic_register_read(hypctx, dist_registers, nitems(dist_registers),
sys/arm64/vmm/io/vgic_v3.c
1414
struct hypctx *hypctx;
sys/arm64/vmm/io/vgic_v3.c
1418
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vgic_v3.c
1419
hyp = hypctx->hyp;
sys/arm64/vmm/io/vgic_v3.c
1435
if (vgic_register_write(hypctx, dist_registers, nitems(dist_registers),
sys/arm64/vmm/io/vgic_v3.c
1450
redist_ctlr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1458
redist_iidr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1465
redist_typer_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1471
if (vcpu_vcpuid(hypctx->vcpu) == (vgic_max_cpu_count(hypctx->hyp) - 1))
sys/arm64/vmm/io/vgic_v3.c
1474
vmpidr_el2 = hypctx_read_sys_reg(hypctx, HOST_VMPIDR_EL2);
sys/arm64/vmm/io/vgic_v3.c
1488
(uint64_t)vcpu_vcpuid(hypctx->vcpu) << GICR_TYPER_CPUNUM_SHIFT;
sys/arm64/vmm/io/vgic_v3.c
1502
redist_ienabler0_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
1505
*rval = read_enabler(hypctx, 0);
sys/arm64/vmm/io/vgic_v3.c
1509
redist_isenabler0_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1514
write_enabler(hypctx, 0, true, wval);
sys/arm64/vmm/io/vgic_v3.c
1519
redist_icenabler0_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1524
write_enabler(hypctx, 0, false, wval);
sys/arm64/vmm/io/vgic_v3.c
1529
redist_ipendr0_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
1532
*rval = read_pendr(hypctx, 0);
sys/arm64/vmm/io/vgic_v3.c
1536
redist_ispendr0_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1541
write_pendr(hypctx, 0, true, wval);
sys/arm64/vmm/io/vgic_v3.c
1546
redist_icpendr0_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1551
write_pendr(hypctx, 0, false, wval);
sys/arm64/vmm/io/vgic_v3.c
1556
redist_iactiver0_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
1559
*rval = read_activer(hypctx, 0);
sys/arm64/vmm/io/vgic_v3.c
1563
redist_isactiver0_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1566
write_activer(hypctx, 0, true, wval);
sys/arm64/vmm/io/vgic_v3.c
1571
redist_icactiver0_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1574
write_activer(hypctx, 0, false, wval);
sys/arm64/vmm/io/vgic_v3.c
1579
redist_ipriorityr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
158
typedef void (register_read)(struct hypctx *, u_int, uint64_t *, void *);
sys/arm64/vmm/io/vgic_v3.c
1585
*rval = read_priorityr(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1589
redist_ipriorityr_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
159
typedef void (register_write)(struct hypctx *, u_int, u_int, u_int,
sys/arm64/vmm/io/vgic_v3.c
1595
write_priorityr(hypctx, irq_base, size, wval);
sys/arm64/vmm/io/vgic_v3.c
1600
redist_icfgr1_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1602
*rval = read_config(hypctx, 1);
sys/arm64/vmm/io/vgic_v3.c
1606
redist_icfgr1_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1611
write_config(hypctx, 1, wval);
sys/arm64/vmm/io/vgic_v3.c
1619
struct hypctx *hypctx, *target_hypctx;
sys/arm64/vmm/io/vgic_v3.c
1625
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vgic_v3.c
1626
hyp = hypctx->hyp;
sys/arm64/vmm/io/vgic_v3.c
1659
raise_data_insn_abort(hypctx, fault_ipa, true,
sys/arm64/vmm/io/vgic_v3.c
1697
struct hypctx *hypctx, *target_hypctx;
sys/arm64/vmm/io/vgic_v3.c
1703
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vgic_v3.c
1704
hyp = hypctx->hyp;
sys/arm64/vmm/io/vgic_v3.c
1736
raise_data_insn_abort(hypctx, fault_ipa, true,
sys/arm64/vmm/io/vgic_v3.c
1946
struct hypctx *hypctx;
sys/arm64/vmm/io/vgic_v3.c
1951
hypctx = hyp->ctx[vcpuid];
sys/arm64/vmm/io/vgic_v3.c
1952
if (hypctx == NULL)
sys/arm64/vmm/io/vgic_v3.c
1954
vgic_cpu = hypctx->vgic_cpu;
sys/arm64/vmm/io/vgic_v3.c
1980
vgic_v3_has_pending_irq(device_t dev, struct hypctx *hypctx)
sys/arm64/vmm/io/vgic_v3.c
1985
vgic_cpu = hypctx->vgic_cpu;
sys/arm64/vmm/io/vgic_v3.c
2019
struct hypctx *hypctx;
sys/arm64/vmm/io/vgic_v3.c
2052
hypctx = hyp->ctx[vcpuid];
sys/arm64/vmm/io/vgic_v3.c
2053
if (hypctx == NULL) {
sys/arm64/vmm/io/vgic_v3.c
2059
vgic_cpu = hypctx->vgic_cpu;
sys/arm64/vmm/io/vgic_v3.c
2105
vgic_v3_flush_hwstate(device_t dev, struct hypctx *hypctx)
sys/arm64/vmm/io/vgic_v3.c
2111
vgic_cpu = hypctx->vgic_cpu;
sys/arm64/vmm/io/vgic_v3.c
2122
*hypctx_sys_reg(hypctx, HOST_ICH_HCR_EL2) &= ~ICH_HCR_EL2_UIE;
sys/arm64/vmm/io/vgic_v3.c
2132
hypctx_write_sys_reg(hypctx, HOST_ICH_ELRSR_EL2,
sys/arm64/vmm/io/vgic_v3.c
2133
(1u << hypctx->vgic_v3.ich_lr_num) - 1);
sys/arm64/vmm/io/vgic_v3.c
2136
if (i == hypctx->vgic_v3.ich_lr_num)
sys/arm64/vmm/io/vgic_v3.c
2148
hypctx_write_sys_reg(hypctx, HOST_ICH_LR_EL2(i),
sys/arm64/vmm/io/vgic_v3.c
2154
*hypctx_sys_reg(hypctx, HOST_ICH_LR_EL2(i)) |=
sys/arm64/vmm/io/vgic_v3.c
2161
*hypctx_sys_reg(hypctx, HOST_ICH_LR_EL2(i)) |= ICH_LR_EL2_EOI;
sys/arm64/vmm/io/vgic_v3.c
2165
*hypctx_sys_reg(hypctx, HOST_ICH_LR_EL2(i)) |=
sys/arm64/vmm/io/vgic_v3.c
2188
vgic_v3_sync_hwstate(device_t dev, struct hypctx *hypctx)
sys/arm64/vmm/io/vgic_v3.c
2195
vgic_cpu = hypctx->vgic_cpu;
sys/arm64/vmm/io/vgic_v3.c
2207
lr = hypctx_read_sys_reg(hypctx, HOST_ICH_LR_EL2(i));
sys/arm64/vmm/io/vgic_v3.c
2208
hypctx_write_sys_reg(hypctx, HOST_ICH_LR_EL2(i), 0);
sys/arm64/vmm/io/vgic_v3.c
2210
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
2255
*hypctx_sys_reg(hypctx, HOST_ICH_HCR_EL2) &= ~ICH_HCR_EL2_EOICOUNT_MASK;
sys/arm64/vmm/io/vgic_v3.c
429
struct hypctx *hypctx;
sys/arm64/vmm/io/vgic_v3.c
433
hypctx = hyp->ctx[i];
sys/arm64/vmm/io/vgic_v3.c
434
if (hypctx != NULL && (hypctx_read_sys_reg(hypctx, HOST_VMPIDR_EL2) & GICD_AFF) == mpidr)
sys/arm64/vmm/io/vgic_v3.c
465
vgic_v3_cpuinit(device_t dev, struct hypctx *hypctx)
sys/arm64/vmm/io/vgic_v3.c
471
hypctx->vgic_cpu = malloc(sizeof(*hypctx->vgic_cpu),
sys/arm64/vmm/io/vgic_v3.c
473
vgic_cpu = hypctx->vgic_cpu;
sys/arm64/vmm/io/vgic_v3.c
484
irq->mpidr = hypctx_read_sys_reg(hypctx, HOST_VMPIDR_EL2) & GICD_AFF;
sys/arm64/vmm/io/vgic_v3.c
485
irq->target_vcpu = vcpu_vcpuid(hypctx->vcpu);
sys/arm64/vmm/io/vgic_v3.c
506
hypctx_write_sys_reg(hypctx, HOST_ICH_HCR_EL2, ICH_HCR_EL2_En);
sys/arm64/vmm/io/vgic_v3.c
521
hypctx_write_sys_reg(hypctx, HOST_ICH_VMCR_EL2,
sys/arm64/vmm/io/vgic_v3.c
525
*hypctx_sys_reg(hypctx, HOST_ICH_VMCR_EL2) &= ~ICH_VMCR_EL2_VEOIM;
sys/arm64/vmm/io/vgic_v3.c
526
*hypctx_sys_reg(hypctx, HOST_ICH_VMCR_EL2) |= ICH_VMCR_EL2_VENG0 |
sys/arm64/vmm/io/vgic_v3.c
529
hypctx->vgic_v3.ich_lr_num = virt_features.ich_lr_num;
sys/arm64/vmm/io/vgic_v3.c
530
for (i = 0; i < hypctx->vgic_v3.ich_lr_num; i++)
sys/arm64/vmm/io/vgic_v3.c
531
hypctx_write_sys_reg(hypctx, HOST_ICH_LR_EL2(i), 0UL);
sys/arm64/vmm/io/vgic_v3.c
535
hypctx->vgic_v3.ich_apr_num = virt_features.ich_apr_num;
sys/arm64/vmm/io/vgic_v3.c
539
vgic_v3_cpucleanup(device_t dev, struct hypctx *hypctx)
sys/arm64/vmm/io/vgic_v3.c
545
vgic_cpu = hypctx->vgic_cpu;
sys/arm64/vmm/io/vgic_v3.c
552
free(hypctx->vgic_cpu, M_VGIC_V3);
sys/arm64/vmm/io/vgic_v3.c
639
gic_pidr2_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
647
gic_zero_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
654
gic_ignore_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
661
read_enabler(struct hypctx *hypctx, int n)
sys/arm64/vmm/io/vgic_v3.c
671
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
685
write_enabler(struct hypctx *hypctx,int n, bool set, uint64_t val)
sys/arm64/vmm/io/vgic_v3.c
698
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
709
read_pendr(struct hypctx *hypctx, int n)
sys/arm64/vmm/io/vgic_v3.c
719
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
733
write_pendr(struct hypctx *hypctx, int n, bool set, uint64_t val)
sys/arm64/vmm/io/vgic_v3.c
738
struct hypctx *target_hypctx;
sys/arm64/vmm/io/vgic_v3.c
744
hyp = hypctx->hyp;
sys/arm64/vmm/io/vgic_v3.c
752
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
787
read_activer(struct hypctx *hypctx, int n)
sys/arm64/vmm/io/vgic_v3.c
797
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
811
write_activer(struct hypctx *hypctx, u_int n, bool set, uint64_t val)
sys/arm64/vmm/io/vgic_v3.c
816
struct hypctx *target_hypctx;
sys/arm64/vmm/io/vgic_v3.c
821
hyp = hypctx->hyp;
sys/arm64/vmm/io/vgic_v3.c
828
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
862
read_priorityr(struct hypctx *hypctx, int n)
sys/arm64/vmm/io/vgic_v3.c
872
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
885
write_priorityr(struct hypctx *hypctx, u_int irq_base, u_int size, uint64_t val)
sys/arm64/vmm/io/vgic_v3.c
891
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
903
read_config(struct hypctx *hypctx, int n)
sys/arm64/vmm/io/vgic_v3.c
913
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
926
write_config(struct hypctx *hypctx, int n, uint64_t val)
sys/arm64/vmm/io/vgic_v3.c
942
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
954
read_route(struct hypctx *hypctx, int n)
sys/arm64/vmm/io/vgic_v3.c
959
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu), n);
sys/arm64/vmm/io/vgic_v3.c
970
write_route(struct hypctx *hypctx, int n, uint64_t val, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
975
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu), n);
sys/arm64/vmm/io/vgic_v3.c
980
irq->target_vcpu = mpidr_to_vcpu(hypctx->hyp, irq->mpidr);
sys/arm64/vmm/io/vgic_v3.c
995
dist_ctlr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vtimer.c
100
hypctx_read_sys_reg(hypctx, HOST_CNTVOFF_EL2);
sys/arm64/vmm/io/vtimer.c
101
if (hypctx->vtimer_cpu.virt_timer.cntx_cval_el0 < cntpct_el0)
sys/arm64/vmm/io/vtimer.c
102
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vtimer.c
105
cntv_ctl = hypctx->vtimer_cpu.virt_timer.cntx_ctl_el0;
sys/arm64/vmm/io/vtimer.c
136
vtimer_cpuinit(struct hypctx *hypctx)
sys/arm64/vmm/io/vtimer.c
141
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
164
if (allow_ecv_phys && (hypctx->hyp->feats & HYP_FEAT_ECV_POFF) != 0)
sys/arm64/vmm/io/vtimer.c
189
hypctx_write_sys_reg(hypctx, HOST_CNTHCTL_EL2,
sys/arm64/vmm/io/vtimer.c
193
*hypctx_sys_reg(hypctx, HOST_CNTHCTL_EL2) |=
sys/arm64/vmm/io/vtimer.c
199
*hypctx_sys_reg(hypctx, HOST_CNTHCTL_EL2) |=
sys/arm64/vmm/io/vtimer.c
212
hypctx_write_sys_reg(hypctx, HOST_CNTHCTL_EL2,
sys/arm64/vmm/io/vtimer.c
216
hypctx_write_sys_reg(hypctx, HOST_CNTHCTL_EL2,
sys/arm64/vmm/io/vtimer.c
223
*hypctx_sys_reg(hypctx, HOST_CNTHCTL_EL2) |= CNTHCTL_ECV_EN;
sys/arm64/vmm/io/vtimer.c
225
hypctx_write_sys_reg(hypctx, HOST_CNTVOFF_EL2, hypctx->hyp->cntvoff_el2);
sys/arm64/vmm/io/vtimer.c
229
vtimer_cpucleanup(struct hypctx *hypctx)
sys/arm64/vmm/io/vtimer.c
233
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
243
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
246
hypctx = arm64_get_active_vcpu();
sys/arm64/vmm/io/vtimer.c
247
if (!hypctx) {
sys/arm64/vmm/io/vtimer.c
261
vtime_sync_timer(struct hypctx *hypctx, struct vtimer_timer *timer,
sys/arm64/vmm/io/vtimer.c
265
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vtimer.c
268
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vtimer.c
271
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vtimer.c
273
vtimer_schedule_irq(hypctx, false);
sys/arm64/vmm/io/vtimer.c
278
vtimer_sync_hwstate(struct hypctx *hypctx)
sys/arm64/vmm/io/vtimer.c
283
hypctx_read_sys_reg(hypctx, HOST_CNTVOFF_EL2);
sys/arm64/vmm/io/vtimer.c
284
vtime_sync_timer(hypctx, &hypctx->vtimer_cpu.virt_timer, cntpct_el0);
sys/arm64/vmm/io/vtimer.c
286
if ((hypctx_read_sys_reg(hypctx, HOST_CNTHCTL_EL2) & CNTHCTL_ECV_EN) != 0) {
sys/arm64/vmm/io/vtimer.c
287
vtime_sync_timer(hypctx, &hypctx->vtimer_cpu.phys_timer,
sys/arm64/vmm/io/vtimer.c
295
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
297
hypctx = context;
sys/arm64/vmm/io/vtimer.c
298
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vtimer.c
299
hypctx->vtimer_cpu.phys_timer.irqid, true);
sys/arm64/vmm/io/vtimer.c
305
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
307
hypctx = context;
sys/arm64/vmm/io/vtimer.c
308
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vtimer.c
309
hypctx->vtimer_cpu.virt_timer.irqid, true);
sys/arm64/vmm/io/vtimer.c
313
vtimer_schedule_irq(struct hypctx *hypctx, bool phys)
sys/arm64/vmm/io/vtimer.c
321
timer = &hypctx->vtimer_cpu.phys_timer;
sys/arm64/vmm/io/vtimer.c
323
timer = &hypctx->vtimer_cpu.virt_timer;
sys/arm64/vmm/io/vtimer.c
325
hypctx_read_sys_reg(hypctx, HOST_CNTVOFF_EL2);
sys/arm64/vmm/io/vtimer.c
328
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vtimer.c
335
vtimer_inject_irq_callout_phys, hypctx, 0);
sys/arm64/vmm/io/vtimer.c
338
vtimer_inject_irq_callout_virt, hypctx, 0);
sys/arm64/vmm/io/vtimer.c
343
vtimer_remove_irq(struct hypctx *hypctx, struct vcpu *vcpu)
sys/arm64/vmm/io/vtimer.c
348
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
358
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(vcpu), timer->irqid, false);
sys/arm64/vmm/io/vtimer.c
375
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
379
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vtimer.c
380
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
382
cntpct_el0 = READ_SPECIALREG(cntpct_el0) - hypctx_read_sys_reg(hypctx, HOST_CNTVOFF_EL2);
sys/arm64/vmm/io/vtimer.c
395
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
400
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vtimer.c
401
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
409
vtimer_remove_irq(hypctx, vcpu);
sys/arm64/vmm/io/vtimer.c
414
vtimer_schedule_irq(hypctx, true);
sys/arm64/vmm/io/vtimer.c
422
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
424
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vtimer.c
425
*rval = READ_SPECIALREG(cntpct_el0) - hypctx_read_sys_reg(hypctx, HOST_CNTVOFF_EL2);
sys/arm64/vmm/io/vtimer.c
438
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
441
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vtimer.c
442
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
452
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
455
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vtimer.c
456
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
460
vtimer_remove_irq(hypctx, vcpu);
sys/arm64/vmm/io/vtimer.c
462
vtimer_schedule_irq(hypctx, true);
sys/arm64/vmm/io/vtimer.c
471
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
475
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vtimer.c
476
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
488
hypctx_read_sys_reg(hypctx, HOST_CNTVOFF_EL2);
sys/arm64/vmm/io/vtimer.c
498
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
502
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vtimer.c
503
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
505
cntpct_el0 = READ_SPECIALREG(cntpct_el0) - hypctx_read_sys_reg(hypctx, HOST_CNTVOFF_EL2);
sys/arm64/vmm/io/vtimer.c
508
vtimer_remove_irq(hypctx, vcpu);
sys/arm64/vmm/io/vtimer.c
510
vtimer_schedule_irq(hypctx, true);
sys/arm64/vmm/io/vtimer.c
72
static void vtimer_schedule_irq(struct hypctx *hypctx, bool phys);
sys/arm64/vmm/io/vtimer.c
77
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
81
hypctx = arm64_get_active_vcpu();
sys/arm64/vmm/io/vtimer.c
84
if (!hypctx) {
sys/arm64/vmm/io/vtimer.h
38
struct hypctx;
sys/arm64/vmm/io/vtimer.h
65
void vtimer_cpuinit(struct hypctx *);
sys/arm64/vmm/io/vtimer.h
66
void vtimer_cpucleanup(struct hypctx *);
sys/arm64/vmm/io/vtimer.h
69
void vtimer_sync_hwstate(struct hypctx *hypctx);
sys/arm64/vmm/vmm.c
431
struct hypctx *hypctx;
sys/arm64/vmm/vmm.c
433
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/vmm.c
436
hypctx->dbg_oslock = (wval & OSLAR_OSLK) == OSLAR_OSLK;
sys/arm64/vmm/vmm.c
443
struct hypctx *hypctx;
sys/arm64/vmm/vmm.c
446
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/vmm.c
448
if (hypctx->dbg_oslock)
sys/arm64/vmm/vmm.c
860
struct hypctx *hypctx;
sys/arm64/vmm/vmm.c
863
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/vmm.c
865
if ((hypctx_read_sys_reg(hypctx, HOST_ESR_EL2) & ESR_ELx_ISS_MASK) != 0)
sys/arm64/vmm/vmm.c
869
vme->u.smccc_call.func_id = hypctx_read_sys_reg(hypctx, GPR_X(0));
sys/arm64/vmm/vmm.c
871
vme->u.smccc_call.args[i] = hypctx_read_sys_reg(hypctx, GPR_X(i + 1));
sys/arm64/vmm/vmm_arm64.c
1003
hypctx = (struct hypctx *)vcpui;
sys/arm64/vmm/vmm_arm64.c
1018
ptep = ptp_hold(hypctx->vcpu, pte_addr, PAGE_SIZE, &cookie);
sys/arm64/vmm/vmm_arm64.c
107
DPCPU_DEFINE_STATIC(struct hypctx *, vcpu);
sys/arm64/vmm/vmm_arm64.c
110
arm64_set_active_vcpu(struct hypctx *hypctx)
sys/arm64/vmm/vmm_arm64.c
1101
struct hypctx *hypctx;
sys/arm64/vmm/vmm_arm64.c
1106
hypctx = (struct hypctx *)vcpui;
sys/arm64/vmm/vmm_arm64.c
1107
hyp = hypctx->hyp;
sys/arm64/vmm/vmm_arm64.c
1108
vcpu = hypctx->vcpu;
sys/arm64/vmm/vmm_arm64.c
1111
hypctx_write_sys_reg(hypctx, HOST_ELR_EL2, (uint64_t)pc);
sys/arm64/vmm/vmm_arm64.c
1114
if (hypctx->has_exception) {
sys/arm64/vmm/vmm_arm64.c
1115
hypctx->has_exception = false;
sys/arm64/vmm/vmm_arm64.c
1116
hypctx_write_sys_reg(hypctx, ELR_EL1,
sys/arm64/vmm/vmm_arm64.c
1117
hypctx_read_sys_reg(hypctx, HOST_ELR_EL2));
sys/arm64/vmm/vmm_arm64.c
1119
mode = hypctx_read_sys_reg(hypctx, HOST_SPSR_EL2) &
sys/arm64/vmm/vmm_arm64.c
112
DPCPU_SET(vcpu, hypctx);
sys/arm64/vmm/vmm_arm64.c
1122
vbar_el1 = hypctx_read_sys_reg(hypctx, VBAR_EL1);
sys/arm64/vmm/vmm_arm64.c
1124
hypctx_write_sys_reg(hypctx, HOST_ELR_EL2,
sys/arm64/vmm/vmm_arm64.c
1127
hypctx_write_sys_reg(hypctx, HOST_ELR_EL2,
sys/arm64/vmm/vmm_arm64.c
1131
hypctx_write_sys_reg(hypctx, HOST_ELR_EL2,
sys/arm64/vmm/vmm_arm64.c
1135
hypctx_write_sys_reg(hypctx, HOST_ELR_EL2,
sys/arm64/vmm/vmm_arm64.c
1140
new_spsr = hypctx_read_sys_reg(hypctx, HOST_SPSR_EL2);
sys/arm64/vmm/vmm_arm64.c
1141
hypctx_write_sys_reg(hypctx, SPSR_EL1, new_spsr);
sys/arm64/vmm/vmm_arm64.c
1144
hypctx_write_sys_reg(hypctx, HOST_SPSR_EL2,
sys/arm64/vmm/vmm_arm64.c
1146
*hypctx_sys_reg(hypctx, HOST_SPSR_EL2) |= PSR_DAIF |
sys/arm64/vmm/vmm_arm64.c
115
struct hypctx *
sys/arm64/vmm/vmm_arm64.c
1153
if ((hypctx_read_sys_reg(hypctx, SCTLR_EL1) &
sys/arm64/vmm/vmm_arm64.c
1155
*hypctx_sys_reg(hypctx,
sys/arm64/vmm/vmm_arm64.c
1157
if ((hypctx_read_sys_reg(hypctx, SCTLR_EL1) &
sys/arm64/vmm/vmm_arm64.c
1159
*hypctx_sys_reg(hypctx,
sys/arm64/vmm/vmm_arm64.c
1162
*hypctx_sys_reg(hypctx,
sys/arm64/vmm/vmm_arm64.c
1183
hypctx_write_sys_reg(hypctx, HOST_VTTBR_EL2,
sys/arm64/vmm/vmm_arm64.c
1190
arm64_set_active_vcpu(hypctx);
sys/arm64/vmm/vmm_arm64.c
1191
vgic_flush_hwstate(hypctx);
sys/arm64/vmm/vmm_arm64.c
1194
excp_type = vmm_enter_guest(hyp, hypctx);
sys/arm64/vmm/vmm_arm64.c
1196
vgic_sync_hwstate(hypctx);
sys/arm64/vmm/vmm_arm64.c
1197
vtimer_sync_hwstate(hypctx);
sys/arm64/vmm/vmm_arm64.c
1209
vme->pc = hypctx_read_sys_reg(hypctx, HOST_ELR_EL2);
sys/arm64/vmm/vmm_arm64.c
1212
vme->u.hyp.esr_el2 = hypctx_read_sys_reg(hypctx, HOST_ESR_EL2);
sys/arm64/vmm/vmm_arm64.c
1213
vme->u.hyp.far_el2 = hypctx_read_sys_reg(hypctx, HOST_FAR_EL2);
sys/arm64/vmm/vmm_arm64.c
1214
vme->u.hyp.hpfar_el2 = hypctx_read_sys_reg(hypctx, HOST_HPFAR_EL2);
sys/arm64/vmm/vmm_arm64.c
1216
handled = arm64_handle_world_switch(hypctx, excp_type, vme,
sys/arm64/vmm/vmm_arm64.c
1223
*hypctx_sys_reg(hypctx, HOST_ELR_EL2) += vme->inst_length;
sys/arm64/vmm/vmm_arm64.c
1248
struct hypctx *hypctx = vcpui;
sys/arm64/vmm/vmm_arm64.c
1250
vtimer_cpucleanup(hypctx);
sys/arm64/vmm/vmm_arm64.c
1251
vgic_cpucleanup(hypctx);
sys/arm64/vmm/vmm_arm64.c
1254
vmmpmap_remove(hypctx->el2_addr, el2_hypctx_size(), true);
sys/arm64/vmm/vmm_arm64.c
1256
free(hypctx, M_HYP);
sys/arm64/vmm/vmm_arm64.c
1280
hypctx_regptr(struct hypctx *hypctx, int reg)
sys/arm64/vmm/vmm_arm64.c
1284
return hypctx_sys_reg(hypctx, GPR_X(reg));
sys/arm64/vmm/vmm_arm64.c
1286
return hypctx_sys_reg(hypctx, GPR_LR);
sys/arm64/vmm/vmm_arm64.c
1288
return hypctx_sys_reg(hypctx, HOST_SP_EL1);
sys/arm64/vmm/vmm_arm64.c
1290
return hypctx_sys_reg(hypctx, HOST_SPSR_EL2);
sys/arm64/vmm/vmm_arm64.c
1292
return hypctx_sys_reg(hypctx, HOST_ELR_EL2);
sys/arm64/vmm/vmm_arm64.c
1294
return hypctx_sys_reg(hypctx, SCTLR_EL1);
sys/arm64/vmm/vmm_arm64.c
1296
return hypctx_sys_reg(hypctx, TTBR0_EL1);
sys/arm64/vmm/vmm_arm64.c
1298
return hypctx_sys_reg(hypctx, TTBR1_EL1);
sys/arm64/vmm/vmm_arm64.c
1300
return hypctx_sys_reg(hypctx, TCR_EL1);
sys/arm64/vmm/vmm_arm64.c
1302
return hypctx_sys_reg(hypctx, TCR2_EL1);
sys/arm64/vmm/vmm_arm64.c
1304
return hypctx_sys_reg(hypctx, HOST_VMPIDR_EL2);
sys/arm64/vmm/vmm_arm64.c
1316
struct hypctx *hypctx = vcpui;
sys/arm64/vmm/vmm_arm64.c
1318
running = vcpu_is_running(hypctx->vcpu, &hostcpu);
sys/arm64/vmm/vmm_arm64.c
1320
panic("arm_getreg: %s%d is running", vm_name(hypctx->hyp->vm),
sys/arm64/vmm/vmm_arm64.c
1321
vcpu_vcpuid(hypctx->vcpu));
sys/arm64/vmm/vmm_arm64.c
1323
regp = hypctx_regptr(hypctx, reg);
sys/arm64/vmm/vmm_arm64.c
1335
struct hypctx *hypctx = vcpui;
sys/arm64/vmm/vmm_arm64.c
1338
running = vcpu_is_running(hypctx->vcpu, &hostcpu);
sys/arm64/vmm/vmm_arm64.c
1340
panic("arm_setreg: %s%d is running", vm_name(hypctx->hyp->vm),
sys/arm64/vmm/vmm_arm64.c
1341
vcpu_vcpuid(hypctx->vcpu));
sys/arm64/vmm/vmm_arm64.c
1343
regp = hypctx_regptr(hypctx, reg);
sys/arm64/vmm/vmm_arm64.c
1354
struct hypctx *hypctx = vcpui;
sys/arm64/vmm/vmm_arm64.c
1357
running = vcpu_is_running(hypctx->vcpu, &hostcpu);
sys/arm64/vmm/vmm_arm64.c
1359
panic("%s: %s%d is running", __func__, vm_name(hypctx->hyp->vm),
sys/arm64/vmm/vmm_arm64.c
1360
vcpu_vcpuid(hypctx->vcpu));
sys/arm64/vmm/vmm_arm64.c
1362
hypctx_write_sys_reg(hypctx, FAR_EL1, far);
sys/arm64/vmm/vmm_arm64.c
1363
hypctx_write_sys_reg(hypctx, ESR_EL1, esr);
sys/arm64/vmm/vmm_arm64.c
1364
hypctx->has_exception = true;
sys/arm64/vmm/vmm_arm64.c
1372
struct hypctx *hypctx = vcpui;
sys/arm64/vmm/vmm_arm64.c
1385
*retval = (hypctx->setcaps & (1ul << num)) != 0;
sys/arm64/vmm/vmm_arm64.c
1397
struct hypctx *hypctx = vcpui;
sys/arm64/vmm/vmm_arm64.c
1405
if ((val != 0) == ((hypctx->setcaps & (1ul << num)) != 0))
sys/arm64/vmm/vmm_arm64.c
1408
*hypctx_sys_reg(hypctx, HOST_MDCR_EL2) |= MDCR_EL2_TDE;
sys/arm64/vmm/vmm_arm64.c
1409
else if ((hypctx->setcaps & (1ul << VM_CAP_SS_EXIT)) == 0)
sys/arm64/vmm/vmm_arm64.c
1410
*hypctx_sys_reg(hypctx, HOST_MDCR_EL2) &= ~MDCR_EL2_TDE;
sys/arm64/vmm/vmm_arm64.c
1413
if ((val != 0) == ((hypctx->setcaps & (1ul << num)) != 0))
sys/arm64/vmm/vmm_arm64.c
1417
hypctx->debug_spsr |= (hypctx_read_sys_reg(hypctx,
sys/arm64/vmm/vmm_arm64.c
1419
hypctx->debug_mdscr |= (hypctx_read_sys_reg(hypctx,
sys/arm64/vmm/vmm_arm64.c
1422
*hypctx_sys_reg(hypctx, HOST_SPSR_EL2) |= PSR_SS;
sys/arm64/vmm/vmm_arm64.c
1423
*hypctx_sys_reg(hypctx, MDSCR_EL1) |= MDSCR_SS;
sys/arm64/vmm/vmm_arm64.c
1424
*hypctx_sys_reg(hypctx, HOST_MDCR_EL2) |= MDCR_EL2_TDE;
sys/arm64/vmm/vmm_arm64.c
1426
*hypctx_sys_reg(hypctx, HOST_SPSR_EL2) &= ~PSR_SS;
sys/arm64/vmm/vmm_arm64.c
1427
*hypctx_sys_reg(hypctx,
sys/arm64/vmm/vmm_arm64.c
1428
HOST_SPSR_EL2) |= hypctx->debug_spsr;
sys/arm64/vmm/vmm_arm64.c
1429
hypctx->debug_spsr &= ~PSR_SS;
sys/arm64/vmm/vmm_arm64.c
1430
*hypctx_sys_reg(hypctx, MDSCR_EL1) &= ~MDSCR_SS;
sys/arm64/vmm/vmm_arm64.c
1431
*hypctx_sys_reg(hypctx,
sys/arm64/vmm/vmm_arm64.c
1432
MDSCR_EL1) |= hypctx->debug_mdscr;
sys/arm64/vmm/vmm_arm64.c
1433
hypctx->debug_mdscr &= ~MDSCR_SS;
sys/arm64/vmm/vmm_arm64.c
1434
if ((hypctx->setcaps & (1ul << VM_CAP_BRK_EXIT)) == 0)
sys/arm64/vmm/vmm_arm64.c
1435
*hypctx_sys_reg(hypctx,
sys/arm64/vmm/vmm_arm64.c
1440
if ((val != 0) == ((hypctx->setcaps & (1ul << num)) != 0))
sys/arm64/vmm/vmm_arm64.c
1443
host_spsr_el2 = hypctx_read_sys_reg(hypctx, HOST_SPSR_EL2);
sys/arm64/vmm/vmm_arm64.c
1445
hypctx->debug_spsr |= (host_spsr_el2 & (PSR_I | PSR_F));
sys/arm64/vmm/vmm_arm64.c
1449
host_spsr_el2 |= (hypctx->debug_spsr & (PSR_I | PSR_F));
sys/arm64/vmm/vmm_arm64.c
1450
hypctx->debug_spsr &= ~(PSR_I | PSR_F);
sys/arm64/vmm/vmm_arm64.c
1452
hypctx_write_sys_reg(hypctx, HOST_SPSR_EL2, host_spsr_el2);
sys/arm64/vmm/vmm_arm64.c
1461
hypctx->setcaps &= ~(1ul << num);
sys/arm64/vmm/vmm_arm64.c
1463
hypctx->setcaps |= (1ul << num);
sys/arm64/vmm/vmm_arm64.c
487
sizeof(struct hypctx *) * vm_get_maxcpus(vm)));
sys/arm64/vmm/vmm_arm64.c
494
return (round_page(sizeof(struct hypctx) + 2 * VNCR_PAGE_SIZE));
sys/arm64/vmm/vmm_arm64.c
559
struct hypctx *hypctx;
sys/arm64/vmm/vmm_arm64.c
569
hypctx = malloc_aligned(size, PAGE_SIZE, M_HYP, M_WAITOK | M_ZERO);
sys/arm64/vmm/vmm_arm64.c
570
_Static_assert(sizeof(struct hypctx) < VNCR_PAGE_SIZE,
sys/arm64/vmm/vmm_arm64.c
572
hypctx->vncr_regs = (void *)((char *)hypctx + VNCR_PAGE_SIZE);
sys/arm64/vmm/vmm_arm64.c
573
hypctx->host_vncr_regs = (void *)((char *)hypctx + 2 * VNCR_PAGE_SIZE);
sys/arm64/vmm/vmm_arm64.c
577
hyp->ctx[vcpuid] = hypctx;
sys/arm64/vmm/vmm_arm64.c
579
hypctx->hyp = hyp;
sys/arm64/vmm/vmm_arm64.c
580
hypctx->vcpu = vcpu1;
sys/arm64/vmm/vmm_arm64.c
582
reset_vm_el01_regs(hypctx);
sys/arm64/vmm/vmm_arm64.c
583
reset_vm_el2_regs(hypctx);
sys/arm64/vmm/vmm_arm64.c
585
vtimer_cpuinit(hypctx);
sys/arm64/vmm/vmm_arm64.c
586
vgic_cpuinit(hypctx);
sys/arm64/vmm/vmm_arm64.c
589
hypctx->el2_addr = el2_map_enter((vm_offset_t)hypctx, size,
sys/arm64/vmm/vmm_arm64.c
591
hypctx->el2_vncr_addr = hypctx->el2_addr + VNCR_PAGE_SIZE;
sys/arm64/vmm/vmm_arm64.c
592
hypctx->el2_host_vncr_addr = hypctx->el2_addr + 2 * VNCR_PAGE_SIZE;
sys/arm64/vmm/vmm_arm64.c
595
return (hypctx);
sys/arm64/vmm/vmm_arm64.c
630
arm64_gen_inst_emul_data(struct hypctx *hypctx, uint32_t esr_iss,
sys/arm64/vmm/vmm_arm64.c
641
HPFAR_EL2_FIPA_ADDR(hypctx_read_sys_reg(hypctx, HOST_HPFAR_EL2));
sys/arm64/vmm/vmm_arm64.c
643
vme_ret->u.inst_emul.gpa += hypctx_read_sys_reg(hypctx, HOST_FAR_EL2) &
sys/arm64/vmm/vmm_arm64.c
656
paging->ttbr0_addr = hypctx_read_sys_reg(hypctx, TTBR0_EL1) &
sys/arm64/vmm/vmm_arm64.c
658
paging->ttbr1_addr = hypctx_read_sys_reg(hypctx, TTBR1_EL1) &
sys/arm64/vmm/vmm_arm64.c
660
paging->tcr_el1 = hypctx_read_sys_reg(hypctx, TCR_EL1);
sys/arm64/vmm/vmm_arm64.c
661
paging->tcr2_el1 = hypctx_read_sys_reg(hypctx, TCR2_EL1);
sys/arm64/vmm/vmm_arm64.c
662
paging->flags = hypctx_read_sys_reg(hypctx, HOST_SPSR_EL2) & (PSR_M_MASK | PSR_M_32);
sys/arm64/vmm/vmm_arm64.c
663
if ((hypctx_read_sys_reg(hypctx, SCTLR_EL1) & SCTLR_M) != 0)
sys/arm64/vmm/vmm_arm64.c
684
raise_data_insn_abort(struct hypctx *hypctx, uint64_t far, bool dabort, int fsc)
sys/arm64/vmm/vmm_arm64.c
688
if ((hypctx_read_sys_reg(hypctx, HOST_SPSR_EL2) & PSR_M_MASK) == PSR_M_EL0t)
sys/arm64/vmm/vmm_arm64.c
696
esr |= hypctx_read_sys_reg(hypctx, HOST_ESR_EL2) & ESR_ELx_IL;
sys/arm64/vmm/vmm_arm64.c
698
vmmops_exception(hypctx, esr | fsc, far);
sys/arm64/vmm/vmm_arm64.c
702
handle_el1_sync_excp(struct hypctx *hypctx, struct vm_exit *vme_ret,
sys/arm64/vmm/vmm_arm64.c
708
esr_ec = ESR_ELx_EXCEPTION(hypctx_read_sys_reg(hypctx, HOST_ESR_EL2));
sys/arm64/vmm/vmm_arm64.c
709
esr_iss = hypctx_read_sys_reg(hypctx, HOST_ESR_EL2) & ESR_ELx_ISS_MASK;
sys/arm64/vmm/vmm_arm64.c
713
vmm_stat_incr(hypctx->vcpu, VMEXIT_UNKNOWN, 1);
sys/arm64/vmm/vmm_arm64.c
718
if ((hypctx_read_sys_reg(hypctx, HOST_ESR_EL2) & 0x3) == 0) { /* WFI */
sys/arm64/vmm/vmm_arm64.c
719
vmm_stat_incr(hypctx->vcpu, VMEXIT_WFI, 1);
sys/arm64/vmm/vmm_arm64.c
722
vmm_stat_incr(hypctx->vcpu, VMEXIT_WFE, 1);
sys/arm64/vmm/vmm_arm64.c
727
vmm_stat_incr(hypctx->vcpu, VMEXIT_HVC, 1);
sys/arm64/vmm/vmm_arm64.c
731
vmm_stat_incr(hypctx->vcpu, VMEXIT_MSR, 1);
sys/arm64/vmm/vmm_arm64.c
736
vmm_stat_incr(hypctx->vcpu, VMEXIT_BRK, 1);
sys/arm64/vmm/vmm_arm64.c
740
vmm_stat_incr(hypctx->vcpu, VMEXIT_SS, 1);
sys/arm64/vmm/vmm_arm64.c
745
vmm_stat_incr(hypctx->vcpu, esr_ec == EXCP_DATA_ABORT_L ?
sys/arm64/vmm/vmm_arm64.c
747
switch (hypctx_read_sys_reg(hypctx, HOST_ESR_EL2) & ISS_DATA_DFSC_MASK) {
sys/arm64/vmm/vmm_arm64.c
758
gpa = HPFAR_EL2_FIPA_ADDR(hypctx_read_sys_reg(hypctx, HOST_HPFAR_EL2));
sys/arm64/vmm/vmm_arm64.c
761
raise_data_insn_abort(hypctx,
sys/arm64/vmm/vmm_arm64.c
762
hypctx_read_sys_reg(hypctx, HOST_FAR_EL2),
sys/arm64/vmm/vmm_arm64.c
769
if (vm_mem_allocated(hypctx->vcpu, gpa)) {
sys/arm64/vmm/vmm_arm64.c
772
vme_ret->u.paging.esr = hypctx_read_sys_reg(hypctx, HOST_ESR_EL2);
sys/arm64/vmm/vmm_arm64.c
779
raise_data_insn_abort(hypctx,
sys/arm64/vmm/vmm_arm64.c
780
hypctx_read_sys_reg(hypctx, HOST_FAR_EL2), false,
sys/arm64/vmm/vmm_arm64.c
785
arm64_gen_inst_emul_data(hypctx, esr_iss,
sys/arm64/vmm/vmm_arm64.c
799
vmm_stat_incr(hypctx->vcpu, VMEXIT_UNHANDLED_SYNC, 1);
sys/arm64/vmm/vmm_arm64.c
810
arm64_handle_world_switch(struct hypctx *hypctx, int excp_type,
sys/arm64/vmm/vmm_arm64.c
818
handled = handle_el1_sync_excp(hypctx, vme, pmap);
sys/arm64/vmm/vmm_arm64.c
824
vmm_stat_incr(hypctx->vcpu,
sys/arm64/vmm/vmm_arm64.c
835
vmm_stat_incr(hypctx->vcpu, VMEXIT_UNHANDLED_EL2, 1);
sys/arm64/vmm/vmm_arm64.c
841
vmm_stat_incr(hypctx->vcpu, VMEXIT_UNHANDLED, 1);
sys/arm64/vmm/vmm_arm64.c
875
struct hypctx *hypctx;
sys/arm64/vmm/vmm_handlers.c
52
vmm_nvhe_enter_guest(struct hyp *hyp, struct hypctx *hypctx)
sys/arm64/vmm/vmm_handlers.c
54
return (vmm_call_hyp(HYP_ENTER_GUEST, hyp->el2_addr, hypctx->el2_addr));
sys/arm64/vmm/vmm_handlers.c
58
(struct hyp *hyp, struct hypctx *hypctx))
sys/arm64/vmm/vmm_handlers.h
34
struct hypctx;
sys/arm64/vmm/vmm_handlers.h
37
uint64_t vmm_enter_guest(struct hyp *, struct hypctx *);
sys/arm64/vmm/vmm_handlers.h
43
uint64_t vmm_vhe_enter_guest(struct hyp *, struct hypctx *);
sys/arm64/vmm/vmm_hyp.c
106
hypctx_write_sys_reg(hypctx, PMCR_EL0,
sys/arm64/vmm/vmm_hyp.c
108
hypctx_write_sys_reg(hypctx, PMCCNTR_EL0,
sys/arm64/vmm/vmm_hyp.c
110
hypctx_write_sys_reg(hypctx, PMCCFILTR_EL0,
sys/arm64/vmm/vmm_hyp.c
112
hypctx_write_sys_reg(hypctx, PMUSERENR_EL0,
sys/arm64/vmm/vmm_hyp.c
114
hypctx_write_sys_reg(hypctx, PMSELR_EL0,
sys/arm64/vmm/vmm_hyp.c
116
hypctx_write_sys_reg(hypctx, PMXEVCNTR_EL0,
sys/arm64/vmm/vmm_hyp.c
118
hypctx_write_sys_reg(hypctx, PMCNTENSET_EL0,
sys/arm64/vmm/vmm_hyp.c
120
hypctx_write_sys_reg(hypctx, PMINTENSET_EL1,
sys/arm64/vmm/vmm_hyp.c
122
hypctx_write_sys_reg(hypctx, PMOVSSET_EL0,
sys/arm64/vmm/vmm_hyp.c
125
switch ((hypctx_read_sys_reg(hypctx, PMCR_EL0) & PMCR_N_MASK) >>
sys/arm64/vmm/vmm_hyp.c
129
hypctx_write_sys_reg(hypctx, PMEVCNTR_EL0(x), \
sys/arm64/vmm/vmm_hyp.c
131
hypctx_write_sys_reg(hypctx, PMEVTYPER_EL0(x), \
sys/arm64/vmm/vmm_hyp.c
170
hypctx_write_sys_reg(hypctx, HOST_MDCR_EL2,
sys/arm64/vmm/vmm_hyp.c
175
vmm_hyp_reg_store_vgic(struct hypctx *hypctx, bool guest)
sys/arm64/vmm/vmm_hyp.c
177
hypctx_write_sys_reg(hypctx, HOST_ICH_HCR_EL2,
sys/arm64/vmm/vmm_hyp.c
179
hypctx_write_sys_reg(hypctx, HOST_ICH_VMCR_EL2,
sys/arm64/vmm/vmm_hyp.c
186
hypctx_write_sys_reg(hypctx, HOST_ICH_EISR_EL2,
sys/arm64/vmm/vmm_hyp.c
188
hypctx_write_sys_reg(hypctx, HOST_ICH_ELRSR_EL2,
sys/arm64/vmm/vmm_hyp.c
190
hypctx_write_sys_reg(hypctx, HOST_ICH_MISR_EL2,
sys/arm64/vmm/vmm_hyp.c
193
switch (hypctx->vgic_v3.ich_lr_num - 1) {
sys/arm64/vmm/vmm_hyp.c
196
hypctx_write_sys_reg(hypctx, HOST_ICH_LR_EL2(x), \
sys/arm64/vmm/vmm_hyp.c
218
switch (hypctx->vgic_v3.ich_apr_num - 1) {
sys/arm64/vmm/vmm_hyp.c
221
hypctx_write_sys_reg(hypctx, HOST_ICH_AP0R_EL2(x), \
sys/arm64/vmm/vmm_hyp.c
223
hypctx_write_sys_reg(hypctx, HOST_ICH_AP1R_EL2(x), \
sys/arm64/vmm/vmm_hyp.c
235
vmm_hyp_reg_store_timer(struct hypctx *hypctx, struct hyp *hyp, bool guest)
sys/arm64/vmm/vmm_hyp.c
241
hypctx->vtimer_cpu.cntkctl_el1 =
sys/arm64/vmm/vmm_hyp.c
243
hypctx->vtimer_cpu.virt_timer.cntx_cval_el0 =
sys/arm64/vmm/vmm_hyp.c
245
hypctx->vtimer_cpu.virt_timer.cntx_ctl_el0 =
sys/arm64/vmm/vmm_hyp.c
248
hypctx->vtimer_cpu.cntkctl_el1 =
sys/arm64/vmm/vmm_hyp.c
250
hypctx_write_sys_reg(hypctx, HOST_CNTHCTL_EL2,
sys/arm64/vmm/vmm_hyp.c
252
hypctx_write_sys_reg(hypctx, HOST_CNTVOFF_EL2,
sys/arm64/vmm/vmm_hyp.c
256
ecv_poff = (hypctx_read_sys_reg(hypctx, HOST_CNTHCTL_EL2) &
sys/arm64/vmm/vmm_hyp.c
265
hypctx->vtimer_cpu.phys_timer.cntx_cval_el0 =
sys/arm64/vmm/vmm_hyp.c
267
hypctx->vtimer_cpu.phys_timer.cntx_ctl_el0 =
sys/arm64/vmm/vmm_hyp.c
273
vmm_hyp_reg_store_special(struct hypctx *hypctx, struct hyp *hyp, bool guest)
sys/arm64/vmm/vmm_hyp.c
276
hypctx_write_sys_reg(hypctx, HOST_SP_EL1, READ_SPECIALREG(sp_el1));
sys/arm64/vmm/vmm_hyp.c
277
hypctx_write_sys_reg(hypctx, HOST_ELR_EL2, READ_SPECIALREG(elr_el2));
sys/arm64/vmm/vmm_hyp.c
278
hypctx_write_sys_reg(hypctx, HOST_SPSR_EL2, READ_SPECIALREG(spsr_el2));
sys/arm64/vmm/vmm_hyp.c
281
hypctx_write_sys_reg(hypctx, HOST_ESR_EL2,
sys/arm64/vmm/vmm_hyp.c
283
hypctx_write_sys_reg(hypctx, HOST_FAR_EL2,
sys/arm64/vmm/vmm_hyp.c
285
hypctx_write_sys_reg(hypctx, PAR_EL1,
sys/arm64/vmm/vmm_hyp.c
290
hypctx_write_sys_reg(hypctx, SP_EL0, READ_SPECIALREG(sp_el0));
sys/arm64/vmm/vmm_hyp.c
291
hypctx_write_sys_reg(hypctx, TPIDR_EL0, READ_SPECIALREG(tpidr_el0));
sys/arm64/vmm/vmm_hyp.c
292
hypctx_write_sys_reg(hypctx, TPIDRRO_EL0, READ_SPECIALREG(tpidrro_el0));
sys/arm64/vmm/vmm_hyp.c
293
hypctx_write_sys_reg(hypctx, TPIDR_EL1, READ_SPECIALREG(tpidr_el1));
sys/arm64/vmm/vmm_hyp.c
295
hypctx_write_sys_reg(hypctx, ACTLR_EL1, READ_SPECIALREG(actlr_el1));
sys/arm64/vmm/vmm_hyp.c
296
hypctx_write_sys_reg(hypctx, CSSELR_EL1, READ_SPECIALREG(csselr_el1));
sys/arm64/vmm/vmm_hyp.c
297
hypctx_write_sys_reg(hypctx, MDCCINT_EL1, READ_SPECIALREG(mdccint_el1));
sys/arm64/vmm/vmm_hyp.c
298
hypctx_write_sys_reg(hypctx, MDSCR_EL1, READ_SPECIALREG(mdscr_el1));
sys/arm64/vmm/vmm_hyp.c
301
hypctx_write_sys_reg(hypctx, ELR_EL1,
sys/arm64/vmm/vmm_hyp.c
303
hypctx_write_sys_reg(hypctx, VBAR_EL1,
sys/arm64/vmm/vmm_hyp.c
305
hypctx_write_sys_reg(hypctx, AFSR0_EL1,
sys/arm64/vmm/vmm_hyp.c
307
hypctx_write_sys_reg(hypctx, AFSR1_EL1,
sys/arm64/vmm/vmm_hyp.c
309
hypctx_write_sys_reg(hypctx, AMAIR_EL1,
sys/arm64/vmm/vmm_hyp.c
311
hypctx_write_sys_reg(hypctx, CONTEXTIDR_EL1,
sys/arm64/vmm/vmm_hyp.c
313
hypctx_write_sys_reg(hypctx, CPACR_EL1,
sys/arm64/vmm/vmm_hyp.c
315
hypctx_write_sys_reg(hypctx, ESR_EL1,
sys/arm64/vmm/vmm_hyp.c
317
hypctx_write_sys_reg(hypctx, FAR_EL1,
sys/arm64/vmm/vmm_hyp.c
319
hypctx_write_sys_reg(hypctx, MAIR_EL1,
sys/arm64/vmm/vmm_hyp.c
321
hypctx_write_sys_reg(hypctx, SCTLR_EL1,
sys/arm64/vmm/vmm_hyp.c
323
hypctx_write_sys_reg(hypctx, SPSR_EL1,
sys/arm64/vmm/vmm_hyp.c
325
hypctx_write_sys_reg(hypctx, TCR_EL1,
sys/arm64/vmm/vmm_hyp.c
328
hypctx_write_sys_reg(hypctx, TCR2_EL1, 0);
sys/arm64/vmm/vmm_hyp.c
329
hypctx_write_sys_reg(hypctx, TTBR0_EL1,
sys/arm64/vmm/vmm_hyp.c
331
hypctx_write_sys_reg(hypctx, TTBR1_EL1,
sys/arm64/vmm/vmm_hyp.c
335
hypctx_write_sys_reg(hypctx, HOST_CPTR_EL2,
sys/arm64/vmm/vmm_hyp.c
337
hypctx_write_sys_reg(hypctx, HOST_HCR_EL2,
sys/arm64/vmm/vmm_hyp.c
339
hypctx_write_sys_reg(hypctx, HOST_VPIDR_EL2,
sys/arm64/vmm/vmm_hyp.c
341
hypctx_write_sys_reg(hypctx, HOST_VMPIDR_EL2,
sys/arm64/vmm/vmm_hyp.c
346
hypctx_write_sys_reg(hypctx, HOST_HCRX_EL2,
sys/arm64/vmm/vmm_hyp.c
353
vmm_hyp_reg_restore_special(struct hypctx *hypctx, struct hyp *hyp, bool guest)
sys/arm64/vmm/vmm_hyp.c
355
WRITE_SPECIALREG(hcr_el2, hypctx_read_sys_reg(hypctx, HOST_HCR_EL2));
sys/arm64/vmm/vmm_hyp.c
359
hypctx_read_sys_reg(hypctx, HOST_HCRX_EL2));
sys/arm64/vmm/vmm_hyp.c
369
hypctx_read_sys_reg(hypctx, HOST_HDFGWTR_EL2));
sys/arm64/vmm/vmm_hyp.c
371
hypctx_read_sys_reg(hypctx, HOST_HFGITR_EL2));
sys/arm64/vmm/vmm_hyp.c
373
hypctx_read_sys_reg(hypctx, HOST_HFGRTR_EL2));
sys/arm64/vmm/vmm_hyp.c
375
hypctx_read_sys_reg(hypctx, HOST_HFGWTR_EL2));
sys/arm64/vmm/vmm_hyp.c
380
hypctx_read_sys_reg(hypctx, HOST_HDFGRTR2_EL2));
sys/arm64/vmm/vmm_hyp.c
382
hypctx_read_sys_reg(hypctx, HOST_HDFGWTR2_EL2));
sys/arm64/vmm/vmm_hyp.c
384
hypctx_read_sys_reg(hypctx, HOST_HFGITR2_EL2));
sys/arm64/vmm/vmm_hyp.c
386
hypctx_read_sys_reg(hypctx, HOST_HFGRTR2_EL2));
sys/arm64/vmm/vmm_hyp.c
388
hypctx_read_sys_reg(hypctx, HOST_HFGWTR2_EL2));
sys/arm64/vmm/vmm_hyp.c
39
struct hypctx;
sys/arm64/vmm/vmm_hyp.c
393
WRITE_SPECIALREG(sp_el0, hypctx_read_sys_reg(hypctx, SP_EL0));
sys/arm64/vmm/vmm_hyp.c
394
WRITE_SPECIALREG(tpidr_el0, hypctx_read_sys_reg(hypctx, TPIDR_EL0));
sys/arm64/vmm/vmm_hyp.c
395
WRITE_SPECIALREG(tpidrro_el0, hypctx_read_sys_reg(hypctx, TPIDRRO_EL0));
sys/arm64/vmm/vmm_hyp.c
396
WRITE_SPECIALREG(tpidr_el1, hypctx_read_sys_reg(hypctx, TPIDR_EL1));
sys/arm64/vmm/vmm_hyp.c
398
WRITE_SPECIALREG(actlr_el1, hypctx_read_sys_reg(hypctx, ACTLR_EL1));
sys/arm64/vmm/vmm_hyp.c
399
WRITE_SPECIALREG(csselr_el1, hypctx_read_sys_reg(hypctx, CSSELR_EL1));
sys/arm64/vmm/vmm_hyp.c
400
WRITE_SPECIALREG(mdccint_el1, hypctx_read_sys_reg(hypctx, MDCCINT_EL1));
sys/arm64/vmm/vmm_hyp.c
401
WRITE_SPECIALREG(mdscr_el1, hypctx_read_sys_reg(hypctx, MDSCR_EL1));
sys/arm64/vmm/vmm_hyp.c
405
hypctx_read_sys_reg(hypctx, ELR_EL1));
sys/arm64/vmm/vmm_hyp.c
407
hypctx_read_sys_reg(hypctx, VBAR_EL1));
sys/arm64/vmm/vmm_hyp.c
409
hypctx_read_sys_reg(hypctx, AFSR0_EL1));
sys/arm64/vmm/vmm_hyp.c
41
uint64_t VMM_HYP_FUNC(do_call_guest)(struct hypctx *);
sys/arm64/vmm/vmm_hyp.c
411
hypctx_read_sys_reg(hypctx, AFSR1_EL1));
sys/arm64/vmm/vmm_hyp.c
413
hypctx_read_sys_reg(hypctx, AMAIR_EL1));
sys/arm64/vmm/vmm_hyp.c
415
hypctx_read_sys_reg(hypctx, CONTEXTIDR_EL1));
sys/arm64/vmm/vmm_hyp.c
417
hypctx_read_sys_reg(hypctx, CPACR_EL1));
sys/arm64/vmm/vmm_hyp.c
419
hypctx_read_sys_reg(hypctx, ESR_EL1));
sys/arm64/vmm/vmm_hyp.c
421
hypctx_read_sys_reg(hypctx, FAR_EL1));
sys/arm64/vmm/vmm_hyp.c
423
hypctx_read_sys_reg(hypctx, MAIR_EL1));
sys/arm64/vmm/vmm_hyp.c
425
hypctx_read_sys_reg(hypctx, SCTLR_EL1));
sys/arm64/vmm/vmm_hyp.c
427
hypctx_read_sys_reg(hypctx, SPSR_EL1));
sys/arm64/vmm/vmm_hyp.c
429
hypctx_read_sys_reg(hypctx, TCR_EL1));
sys/arm64/vmm/vmm_hyp.c
432
hypctx_read_sys_reg(hypctx, TTBR0_EL1));
sys/arm64/vmm/vmm_hyp.c
434
hypctx_read_sys_reg(hypctx, TTBR1_EL1));
sys/arm64/vmm/vmm_hyp.c
438
WRITE_SPECIALREG(par_el1, hypctx_read_sys_reg(hypctx, PAR_EL1));
sys/arm64/vmm/vmm_hyp.c
44
vmm_hyp_reg_store_pmu_debug(struct hypctx *hypctx, bool guest)
sys/arm64/vmm/vmm_hyp.c
442
hypctx_read_sys_reg(hypctx, HOST_CPTR_EL2));
sys/arm64/vmm/vmm_hyp.c
444
hypctx_read_sys_reg(hypctx, HOST_VPIDR_EL2));
sys/arm64/vmm/vmm_hyp.c
446
hypctx_read_sys_reg(hypctx, HOST_VMPIDR_EL2));
sys/arm64/vmm/vmm_hyp.c
449
WRITE_SPECIALREG(sp_el1, hypctx_read_sys_reg(hypctx, HOST_SP_EL1));
sys/arm64/vmm/vmm_hyp.c
450
WRITE_SPECIALREG(elr_el2, hypctx_read_sys_reg(hypctx, HOST_ELR_EL2));
sys/arm64/vmm/vmm_hyp.c
451
WRITE_SPECIALREG(spsr_el2, hypctx_read_sys_reg(hypctx, HOST_SPSR_EL2));
sys/arm64/vmm/vmm_hyp.c
455
vmm_hyp_reg_restore_pmu_debug(struct hypctx *hypctx)
sys/arm64/vmm/vmm_hyp.c
461
hypctx_read_sys_reg(hypctx, PMCR_EL0));
sys/arm64/vmm/vmm_hyp.c
463
hypctx_read_sys_reg(hypctx, PMCCNTR_EL0));
sys/arm64/vmm/vmm_hyp.c
465
hypctx_read_sys_reg(hypctx, PMCCFILTR_EL0));
sys/arm64/vmm/vmm_hyp.c
467
hypctx_read_sys_reg(hypctx, PMUSERENR_EL0));
sys/arm64/vmm/vmm_hyp.c
469
hypctx_read_sys_reg(hypctx, PMSELR_EL0));
sys/arm64/vmm/vmm_hyp.c
47
hypctx_write_sys_reg(hypctx, DBGCLAIMSET_EL1,
sys/arm64/vmm/vmm_hyp.c
471
hypctx_read_sys_reg(hypctx, PMXEVCNTR_EL0));
sys/arm64/vmm/vmm_hyp.c
475
hypctx_read_sys_reg(hypctx, PMCNTENSET_EL0));
sys/arm64/vmm/vmm_hyp.c
478
hypctx_read_sys_reg(hypctx, PMINTENSET_EL1));
sys/arm64/vmm/vmm_hyp.c
481
hypctx_read_sys_reg(hypctx, PMOVSSET_EL0));
sys/arm64/vmm/vmm_hyp.c
483
switch ((hypctx_read_sys_reg(hypctx, PMCR_EL0) & PMCR_N_MASK) >>
sys/arm64/vmm/vmm_hyp.c
488
hypctx_read_sys_reg(hypctx, PMEVCNTR_EL0(x))); \
sys/arm64/vmm/vmm_hyp.c
490
hypctx_read_sys_reg(hypctx, PMEVTYPER_EL0(x)))
sys/arm64/vmm/vmm_hyp.c
529
hypctx_read_sys_reg(hypctx, DBGCLAIMSET_EL1));
sys/arm64/vmm/vmm_hyp.c
536
hypctx_read_sys_reg(hypctx, DBGBCR_EL1(x))); \
sys/arm64/vmm/vmm_hyp.c
538
hypctx_read_sys_reg(hypctx, DBGBVR_EL1(x)))
sys/arm64/vmm/vmm_hyp.c
54
hypctx_write_sys_reg(hypctx, DBGBCR_EL1(x), \
sys/arm64/vmm/vmm_hyp.c
56
hypctx_write_sys_reg(hypctx, DBGBVR_EL1(x), \
sys/arm64/vmm/vmm_hyp.c
563
hypctx_read_sys_reg(hypctx, DBGWCR_EL1(x))); \
sys/arm64/vmm/vmm_hyp.c
565
hypctx_read_sys_reg(hypctx, DBGWVR_EL1(x)))
sys/arm64/vmm/vmm_hyp.c
588
vmm_hyp_reg_restore_timer(struct hypctx *hypctx, struct hyp *hyp, bool guest)
sys/arm64/vmm/vmm_hyp.c
591
ecv_poff = (hypctx_read_sys_reg(hypctx, HOST_CNTHCTL_EL2) &
sys/arm64/vmm/vmm_hyp.c
595
hypctx_read_sys_reg(hypctx, HOST_CNTHCTL_EL2));
sys/arm64/vmm/vmm_hyp.c
597
hypctx_read_sys_reg(hypctx, HOST_CNTVOFF_EL2));
sys/arm64/vmm/vmm_hyp.c
601
hypctx->vtimer_cpu.cntkctl_el1);
sys/arm64/vmm/vmm_hyp.c
603
hypctx->vtimer_cpu.virt_timer.cntx_cval_el0);
sys/arm64/vmm/vmm_hyp.c
605
hypctx->vtimer_cpu.virt_timer.cntx_ctl_el0);
sys/arm64/vmm/vmm_hyp.c
613
hypctx_read_sys_reg(hypctx, HOST_CNTVOFF_EL2));
sys/arm64/vmm/vmm_hyp.c
617
WRITE_SPECIALREG(cntkctl_el1, hypctx->vtimer_cpu.cntkctl_el1);
sys/arm64/vmm/vmm_hyp.c
626
hypctx->vtimer_cpu.phys_timer.cntx_cval_el0);
sys/arm64/vmm/vmm_hyp.c
628
hypctx->vtimer_cpu.phys_timer.cntx_ctl_el0);
sys/arm64/vmm/vmm_hyp.c
633
vmm_hyp_reg_restore_vgic(struct hypctx *hypctx, bool guest)
sys/arm64/vmm/vmm_hyp.c
637
hypctx_read_sys_reg(hypctx, HOST_ICH_HCR_EL2));
sys/arm64/vmm/vmm_hyp.c
639
hypctx_read_sys_reg(hypctx, HOST_ICH_VMCR_EL2));
sys/arm64/vmm/vmm_hyp.c
644
switch (hypctx->vgic_v3.ich_lr_num - 1) {
sys/arm64/vmm/vmm_hyp.c
648
hypctx_read_sys_reg(hypctx, HOST_ICH_LR_EL2(x)))
sys/arm64/vmm/vmm_hyp.c
669
switch (hypctx->vgic_v3.ich_apr_num - 1) {
sys/arm64/vmm/vmm_hyp.c
673
hypctx_read_sys_reg(hypctx, HOST_ICH_AP0R_EL2(x))); \
sys/arm64/vmm/vmm_hyp.c
675
hypctx_read_sys_reg(hypctx, HOST_ICH_AP1R_EL2(x)))
sys/arm64/vmm/vmm_hyp.c
686
vmm_hyp_reg_store(struct hypctx *hypctx, struct hyp *hyp, bool guest)
sys/arm64/vmm/vmm_hyp.c
688
vmm_hyp_reg_store_vgic(hypctx, guest);
sys/arm64/vmm/vmm_hyp.c
689
vmm_hyp_reg_store_timer(hypctx, hyp, guest);
sys/arm64/vmm/vmm_hyp.c
690
vmm_hyp_reg_store_pmu_debug(hypctx, guest);
sys/arm64/vmm/vmm_hyp.c
691
vmm_hyp_reg_store_special(hypctx, hyp, guest);
sys/arm64/vmm/vmm_hyp.c
695
vmm_hyp_reg_restore(struct hypctx *hypctx, struct hyp *hyp, bool guest)
sys/arm64/vmm/vmm_hyp.c
697
vmm_hyp_reg_restore_special(hypctx, hyp, guest);
sys/arm64/vmm/vmm_hyp.c
698
vmm_hyp_reg_restore_pmu_debug(hypctx);
sys/arm64/vmm/vmm_hyp.c
699
vmm_hyp_reg_restore_timer(hypctx, hyp, guest);
sys/arm64/vmm/vmm_hyp.c
700
vmm_hyp_reg_restore_vgic(hypctx, guest);
sys/arm64/vmm/vmm_hyp.c
704
vmm_hyp_handle_guest_exit(struct hypctx *hypctx, uint64_t *ret)
sys/arm64/vmm/vmm_hyp.c
710
host_esr_el2 = hypctx_read_sys_reg(hypctx, HOST_ESR_EL2);
sys/arm64/vmm/vmm_hyp.c
741
hypctx_write_sys_reg(hypctx, HOST_HPFAR_EL2,
sys/arm64/vmm/vmm_hyp.c
748
host_far_el2 = hypctx_read_sys_reg(hypctx, HOST_FAR_EL2);
sys/arm64/vmm/vmm_hyp.c
753
hypctx_write_sys_reg(hypctx, HOST_HPFAR_EL2, hpfar_el2);
sys/arm64/vmm/vmm_hyp.c
762
__vmm_hyp_call_guest(struct hypctx *hypctx, struct hypctx *host_hypctx)
sys/arm64/vmm/vmm_hyp.c
765
WRITE_SPECIALREG(vttbr_el2, hypctx_read_sys_reg(hypctx, HOST_VTTBR_EL2));
sys/arm64/vmm/vmm_hyp.c
766
WRITE_SPECIALREG(mdcr_el2, hypctx_read_sys_reg(hypctx, HOST_MDCR_EL2));
sys/arm64/vmm/vmm_hyp.c
768
ret = VMM_HYP_FUNC(do_call_guest)(hypctx);
sys/arm64/vmm/vmm_hyp.c
777
vmm_hyp_call_guest(struct hyp *hyp, struct hypctx *hypctx)
sys/arm64/vmm/vmm_hyp.c
779
struct hypctx host_hypctx;
sys/arm64/vmm/vmm_hyp.c
783
host_hypctx.vncr_regs = hypctx->host_vncr_regs;
sys/arm64/vmm/vmm_hyp.c
785
host_hypctx.el2_vncr_addr = hypctx->el2_host_vncr_addr;
sys/arm64/vmm/vmm_hyp.c
789
vmm_hyp_reg_restore(hypctx, hyp, true);
sys/arm64/vmm/vmm_hyp.c
791
ret = __vmm_hyp_call_guest(hypctx, &host_hypctx);
sys/arm64/vmm/vmm_hyp.c
793
vmm_hyp_reg_store(hypctx, hyp, true);
sys/arm64/vmm/vmm_hyp.c
794
vmm_hyp_handle_guest_exit(hypctx, &ret);
sys/arm64/vmm/vmm_hyp.c
801
VMM_HYP_FUNC(enter_guest)(struct hyp *hyp, struct hypctx *hypctx)
sys/arm64/vmm/vmm_hyp.c
806
ret = vmm_hyp_call_guest(hyp, hypctx);
sys/arm64/vmm/vmm_hyp.c
81
hypctx_write_sys_reg(hypctx, DBGWCR_EL1(x), \
sys/arm64/vmm/vmm_hyp.c
83
hypctx_write_sys_reg(hypctx, DBGWVR_EL1(x), \
sys/arm64/vmm/vmm_nvhe.c
39
#define __hypctx_vncr_sysreg(hypctx, reg) \
sys/arm64/vmm/vmm_nvhe.c
40
((uint64_t*)(hypctx->el2_vncr_addr + REG_VNCR_OFFSET(reg)))
sys/arm64/vmm/vmm_nvhe.c
99
(struct hypctx *)x2));
sys/arm64/vmm/vmm_reset.c
52
struct hypctx *el2ctx;
sys/arm64/vmm/vmm_reset.c
75
struct hypctx *el2ctx;
sys/riscv/riscv/genassym.c
102
ASSYM(HYP_H_RA, offsetof(struct hypctx, host_regs.hyp_ra));
sys/riscv/riscv/genassym.c
103
ASSYM(HYP_H_SP, offsetof(struct hypctx, host_regs.hyp_sp));
sys/riscv/riscv/genassym.c
104
ASSYM(HYP_H_GP, offsetof(struct hypctx, host_regs.hyp_gp));
sys/riscv/riscv/genassym.c
105
ASSYM(HYP_H_TP, offsetof(struct hypctx, host_regs.hyp_tp));
sys/riscv/riscv/genassym.c
106
ASSYM(HYP_H_T, offsetof(struct hypctx, host_regs.hyp_t));
sys/riscv/riscv/genassym.c
107
ASSYM(HYP_H_S, offsetof(struct hypctx, host_regs.hyp_s));
sys/riscv/riscv/genassym.c
108
ASSYM(HYP_H_A, offsetof(struct hypctx, host_regs.hyp_a));
sys/riscv/riscv/genassym.c
109
ASSYM(HYP_H_SEPC, offsetof(struct hypctx, host_regs.hyp_sepc));
sys/riscv/riscv/genassym.c
110
ASSYM(HYP_H_SSTATUS, offsetof(struct hypctx, host_regs.hyp_sstatus));
sys/riscv/riscv/genassym.c
111
ASSYM(HYP_H_HSTATUS, offsetof(struct hypctx, host_regs.hyp_hstatus));
sys/riscv/riscv/genassym.c
112
ASSYM(HYP_H_SSCRATCH, offsetof(struct hypctx, host_sscratch));
sys/riscv/riscv/genassym.c
113
ASSYM(HYP_H_STVEC, offsetof(struct hypctx, host_stvec));
sys/riscv/riscv/genassym.c
114
ASSYM(HYP_H_SCOUNTEREN, offsetof(struct hypctx, host_scounteren));
sys/riscv/riscv/genassym.c
116
ASSYM(HYP_G_RA, offsetof(struct hypctx, guest_regs.hyp_ra));
sys/riscv/riscv/genassym.c
117
ASSYM(HYP_G_SP, offsetof(struct hypctx, guest_regs.hyp_sp));
sys/riscv/riscv/genassym.c
118
ASSYM(HYP_G_GP, offsetof(struct hypctx, guest_regs.hyp_gp));
sys/riscv/riscv/genassym.c
119
ASSYM(HYP_G_TP, offsetof(struct hypctx, guest_regs.hyp_tp));
sys/riscv/riscv/genassym.c
120
ASSYM(HYP_G_T, offsetof(struct hypctx, guest_regs.hyp_t));
sys/riscv/riscv/genassym.c
121
ASSYM(HYP_G_S, offsetof(struct hypctx, guest_regs.hyp_s));
sys/riscv/riscv/genassym.c
122
ASSYM(HYP_G_A, offsetof(struct hypctx, guest_regs.hyp_a));
sys/riscv/riscv/genassym.c
123
ASSYM(HYP_G_SEPC, offsetof(struct hypctx, guest_regs.hyp_sepc));
sys/riscv/riscv/genassym.c
124
ASSYM(HYP_G_SSTATUS, offsetof(struct hypctx, guest_regs.hyp_sstatus));
sys/riscv/riscv/genassym.c
125
ASSYM(HYP_G_HSTATUS, offsetof(struct hypctx, guest_regs.hyp_hstatus));
sys/riscv/riscv/genassym.c
126
ASSYM(HYP_G_SCOUNTEREN, offsetof(struct hypctx, guest_scounteren));
sys/riscv/vmm/riscv.h
114
struct hypctx *ctx[];
sys/riscv/vmm/riscv.h
127
struct hypctx *riscv_get_active_vcpu(void);
sys/riscv/vmm/riscv.h
128
void vmm_switch(struct hypctx *);
sys/riscv/vmm/riscv.h
133
int riscv_check_ipi(struct hypctx *hypctx, bool clear);
sys/riscv/vmm/riscv.h
134
bool riscv_check_interrupts_pending(struct hypctx *hypctx);
sys/riscv/vmm/vmm_aplic.c
330
struct hypctx *hypctx;
sys/riscv/vmm/vmm_aplic.c
337
hypctx = vcpu_get_cookie(vcpu);
sys/riscv/vmm/vmm_aplic.c
338
hyp = hypctx->hyp;
sys/riscv/vmm/vmm_aplic.c
359
struct hypctx *hypctx;
sys/riscv/vmm/vmm_aplic.c
366
hypctx = vcpu_get_cookie(vcpu);
sys/riscv/vmm/vmm_aplic.c
367
hyp = hypctx->hyp;
sys/riscv/vmm/vmm_aplic.c
450
aplic_check_pending(struct hypctx *hypctx)
sys/riscv/vmm/vmm_aplic.c
457
hyp = hypctx->hyp;
sys/riscv/vmm/vmm_aplic.c
468
if (irq->target_hart != hypctx->cpu_id)
sys/riscv/vmm/vmm_aplic.c
560
aplic_cpuinit(struct hypctx *hypctx)
sys/riscv/vmm/vmm_aplic.c
566
aplic_cpucleanup(struct hypctx *hypctx)
sys/riscv/vmm/vmm_aplic.c
572
aplic_flush_hwstate(struct hypctx *hypctx)
sys/riscv/vmm/vmm_aplic.c
578
aplic_sync_hwstate(struct hypctx *hypctx)
sys/riscv/vmm/vmm_aplic.h
37
struct hypctx;
sys/riscv/vmm/vmm_aplic.h
46
int aplic_check_pending(struct hypctx *hypctx);
sys/riscv/vmm/vmm_aplic.h
48
void aplic_cpuinit(struct hypctx *hypctx);
sys/riscv/vmm/vmm_aplic.h
49
void aplic_cpucleanup(struct hypctx *hypctx);
sys/riscv/vmm/vmm_aplic.h
50
void aplic_flush_hwstate(struct hypctx *hypctx);
sys/riscv/vmm/vmm_aplic.h
51
void aplic_sync_hwstate(struct hypctx *hypctx);
sys/riscv/vmm/vmm_fence.c
124
vmm_fence_process(struct hypctx *hypctx)
sys/riscv/vmm/vmm_fence.c
129
pending = atomic_readandclear_32(&hypctx->fence_req);
sys/riscv/vmm/vmm_fence.c
140
while (vmm_fence_dequeue(hypctx, &fence) == true)
sys/riscv/vmm/vmm_fence.c
147
struct hypctx *hypctx;
sys/riscv/vmm/vmm_fence.c
162
hypctx = vcpu_get_cookie(vcpu);
sys/riscv/vmm/vmm_fence.c
169
atomic_set_32(&hypctx->fence_req, FENCE_REQ_I);
sys/riscv/vmm/vmm_fence.c
174
atomic_set_32(&hypctx->fence_req,
sys/riscv/vmm/vmm_fence.c
193
if (vmm_fence_enqueue(hypctx, fence) == false)
sys/riscv/vmm/vmm_fence.c
194
atomic_set_32(&hypctx->fence_req,
sys/riscv/vmm/vmm_fence.c
50
vmm_fence_dequeue(struct hypctx *hypctx, struct vmm_fence *new_fence)
sys/riscv/vmm/vmm_fence.c
55
mtx_lock_spin(&hypctx->fence_queue_mtx);
sys/riscv/vmm/vmm_fence.c
56
queue = hypctx->fence_queue;
sys/riscv/vmm/vmm_fence.c
57
fence = &queue[hypctx->fence_queue_head];
sys/riscv/vmm/vmm_fence.c
61
hypctx->fence_queue_head =
sys/riscv/vmm/vmm_fence.c
62
(hypctx->fence_queue_head + 1) % VMM_FENCE_QUEUE_SIZE;
sys/riscv/vmm/vmm_fence.c
64
mtx_unlock_spin(&hypctx->fence_queue_mtx);
sys/riscv/vmm/vmm_fence.c
67
mtx_unlock_spin(&hypctx->fence_queue_mtx);
sys/riscv/vmm/vmm_fence.c
73
vmm_fence_enqueue(struct hypctx *hypctx, struct vmm_fence *new_fence)
sys/riscv/vmm/vmm_fence.c
78
mtx_lock_spin(&hypctx->fence_queue_mtx);
sys/riscv/vmm/vmm_fence.c
79
queue = hypctx->fence_queue;
sys/riscv/vmm/vmm_fence.c
80
fence = &queue[hypctx->fence_queue_tail];
sys/riscv/vmm/vmm_fence.c
83
hypctx->fence_queue_tail =
sys/riscv/vmm/vmm_fence.c
84
(hypctx->fence_queue_tail + 1) % VMM_FENCE_QUEUE_SIZE;
sys/riscv/vmm/vmm_fence.c
86
mtx_unlock_spin(&hypctx->fence_queue_mtx);
sys/riscv/vmm/vmm_fence.c
89
mtx_unlock_spin(&hypctx->fence_queue_mtx);
sys/riscv/vmm/vmm_fence.h
36
struct hypctx;
sys/riscv/vmm/vmm_fence.h
40
void vmm_fence_process(struct hypctx *hypctx);
sys/riscv/vmm/vmm_riscv.c
130
sizeof(struct hypctx *) * vm_get_maxcpus(vm));
sys/riscv/vmm/vmm_riscv.c
162
vmmops_vcpu_restore_csrs(struct hypctx *hypctx)
sys/riscv/vmm/vmm_riscv.c
166
csrs = &hypctx->guest_csrs;
sys/riscv/vmm/vmm_riscv.c
180
vmmops_vcpu_save_csrs(struct hypctx *hypctx)
sys/riscv/vmm/vmm_riscv.c
184
csrs = &hypctx->guest_csrs;
sys/riscv/vmm/vmm_riscv.c
200
struct hypctx *hypctx;
sys/riscv/vmm/vmm_riscv.c
211
size = round_page(sizeof(struct hypctx));
sys/riscv/vmm/vmm_riscv.c
213
hypctx = malloc_aligned(size, PAGE_SIZE, M_HYP, M_WAITOK | M_ZERO);
sys/riscv/vmm/vmm_riscv.c
214
hypctx->hyp = hyp;
sys/riscv/vmm/vmm_riscv.c
215
hypctx->vcpu = vcpu1;
sys/riscv/vmm/vmm_riscv.c
216
hypctx->guest_scounteren = HCOUNTEREN_CY | HCOUNTEREN_TM;
sys/riscv/vmm/vmm_riscv.c
219
hypctx->fence_queue = mallocarray(VMM_FENCE_QUEUE_SIZE,
sys/riscv/vmm/vmm_riscv.c
221
mtx_init(&hypctx->fence_queue_mtx, "fence queue", NULL, MTX_SPIN);
sys/riscv/vmm/vmm_riscv.c
224
hypctx->guest_regs.hyp_sstatus = SSTATUS_SPP | SSTATUS_SPIE;
sys/riscv/vmm/vmm_riscv.c
225
hypctx->guest_regs.hyp_sstatus |= SSTATUS_FS_INITIAL;
sys/riscv/vmm/vmm_riscv.c
228
hypctx->guest_regs.hyp_hstatus = HSTATUS_SPV | HSTATUS_VTW;
sys/riscv/vmm/vmm_riscv.c
229
hypctx->guest_regs.hyp_hstatus |= HSTATUS_SPVP;
sys/riscv/vmm/vmm_riscv.c
231
hypctx->cpu_id = vcpuid;
sys/riscv/vmm/vmm_riscv.c
232
hyp->ctx[vcpuid] = hypctx;
sys/riscv/vmm/vmm_riscv.c
234
aplic_cpuinit(hypctx);
sys/riscv/vmm/vmm_riscv.c
235
vtimer_cpuinit(hypctx);
sys/riscv/vmm/vmm_riscv.c
237
return (hypctx);
sys/riscv/vmm/vmm_riscv.c
267
riscv_unpriv_read(struct hypctx *hypctx, uintptr_t guest_addr, uint64_t *data,
sys/riscv/vmm/vmm_riscv.c
283
old_hstatus = csr_swap(hstatus, hypctx->guest_regs.hyp_hstatus);
sys/riscv/vmm/vmm_riscv.c
327
riscv_gen_inst_emul_data(struct hypctx *hypctx, struct vm_exit *vme_ret,
sys/riscv/vmm/vmm_riscv.c
353
riscv_unpriv_read(hypctx, guest_addr, &insn, trap);
sys/riscv/vmm/vmm_riscv.c
448
riscv_handle_world_switch(struct hypctx *hypctx, struct vm_exit *vme,
sys/riscv/vmm/vmm_riscv.c
464
vmm_stat_incr(hypctx->vcpu, VMEXIT_IRQ, 1);
sys/riscv/vmm/vmm_riscv.c
475
if (vm_mem_allocated(hypctx->vcpu, gpa)) {
sys/riscv/vmm/vmm_riscv.c
480
ret = riscv_gen_inst_emul_data(hypctx, vme, &trap);
sys/riscv/vmm/vmm_riscv.c
495
vmm_stat_incr(hypctx->vcpu, VMEXIT_UNHANDLED, 1);
sys/riscv/vmm/vmm_riscv.c
500
handled = vmm_sbi_ecall(hypctx->vcpu);
sys/riscv/vmm/vmm_riscv.c
504
vme->u.ecall.args[i] = hypctx->guest_regs.hyp_a[i];
sys/riscv/vmm/vmm_riscv.c
517
vmm_stat_incr(hypctx->vcpu, VMEXIT_UNHANDLED, 1);
sys/riscv/vmm/vmm_riscv.c
539
struct hypctx *hypctx;
sys/riscv/vmm/vmm_riscv.c
550
hypctx = hyp->ctx[i];
sys/riscv/vmm/vmm_riscv.c
551
atomic_set_32(&hypctx->ipi_pending, 1);
sys/riscv/vmm/vmm_riscv.c
557
riscv_check_ipi(struct hypctx *hypctx, bool clear)
sys/riscv/vmm/vmm_riscv.c
562
val = atomic_swap_32(&hypctx->ipi_pending, 0);
sys/riscv/vmm/vmm_riscv.c
564
val = hypctx->ipi_pending;
sys/riscv/vmm/vmm_riscv.c
570
riscv_check_interrupts_pending(struct hypctx *hypctx)
sys/riscv/vmm/vmm_riscv.c
573
if (hypctx->interrupts_pending)
sys/riscv/vmm/vmm_riscv.c
580
riscv_sync_interrupts(struct hypctx *hypctx)
sys/riscv/vmm/vmm_riscv.c
584
pending = aplic_check_pending(hypctx);
sys/riscv/vmm/vmm_riscv.c
586
hypctx->guest_csrs.hvip |= HVIP_VSEIP;
sys/riscv/vmm/vmm_riscv.c
588
hypctx->guest_csrs.hvip &= ~HVIP_VSEIP;
sys/riscv/vmm/vmm_riscv.c
591
if (riscv_check_ipi(hypctx, true))
sys/riscv/vmm/vmm_riscv.c
592
hypctx->guest_csrs.hvip |= HVIP_VSSIP;
sys/riscv/vmm/vmm_riscv.c
594
if (riscv_check_interrupts_pending(hypctx))
sys/riscv/vmm/vmm_riscv.c
595
hypctx->guest_csrs.hvip |= HVIP_VSTIP;
sys/riscv/vmm/vmm_riscv.c
597
hypctx->guest_csrs.hvip &= ~HVIP_VSTIP;
sys/riscv/vmm/vmm_riscv.c
599
csr_write(hvip, hypctx->guest_csrs.hvip);
sys/riscv/vmm/vmm_riscv.c
605
struct hypctx *hypctx;
sys/riscv/vmm/vmm_riscv.c
612
hypctx = (struct hypctx *)vcpui;
sys/riscv/vmm/vmm_riscv.c
613
vcpu = hypctx->vcpu;
sys/riscv/vmm/vmm_riscv.c
616
hypctx->guest_regs.hyp_sepc = (uint64_t)pc;
sys/riscv/vmm/vmm_riscv.c
637
vmmops_vcpu_restore_csrs(hypctx);
sys/riscv/vmm/vmm_riscv.c
642
if (hypctx->has_exception) {
sys/riscv/vmm/vmm_riscv.c
643
hypctx->has_exception = false;
sys/riscv/vmm/vmm_riscv.c
668
riscv_set_active_vcpu(hypctx);
sys/riscv/vmm/vmm_riscv.c
669
aplic_flush_hwstate(hypctx);
sys/riscv/vmm/vmm_riscv.c
670
riscv_sync_interrupts(hypctx);
sys/riscv/vmm/vmm_riscv.c
671
vmm_fence_process(hypctx);
sys/riscv/vmm/vmm_riscv.c
674
__func__, csr_read(vsatp), hypctx->guest_regs.hyp_sstatus,
sys/riscv/vmm/vmm_riscv.c
675
hypctx->guest_regs.hyp_hstatus);
sys/riscv/vmm/vmm_riscv.c
677
vmm_switch(hypctx);
sys/riscv/vmm/vmm_riscv.c
680
hypctx->guest_regs.hyp_hstatus);
sys/riscv/vmm/vmm_riscv.c
684
if ((hypctx->guest_csrs.hvip ^ hvip) & HVIP_VSSIP) {
sys/riscv/vmm/vmm_riscv.c
689
hypctx->guest_csrs.hvip &= ~HVIP_VSSIP;
sys/riscv/vmm/vmm_riscv.c
693
aplic_sync_hwstate(hypctx);
sys/riscv/vmm/vmm_riscv.c
708
vme->pc = hypctx->guest_regs.hyp_sepc;
sys/riscv/vmm/vmm_riscv.c
711
handled = riscv_handle_world_switch(hypctx, vme, pmap);
sys/riscv/vmm/vmm_riscv.c
717
hypctx->guest_regs.hyp_sepc += vme->inst_length;
sys/riscv/vmm/vmm_riscv.c
721
vmmops_vcpu_save_csrs(hypctx);
sys/riscv/vmm/vmm_riscv.c
745
struct hypctx *hypctx;
sys/riscv/vmm/vmm_riscv.c
747
hypctx = vcpui;
sys/riscv/vmm/vmm_riscv.c
751
aplic_cpucleanup(hypctx);
sys/riscv/vmm/vmm_riscv.c
753
mtx_destroy(&hypctx->fence_queue_mtx);
sys/riscv/vmm/vmm_riscv.c
754
free(hypctx->fence_queue, M_HYP);
sys/riscv/vmm/vmm_riscv.c
755
free(hypctx, M_HYP);
sys/riscv/vmm/vmm_riscv.c
779
hypctx_regptr(struct hypctx *hypctx, int reg)
sys/riscv/vmm/vmm_riscv.c
78
DPCPU_DEFINE_STATIC(struct hypctx *, vcpu);
sys/riscv/vmm/vmm_riscv.c
784
return (&hypctx->guest_regs.hyp_ra);
sys/riscv/vmm/vmm_riscv.c
786
return (&hypctx->guest_regs.hyp_sp);
sys/riscv/vmm/vmm_riscv.c
788
return (&hypctx->guest_regs.hyp_gp);
sys/riscv/vmm/vmm_riscv.c
790
return (&hypctx->guest_regs.hyp_tp);
sys/riscv/vmm/vmm_riscv.c
792
return (&hypctx->guest_regs.hyp_t[0]);
sys/riscv/vmm/vmm_riscv.c
794
return (&hypctx->guest_regs.hyp_t[1]);
sys/riscv/vmm/vmm_riscv.c
796
return (&hypctx->guest_regs.hyp_t[2]);
sys/riscv/vmm/vmm_riscv.c
798
return (&hypctx->guest_regs.hyp_s[0]);
sys/riscv/vmm/vmm_riscv.c
800
return (&hypctx->guest_regs.hyp_s[1]);
sys/riscv/vmm/vmm_riscv.c
802
return (&hypctx->guest_regs.hyp_a[0]);
sys/riscv/vmm/vmm_riscv.c
804
return (&hypctx->guest_regs.hyp_a[1]);
sys/riscv/vmm/vmm_riscv.c
806
return (&hypctx->guest_regs.hyp_a[2]);
sys/riscv/vmm/vmm_riscv.c
808
return (&hypctx->guest_regs.hyp_a[3]);
sys/riscv/vmm/vmm_riscv.c
810
return (&hypctx->guest_regs.hyp_a[4]);
sys/riscv/vmm/vmm_riscv.c
812
return (&hypctx->guest_regs.hyp_a[5]);
sys/riscv/vmm/vmm_riscv.c
814
return (&hypctx->guest_regs.hyp_a[6]);
sys/riscv/vmm/vmm_riscv.c
816
return (&hypctx->guest_regs.hyp_a[7]);
sys/riscv/vmm/vmm_riscv.c
818
return (&hypctx->guest_regs.hyp_s[2]);
sys/riscv/vmm/vmm_riscv.c
820
return (&hypctx->guest_regs.hyp_s[3]);
sys/riscv/vmm/vmm_riscv.c
822
return (&hypctx->guest_regs.hyp_s[4]);
sys/riscv/vmm/vmm_riscv.c
824
return (&hypctx->guest_regs.hyp_s[5]);
sys/riscv/vmm/vmm_riscv.c
826
return (&hypctx->guest_regs.hyp_s[6]);
sys/riscv/vmm/vmm_riscv.c
828
return (&hypctx->guest_regs.hyp_s[7]);
sys/riscv/vmm/vmm_riscv.c
830
return (&hypctx->guest_regs.hyp_s[8]);
sys/riscv/vmm/vmm_riscv.c
832
return (&hypctx->guest_regs.hyp_s[9]);
sys/riscv/vmm/vmm_riscv.c
834
return (&hypctx->guest_regs.hyp_s[10]);
sys/riscv/vmm/vmm_riscv.c
836
return (&hypctx->guest_regs.hyp_s[11]);
sys/riscv/vmm/vmm_riscv.c
838
return (&hypctx->guest_regs.hyp_t[3]);
sys/riscv/vmm/vmm_riscv.c
840
return (&hypctx->guest_regs.hyp_t[4]);
sys/riscv/vmm/vmm_riscv.c
842
return (&hypctx->guest_regs.hyp_t[5]);
sys/riscv/vmm/vmm_riscv.c
844
return (&hypctx->guest_regs.hyp_t[6]);
sys/riscv/vmm/vmm_riscv.c
846
return (&hypctx->guest_regs.hyp_sepc);
sys/riscv/vmm/vmm_riscv.c
859
struct hypctx *hypctx;
sys/riscv/vmm/vmm_riscv.c
861
hypctx = vcpui;
sys/riscv/vmm/vmm_riscv.c
863
running = vcpu_is_running(hypctx->vcpu, &hostcpu);
sys/riscv/vmm/vmm_riscv.c
865
panic("%s: %s%d is running", __func__, vm_name(hypctx->hyp->vm),
sys/riscv/vmm/vmm_riscv.c
866
vcpu_vcpuid(hypctx->vcpu));
sys/riscv/vmm/vmm_riscv.c
873
regp = hypctx_regptr(hypctx, reg);
sys/riscv/vmm/vmm_riscv.c
885
struct hypctx *hypctx;
sys/riscv/vmm/vmm_riscv.c
889
hypctx = vcpui;
sys/riscv/vmm/vmm_riscv.c
891
running = vcpu_is_running(hypctx->vcpu, &hostcpu);
sys/riscv/vmm/vmm_riscv.c
893
panic("%s: %s%d is running", __func__, vm_name(hypctx->hyp->vm),
sys/riscv/vmm/vmm_riscv.c
894
vcpu_vcpuid(hypctx->vcpu));
sys/riscv/vmm/vmm_riscv.c
896
regp = hypctx_regptr(hypctx, reg);
sys/riscv/vmm/vmm_riscv.c
908
struct hypctx *hypctx;
sys/riscv/vmm/vmm_riscv.c
91
riscv_set_active_vcpu(struct hypctx *hypctx)
sys/riscv/vmm/vmm_riscv.c
911
hypctx = vcpui;
sys/riscv/vmm/vmm_riscv.c
913
running = vcpu_is_running(hypctx->vcpu, &hostcpu);
sys/riscv/vmm/vmm_riscv.c
915
panic("%s: %s%d is running", __func__, vm_name(hypctx->hyp->vm),
sys/riscv/vmm/vmm_riscv.c
916
vcpu_vcpuid(hypctx->vcpu));
sys/riscv/vmm/vmm_riscv.c
94
DPCPU_SET(vcpu, hypctx);
sys/riscv/vmm/vmm_riscv.c
97
struct hypctx *
sys/riscv/vmm/vmm_sbi.c
114
vmm_sbi_handle_time(struct vcpu *vcpu, struct hypctx *hypctx)
sys/riscv/vmm/vmm_sbi.c
119
func_id = hypctx->guest_regs.hyp_a[6];
sys/riscv/vmm/vmm_sbi.c
120
next_val = hypctx->guest_regs.hyp_a[0];
sys/riscv/vmm/vmm_sbi.c
124
vtimer_set_timer(hypctx, next_val);
sys/riscv/vmm/vmm_sbi.c
134
vmm_sbi_handle_ipi(struct vcpu *vcpu, struct hypctx *hypctx)
sys/riscv/vmm/vmm_sbi.c
145
func_id = hypctx->guest_regs.hyp_a[6];
sys/riscv/vmm/vmm_sbi.c
146
hart_mask = hypctx->guest_regs.hyp_a[0];
sys/riscv/vmm/vmm_sbi.c
147
hart_mask_base = hypctx->guest_regs.hyp_a[1];
sys/riscv/vmm/vmm_sbi.c
151
hyp = hypctx->hyp;
sys/riscv/vmm/vmm_sbi.c
185
struct hypctx *hypctx;
sys/riscv/vmm/vmm_sbi.c
188
hypctx = riscv_get_active_vcpu();
sys/riscv/vmm/vmm_sbi.c
189
sbi_extension_id = hypctx->guest_regs.hyp_a[7];
sys/riscv/vmm/vmm_sbi.c
192
hypctx->guest_regs.hyp_a[0],
sys/riscv/vmm/vmm_sbi.c
193
hypctx->guest_regs.hyp_a[1],
sys/riscv/vmm/vmm_sbi.c
194
hypctx->guest_regs.hyp_a[2],
sys/riscv/vmm/vmm_sbi.c
195
hypctx->guest_regs.hyp_a[3],
sys/riscv/vmm/vmm_sbi.c
196
hypctx->guest_regs.hyp_a[4],
sys/riscv/vmm/vmm_sbi.c
197
hypctx->guest_regs.hyp_a[5],
sys/riscv/vmm/vmm_sbi.c
198
hypctx->guest_regs.hyp_a[6],
sys/riscv/vmm/vmm_sbi.c
199
hypctx->guest_regs.hyp_a[7]);
sys/riscv/vmm/vmm_sbi.c
203
error = vmm_sbi_handle_rfnc(vcpu, hypctx);
sys/riscv/vmm/vmm_sbi.c
206
error = vmm_sbi_handle_time(vcpu, hypctx);
sys/riscv/vmm/vmm_sbi.c
209
error = vmm_sbi_handle_ipi(vcpu, hypctx);
sys/riscv/vmm/vmm_sbi.c
216
hypctx->guest_regs.hyp_a[0] = error;
sys/riscv/vmm/vmm_sbi.c
45
vmm_sbi_handle_rfnc(struct vcpu *vcpu, struct hypctx *hypctx)
sys/riscv/vmm/vmm_sbi.c
57
func_id = hypctx->guest_regs.hyp_a[6];
sys/riscv/vmm/vmm_sbi.c
58
hart_mask = hypctx->guest_regs.hyp_a[0];
sys/riscv/vmm/vmm_sbi.c
59
hart_mask_base = hypctx->guest_regs.hyp_a[1];
sys/riscv/vmm/vmm_sbi.c
63
fence.start = hypctx->guest_regs.hyp_a[2];
sys/riscv/vmm/vmm_sbi.c
64
fence.size = hypctx->guest_regs.hyp_a[3];
sys/riscv/vmm/vmm_sbi.c
65
fence.asid = hypctx->guest_regs.hyp_a[4];
sys/riscv/vmm/vmm_sbi.c
83
hyp = hypctx->hyp;
sys/riscv/vmm/vmm_vtimer.c
106
vtimer = &hypctx->vtimer;
sys/riscv/vmm/vmm_vtimer.c
112
atomic_clear_32(&hypctx->interrupts_pending, HVIP_VSTIP);
sys/riscv/vmm/vmm_vtimer.c
114
vtimer_inject_irq_callout, hypctx, 0);
sys/riscv/vmm/vmm_vtimer.c
116
atomic_set_32(&hypctx->interrupts_pending, HVIP_VSTIP);
sys/riscv/vmm/vmm_vtimer.c
68
vtimer_cpuinit(struct hypctx *hypctx)
sys/riscv/vmm/vmm_vtimer.c
74
vtimer = &hypctx->vtimer;
sys/riscv/vmm/vmm_vtimer.c
88
struct hypctx *hypctx;
sys/riscv/vmm/vmm_vtimer.c
91
hypctx = arg;
sys/riscv/vmm/vmm_vtimer.c
92
hyp = hypctx->hyp;
sys/riscv/vmm/vmm_vtimer.c
94
atomic_set_32(&hypctx->interrupts_pending, HVIP_VSTIP);
sys/riscv/vmm/vmm_vtimer.c
95
vcpu_notify_event(vm_vcpu(hyp->vm, hypctx->cpu_id));
sys/riscv/vmm/vmm_vtimer.c
99
vtimer_set_timer(struct hypctx *hypctx, uint64_t next_val)
sys/riscv/vmm/vmm_vtimer.h
36
struct hypctx;
sys/riscv/vmm/vmm_vtimer.h
44
void vtimer_cpuinit(struct hypctx *hypctx);
sys/riscv/vmm/vmm_vtimer.h
45
int vtimer_set_timer(struct hypctx *hypctx, uint64_t next_val);