Symbol: hypctx
sys/arm64/vmm/arm64.h
154
struct hypctx *ctx[];
sys/arm64/vmm/arm64.h
165
struct hypctx *arm64_get_active_vcpu(void);
sys/arm64/vmm/arm64.h
166
void raise_data_insn_abort(struct hypctx *, uint64_t, bool, int);
sys/arm64/vmm/io/vgic.c
113
vgic_flush_hwstate(struct hypctx *hypctx)
sys/arm64/vmm/io/vgic.c
115
VGIC_FLUSH_HWSTATE(vgic_dev, hypctx);
sys/arm64/vmm/io/vgic.c
119
vgic_sync_hwstate(struct hypctx *hypctx)
sys/arm64/vmm/io/vgic.c
121
VGIC_SYNC_HWSTATE(vgic_dev, hypctx);
sys/arm64/vmm/io/vgic.c
69
vgic_cpuinit(struct hypctx *hypctx)
sys/arm64/vmm/io/vgic.c
71
VGIC_CPUINIT(vgic_dev, hypctx);
sys/arm64/vmm/io/vgic.c
75
vgic_cpucleanup(struct hypctx *hypctx)
sys/arm64/vmm/io/vgic.c
77
VGIC_CPUCLEANUP(vgic_dev, hypctx);
sys/arm64/vmm/io/vgic.c
93
vgic_has_pending_irq(struct hypctx *hypctx)
sys/arm64/vmm/io/vgic.c
95
return (VGIC_HAS_PENDING_IRQ(vgic_dev, hypctx));
sys/arm64/vmm/io/vgic.h
32
struct hypctx;
sys/arm64/vmm/io/vgic.h
42
void vgic_cpuinit(struct hypctx *hypctx);
sys/arm64/vmm/io/vgic.h
43
void vgic_cpucleanup(struct hypctx *hypctx);
sys/arm64/vmm/io/vgic.h
46
bool vgic_has_pending_irq(struct hypctx *hypctx);
sys/arm64/vmm/io/vgic.h
49
void vgic_flush_hwstate(struct hypctx *hypctx);
sys/arm64/vmm/io/vgic.h
50
void vgic_sync_hwstate(struct hypctx *hypctx);
sys/arm64/vmm/io/vgic_v3.c
1000
hyp = hypctx->hyp;
sys/arm64/vmm/io/vgic_v3.c
1012
dist_ctlr_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1019
vgic = hypctx->hyp->vgic;
sys/arm64/vmm/io/vgic_v3.c
1041
dist_typer_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
1056
dist_iidr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1063
dist_setclrspi_nsr_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1071
INJECT_IRQ(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu), irqid,
sys/arm64/vmm/io/vgic_v3.c
1077
dist_isenabler_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1084
*rval = read_enabler(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1088
dist_isenabler_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1098
write_enabler(hypctx, n, true, wval);
sys/arm64/vmm/io/vgic_v3.c
1103
dist_icenabler_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1110
*rval = read_enabler(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1114
dist_icenabler_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1124
write_enabler(hypctx, n, false, wval);
sys/arm64/vmm/io/vgic_v3.c
1129
dist_ispendr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1136
*rval = read_pendr(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1140
dist_ispendr_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1150
write_pendr(hypctx, n, true, wval);
sys/arm64/vmm/io/vgic_v3.c
1155
dist_icpendr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1162
*rval = read_pendr(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1166
dist_icpendr_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1176
write_pendr(hypctx, n, false, wval);
sys/arm64/vmm/io/vgic_v3.c
1182
dist_isactiver_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1189
*rval = read_activer(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1193
dist_isactiver_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1203
write_activer(hypctx, n, true, wval);
sys/arm64/vmm/io/vgic_v3.c
1208
dist_icactiver_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
1216
*rval = read_activer(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1220
dist_icactiver_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1230
write_activer(hypctx, n, false, wval);
sys/arm64/vmm/io/vgic_v3.c
1236
dist_ipriorityr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
1244
*rval = read_priorityr(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1248
dist_ipriorityr_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1256
write_priorityr(hypctx, irq_base, size, wval);
sys/arm64/vmm/io/vgic_v3.c
1261
dist_icfgr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1268
*rval = read_config(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1272
dist_icfgr_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1282
write_config(hypctx, n, wval);
sys/arm64/vmm/io/vgic_v3.c
1287
dist_irouter_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1294
*rval = read_route(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1298
dist_irouter_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1306
write_route(hypctx, n, wval, offset, size);
sys/arm64/vmm/io/vgic_v3.c
1310
vgic_register_read(struct hypctx *hypctx, struct vgic_register *reg_list,
sys/arm64/vmm/io/vgic_v3.c
1320
reg_list[i].read(hypctx, reg, rval, NULL);
sys/arm64/vmm/io/vgic_v3.c
1345
vgic_register_write(struct hypctx *hypctx, struct vgic_register *reg_list,
sys/arm64/vmm/io/vgic_v3.c
1355
reg_list[i].write(hypctx, reg, offset,
sys/arm64/vmm/io/vgic_v3.c
1375
struct hypctx *hypctx;
sys/arm64/vmm/io/vgic_v3.c
1379
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vgic_v3.c
1380
hyp = hypctx->hyp;
sys/arm64/vmm/io/vgic_v3.c
1398
if (vgic_register_read(hypctx, dist_registers, nitems(dist_registers),
sys/arm64/vmm/io/vgic_v3.c
1413
struct hypctx *hypctx;
sys/arm64/vmm/io/vgic_v3.c
1417
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vgic_v3.c
1418
hyp = hypctx->hyp;
sys/arm64/vmm/io/vgic_v3.c
1434
if (vgic_register_write(hypctx, dist_registers, nitems(dist_registers),
sys/arm64/vmm/io/vgic_v3.c
1449
redist_ctlr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1457
redist_iidr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1464
redist_typer_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1470
if (vcpu_vcpuid(hypctx->vcpu) == (vgic_max_cpu_count(hypctx->hyp) - 1))
sys/arm64/vmm/io/vgic_v3.c
1473
vmpidr_el2 = hypctx->vmpidr_el2;
sys/arm64/vmm/io/vgic_v3.c
1487
(uint64_t)vcpu_vcpuid(hypctx->vcpu) << GICR_TYPER_CPUNUM_SHIFT;
sys/arm64/vmm/io/vgic_v3.c
1501
redist_ienabler0_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
1504
*rval = read_enabler(hypctx, 0);
sys/arm64/vmm/io/vgic_v3.c
1508
redist_isenabler0_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1513
write_enabler(hypctx, 0, true, wval);
sys/arm64/vmm/io/vgic_v3.c
1518
redist_icenabler0_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1523
write_enabler(hypctx, 0, false, wval);
sys/arm64/vmm/io/vgic_v3.c
1528
redist_ipendr0_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
1531
*rval = read_pendr(hypctx, 0);
sys/arm64/vmm/io/vgic_v3.c
1535
redist_ispendr0_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1540
write_pendr(hypctx, 0, true, wval);
sys/arm64/vmm/io/vgic_v3.c
1545
redist_icpendr0_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1550
write_pendr(hypctx, 0, false, wval);
sys/arm64/vmm/io/vgic_v3.c
1555
redist_iactiver0_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
1558
*rval = read_activer(hypctx, 0);
sys/arm64/vmm/io/vgic_v3.c
1562
redist_isactiver0_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1565
write_activer(hypctx, 0, true, wval);
sys/arm64/vmm/io/vgic_v3.c
1570
redist_icactiver0_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
1573
write_activer(hypctx, 0, false, wval);
sys/arm64/vmm/io/vgic_v3.c
1578
redist_ipriorityr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
158
typedef void (register_read)(struct hypctx *, u_int, uint64_t *, void *);
sys/arm64/vmm/io/vgic_v3.c
1584
*rval = read_priorityr(hypctx, n);
sys/arm64/vmm/io/vgic_v3.c
1588
redist_ipriorityr_write(struct hypctx *hypctx, u_int reg, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
159
typedef void (register_write)(struct hypctx *, u_int, u_int, u_int,
sys/arm64/vmm/io/vgic_v3.c
1594
write_priorityr(hypctx, irq_base, size, wval);
sys/arm64/vmm/io/vgic_v3.c
1599
redist_icfgr1_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)
sys/arm64/vmm/io/vgic_v3.c
1601
*rval = read_config(hypctx, 1);
sys/arm64/vmm/io/vgic_v3.c
1605
redist_icfgr1_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
1610
write_config(hypctx, 1, wval);
sys/arm64/vmm/io/vgic_v3.c
1618
struct hypctx *hypctx, *target_hypctx;
sys/arm64/vmm/io/vgic_v3.c
1624
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vgic_v3.c
1625
hyp = hypctx->hyp;
sys/arm64/vmm/io/vgic_v3.c
1658
raise_data_insn_abort(hypctx, fault_ipa, true,
sys/arm64/vmm/io/vgic_v3.c
1696
struct hypctx *hypctx, *target_hypctx;
sys/arm64/vmm/io/vgic_v3.c
1702
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vgic_v3.c
1703
hyp = hypctx->hyp;
sys/arm64/vmm/io/vgic_v3.c
1735
raise_data_insn_abort(hypctx, fault_ipa, true,
sys/arm64/vmm/io/vgic_v3.c
1945
struct hypctx *hypctx;
sys/arm64/vmm/io/vgic_v3.c
1950
hypctx = hyp->ctx[vcpuid];
sys/arm64/vmm/io/vgic_v3.c
1951
if (hypctx == NULL)
sys/arm64/vmm/io/vgic_v3.c
1953
vgic_cpu = hypctx->vgic_cpu;
sys/arm64/vmm/io/vgic_v3.c
1979
vgic_v3_has_pending_irq(device_t dev, struct hypctx *hypctx)
sys/arm64/vmm/io/vgic_v3.c
1984
vgic_cpu = hypctx->vgic_cpu;
sys/arm64/vmm/io/vgic_v3.c
2018
struct hypctx *hypctx;
sys/arm64/vmm/io/vgic_v3.c
2051
hypctx = hyp->ctx[vcpuid];
sys/arm64/vmm/io/vgic_v3.c
2052
if (hypctx == NULL) {
sys/arm64/vmm/io/vgic_v3.c
2058
vgic_cpu = hypctx->vgic_cpu;
sys/arm64/vmm/io/vgic_v3.c
2104
vgic_v3_flush_hwstate(device_t dev, struct hypctx *hypctx)
sys/arm64/vmm/io/vgic_v3.c
2110
vgic_cpu = hypctx->vgic_cpu;
sys/arm64/vmm/io/vgic_v3.c
2121
hypctx->vgic_v3_regs.ich_hcr_el2 &= ~ICH_HCR_EL2_UIE;
sys/arm64/vmm/io/vgic_v3.c
2131
hypctx->vgic_v3_regs.ich_elrsr_el2 =
sys/arm64/vmm/io/vgic_v3.c
2132
(1u << hypctx->vgic_v3_regs.ich_lr_num) - 1;
sys/arm64/vmm/io/vgic_v3.c
2135
if (i == hypctx->vgic_v3_regs.ich_lr_num)
sys/arm64/vmm/io/vgic_v3.c
2141
hypctx->vgic_v3_regs.ich_lr_el2[i] = ICH_LR_EL2_GROUP1 |
sys/arm64/vmm/io/vgic_v3.c
2146
hypctx->vgic_v3_regs.ich_lr_el2[i] |=
sys/arm64/vmm/io/vgic_v3.c
2153
hypctx->vgic_v3_regs.ich_lr_el2[i] |= ICH_LR_EL2_EOI;
sys/arm64/vmm/io/vgic_v3.c
2157
hypctx->vgic_v3_regs.ich_lr_el2[i] |=
sys/arm64/vmm/io/vgic_v3.c
2180
vgic_v3_sync_hwstate(device_t dev, struct hypctx *hypctx)
sys/arm64/vmm/io/vgic_v3.c
2187
vgic_cpu = hypctx->vgic_cpu;
sys/arm64/vmm/io/vgic_v3.c
2199
lr = hypctx->vgic_v3_regs.ich_lr_el2[i];
sys/arm64/vmm/io/vgic_v3.c
2200
hypctx->vgic_v3_regs.ich_lr_el2[i] = 0;
sys/arm64/vmm/io/vgic_v3.c
2202
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
2247
hypctx->vgic_v3_regs.ich_hcr_el2 &= ~ICH_HCR_EL2_EOICOUNT_MASK;
sys/arm64/vmm/io/vgic_v3.c
429
struct hypctx *hypctx;
sys/arm64/vmm/io/vgic_v3.c
433
hypctx = hyp->ctx[i];
sys/arm64/vmm/io/vgic_v3.c
434
if (hypctx != NULL && (hypctx->vmpidr_el2 & GICD_AFF) == mpidr)
sys/arm64/vmm/io/vgic_v3.c
465
vgic_v3_cpuinit(device_t dev, struct hypctx *hypctx)
sys/arm64/vmm/io/vgic_v3.c
471
hypctx->vgic_cpu = malloc(sizeof(*hypctx->vgic_cpu),
sys/arm64/vmm/io/vgic_v3.c
473
vgic_cpu = hypctx->vgic_cpu;
sys/arm64/vmm/io/vgic_v3.c
484
irq->mpidr = hypctx->vmpidr_el2 & GICD_AFF;
sys/arm64/vmm/io/vgic_v3.c
485
irq->target_vcpu = vcpu_vcpuid(hypctx->vcpu);
sys/arm64/vmm/io/vgic_v3.c
506
hypctx->vgic_v3_regs.ich_hcr_el2 = ICH_HCR_EL2_En;
sys/arm64/vmm/io/vgic_v3.c
521
hypctx->vgic_v3_regs.ich_vmcr_el2 =
sys/arm64/vmm/io/vgic_v3.c
524
hypctx->vgic_v3_regs.ich_vmcr_el2 &= ~ICH_VMCR_EL2_VEOIM;
sys/arm64/vmm/io/vgic_v3.c
525
hypctx->vgic_v3_regs.ich_vmcr_el2 |= ICH_VMCR_EL2_VENG0 |
sys/arm64/vmm/io/vgic_v3.c
528
hypctx->vgic_v3_regs.ich_lr_num = virt_features.ich_lr_num;
sys/arm64/vmm/io/vgic_v3.c
529
for (i = 0; i < hypctx->vgic_v3_regs.ich_lr_num; i++)
sys/arm64/vmm/io/vgic_v3.c
530
hypctx->vgic_v3_regs.ich_lr_el2[i] = 0UL;
sys/arm64/vmm/io/vgic_v3.c
534
hypctx->vgic_v3_regs.ich_apr_num = virt_features.ich_apr_num;
sys/arm64/vmm/io/vgic_v3.c
538
vgic_v3_cpucleanup(device_t dev, struct hypctx *hypctx)
sys/arm64/vmm/io/vgic_v3.c
544
vgic_cpu = hypctx->vgic_cpu;
sys/arm64/vmm/io/vgic_v3.c
551
free(hypctx->vgic_cpu, M_VGIC_V3);
sys/arm64/vmm/io/vgic_v3.c
638
gic_pidr2_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
646
gic_zero_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vgic_v3.c
653
gic_ignore_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,
sys/arm64/vmm/io/vgic_v3.c
660
read_enabler(struct hypctx *hypctx, int n)
sys/arm64/vmm/io/vgic_v3.c
670
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
684
write_enabler(struct hypctx *hypctx,int n, bool set, uint64_t val)
sys/arm64/vmm/io/vgic_v3.c
697
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
708
read_pendr(struct hypctx *hypctx, int n)
sys/arm64/vmm/io/vgic_v3.c
718
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
732
write_pendr(struct hypctx *hypctx, int n, bool set, uint64_t val)
sys/arm64/vmm/io/vgic_v3.c
737
struct hypctx *target_hypctx;
sys/arm64/vmm/io/vgic_v3.c
743
hyp = hypctx->hyp;
sys/arm64/vmm/io/vgic_v3.c
751
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
786
read_activer(struct hypctx *hypctx, int n)
sys/arm64/vmm/io/vgic_v3.c
796
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
810
write_activer(struct hypctx *hypctx, u_int n, bool set, uint64_t val)
sys/arm64/vmm/io/vgic_v3.c
815
struct hypctx *target_hypctx;
sys/arm64/vmm/io/vgic_v3.c
820
hyp = hypctx->hyp;
sys/arm64/vmm/io/vgic_v3.c
827
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
861
read_priorityr(struct hypctx *hypctx, int n)
sys/arm64/vmm/io/vgic_v3.c
871
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
884
write_priorityr(struct hypctx *hypctx, u_int irq_base, u_int size, uint64_t val)
sys/arm64/vmm/io/vgic_v3.c
890
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
902
read_config(struct hypctx *hypctx, int n)
sys/arm64/vmm/io/vgic_v3.c
912
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
925
write_config(struct hypctx *hypctx, int n, uint64_t val)
sys/arm64/vmm/io/vgic_v3.c
941
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vgic_v3.c
953
read_route(struct hypctx *hypctx, int n)
sys/arm64/vmm/io/vgic_v3.c
958
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu), n);
sys/arm64/vmm/io/vgic_v3.c
969
write_route(struct hypctx *hypctx, int n, uint64_t val, u_int offset,
sys/arm64/vmm/io/vgic_v3.c
974
irq = vgic_v3_get_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu), n);
sys/arm64/vmm/io/vgic_v3.c
979
irq->target_vcpu = mpidr_to_vcpu(hypctx->hyp, irq->mpidr);
sys/arm64/vmm/io/vgic_v3.c
994
dist_ctlr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,
sys/arm64/vmm/io/vtimer.c
100
hypctx->hyp->vtimer.cntvoff_el2;
sys/arm64/vmm/io/vtimer.c
101
if (hypctx->vtimer_cpu.virt_timer.cntx_cval_el0 < cntpct_el0)
sys/arm64/vmm/io/vtimer.c
102
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vtimer.c
105
cntv_ctl = hypctx->vtimer_cpu.virt_timer.cntx_ctl_el0;
sys/arm64/vmm/io/vtimer.c
211
vtimer_cpuinit(struct hypctx *hypctx)
sys/arm64/vmm/io/vtimer.c
215
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
238
vtimer_cpucleanup(struct hypctx *hypctx)
sys/arm64/vmm/io/vtimer.c
242
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
252
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
255
hypctx = arm64_get_active_vcpu();
sys/arm64/vmm/io/vtimer.c
256
if (!hypctx) {
sys/arm64/vmm/io/vtimer.c
270
vtime_sync_timer(struct hypctx *hypctx, struct vtimer_timer *timer,
sys/arm64/vmm/io/vtimer.c
274
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vtimer.c
277
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vtimer.c
280
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vtimer.c
282
vtimer_schedule_irq(hypctx, false);
sys/arm64/vmm/io/vtimer.c
287
vtimer_sync_hwstate(struct hypctx *hypctx)
sys/arm64/vmm/io/vtimer.c
292
hypctx->hyp->vtimer.cntvoff_el2;
sys/arm64/vmm/io/vtimer.c
293
vtime_sync_timer(hypctx, &hypctx->vtimer_cpu.virt_timer, cntpct_el0);
sys/arm64/vmm/io/vtimer.c
295
if ((hypctx->hyp->vtimer.cnthctl_el2 & CNTHCTL_ECV_EN) != 0) {
sys/arm64/vmm/io/vtimer.c
296
vtime_sync_timer(hypctx, &hypctx->vtimer_cpu.phys_timer,
sys/arm64/vmm/io/vtimer.c
304
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
306
hypctx = context;
sys/arm64/vmm/io/vtimer.c
307
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vtimer.c
308
hypctx->vtimer_cpu.phys_timer.irqid, true);
sys/arm64/vmm/io/vtimer.c
314
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
316
hypctx = context;
sys/arm64/vmm/io/vtimer.c
317
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vtimer.c
318
hypctx->vtimer_cpu.virt_timer.irqid, true);
sys/arm64/vmm/io/vtimer.c
322
vtimer_schedule_irq(struct hypctx *hypctx, bool phys)
sys/arm64/vmm/io/vtimer.c
330
timer = &hypctx->vtimer_cpu.phys_timer;
sys/arm64/vmm/io/vtimer.c
332
timer = &hypctx->vtimer_cpu.virt_timer;
sys/arm64/vmm/io/vtimer.c
334
hypctx->hyp->vtimer.cntvoff_el2;
sys/arm64/vmm/io/vtimer.c
337
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(hypctx->vcpu),
sys/arm64/vmm/io/vtimer.c
344
vtimer_inject_irq_callout_phys, hypctx, 0);
sys/arm64/vmm/io/vtimer.c
347
vtimer_inject_irq_callout_virt, hypctx, 0);
sys/arm64/vmm/io/vtimer.c
352
vtimer_remove_irq(struct hypctx *hypctx, struct vcpu *vcpu)
sys/arm64/vmm/io/vtimer.c
357
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
367
vgic_inject_irq(hypctx->hyp, vcpu_vcpuid(vcpu), timer->irqid, false);
sys/arm64/vmm/io/vtimer.c
385
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
389
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vtimer.c
390
hyp = hypctx->hyp;
sys/arm64/vmm/io/vtimer.c
391
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
406
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
411
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vtimer.c
412
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
420
vtimer_remove_irq(hypctx, vcpu);
sys/arm64/vmm/io/vtimer.c
425
vtimer_schedule_irq(hypctx, true);
sys/arm64/vmm/io/vtimer.c
451
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
454
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vtimer.c
455
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
465
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
468
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vtimer.c
469
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
473
vtimer_remove_irq(hypctx, vcpu);
sys/arm64/vmm/io/vtimer.c
475
vtimer_schedule_irq(hypctx, true);
sys/arm64/vmm/io/vtimer.c
485
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
489
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vtimer.c
490
hyp = hypctx->hyp;
sys/arm64/vmm/io/vtimer.c
491
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
514
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
518
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/io/vtimer.c
519
hyp = hypctx->hyp;
sys/arm64/vmm/io/vtimer.c
520
vtimer_cpu = &hypctx->vtimer_cpu;
sys/arm64/vmm/io/vtimer.c
525
vtimer_remove_irq(hypctx, vcpu);
sys/arm64/vmm/io/vtimer.c
527
vtimer_schedule_irq(hypctx, true);
sys/arm64/vmm/io/vtimer.c
72
static void vtimer_schedule_irq(struct hypctx *hypctx, bool phys);
sys/arm64/vmm/io/vtimer.c
77
struct hypctx *hypctx;
sys/arm64/vmm/io/vtimer.c
81
hypctx = arm64_get_active_vcpu();
sys/arm64/vmm/io/vtimer.c
84
if (!hypctx) {
sys/arm64/vmm/io/vtimer.h
38
struct hypctx;
sys/arm64/vmm/io/vtimer.h
71
void vtimer_cpuinit(struct hypctx *);
sys/arm64/vmm/io/vtimer.h
72
void vtimer_cpucleanup(struct hypctx *);
sys/arm64/vmm/io/vtimer.h
75
void vtimer_sync_hwstate(struct hypctx *hypctx);
sys/arm64/vmm/vmm.c
431
struct hypctx *hypctx;
sys/arm64/vmm/vmm.c
433
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/vmm.c
436
hypctx->dbg_oslock = (wval & OSLAR_OSLK) == OSLAR_OSLK;
sys/arm64/vmm/vmm.c
443
struct hypctx *hypctx;
sys/arm64/vmm/vmm.c
446
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/vmm.c
448
if (hypctx->dbg_oslock)
sys/arm64/vmm/vmm.c
860
struct hypctx *hypctx;
sys/arm64/vmm/vmm.c
863
hypctx = vcpu_get_cookie(vcpu);
sys/arm64/vmm/vmm.c
865
if ((hypctx->tf.tf_esr & ESR_ELx_ISS_MASK) != 0)
sys/arm64/vmm/vmm.c
869
vme->u.smccc_call.func_id = hypctx->tf.tf_x[0];
sys/arm64/vmm/vmm.c
871
vme->u.smccc_call.args[i] = hypctx->tf.tf_x[i + 1];
sys/arm64/vmm/vmm_arm64.c
1000
ptep = ptp_hold(hypctx->vcpu, pte_addr, PAGE_SIZE, &cookie);
sys/arm64/vmm/vmm_arm64.c
107
DPCPU_DEFINE_STATIC(struct hypctx *, vcpu);
sys/arm64/vmm/vmm_arm64.c
1083
struct hypctx *hypctx;
sys/arm64/vmm/vmm_arm64.c
1088
hypctx = (struct hypctx *)vcpui;
sys/arm64/vmm/vmm_arm64.c
1089
hyp = hypctx->hyp;
sys/arm64/vmm/vmm_arm64.c
1090
vcpu = hypctx->vcpu;
sys/arm64/vmm/vmm_arm64.c
1093
hypctx->tf.tf_elr = (uint64_t)pc;
sys/arm64/vmm/vmm_arm64.c
1096
if (hypctx->has_exception) {
sys/arm64/vmm/vmm_arm64.c
1097
hypctx->has_exception = false;
sys/arm64/vmm/vmm_arm64.c
1098
hypctx->elr_el1 = hypctx->tf.tf_elr;
sys/arm64/vmm/vmm_arm64.c
110
arm64_set_active_vcpu(struct hypctx *hypctx)
sys/arm64/vmm/vmm_arm64.c
1100
mode = hypctx->tf.tf_spsr & (PSR_M_MASK | PSR_M_32);
sys/arm64/vmm/vmm_arm64.c
1103
hypctx->tf.tf_elr = hypctx->vbar_el1 + 0x0;
sys/arm64/vmm/vmm_arm64.c
1105
hypctx->tf.tf_elr = hypctx->vbar_el1 + 0x200;
sys/arm64/vmm/vmm_arm64.c
1108
hypctx->tf.tf_elr = hypctx->vbar_el1 + 0x400;
sys/arm64/vmm/vmm_arm64.c
1111
hypctx->tf.tf_elr = hypctx->vbar_el1 + 0x600;
sys/arm64/vmm/vmm_arm64.c
1115
hypctx->spsr_el1 = hypctx->tf.tf_spsr;
sys/arm64/vmm/vmm_arm64.c
1118
hypctx->tf.tf_spsr = hypctx->spsr_el1 & PSR_FLAGS;
sys/arm64/vmm/vmm_arm64.c
1119
hypctx->tf.tf_spsr |= PSR_DAIF | PSR_M_EL1h;
sys/arm64/vmm/vmm_arm64.c
112
DPCPU_SET(vcpu, hypctx);
sys/arm64/vmm/vmm_arm64.c
1125
if ((hypctx->sctlr_el1 & SCTLR_SPAN) == 0)
sys/arm64/vmm/vmm_arm64.c
1126
hypctx->tf.tf_spsr |= PSR_PAN;
sys/arm64/vmm/vmm_arm64.c
1127
if ((hypctx->sctlr_el1 & SCTLR_DSSBS) == 0)
sys/arm64/vmm/vmm_arm64.c
1128
hypctx->tf.tf_spsr &= ~PSR_SSBS;
sys/arm64/vmm/vmm_arm64.c
1130
hypctx->tf.tf_spsr |= PSR_SSBS;
sys/arm64/vmm/vmm_arm64.c
115
struct hypctx *
sys/arm64/vmm/vmm_arm64.c
1156
arm64_set_active_vcpu(hypctx);
sys/arm64/vmm/vmm_arm64.c
1157
vgic_flush_hwstate(hypctx);
sys/arm64/vmm/vmm_arm64.c
1160
excp_type = vmm_enter_guest(hyp, hypctx);
sys/arm64/vmm/vmm_arm64.c
1162
vgic_sync_hwstate(hypctx);
sys/arm64/vmm/vmm_arm64.c
1163
vtimer_sync_hwstate(hypctx);
sys/arm64/vmm/vmm_arm64.c
1175
vme->pc = hypctx->tf.tf_elr;
sys/arm64/vmm/vmm_arm64.c
1178
vme->u.hyp.esr_el2 = hypctx->tf.tf_esr;
sys/arm64/vmm/vmm_arm64.c
1179
vme->u.hyp.far_el2 = hypctx->exit_info.far_el2;
sys/arm64/vmm/vmm_arm64.c
1180
vme->u.hyp.hpfar_el2 = hypctx->exit_info.hpfar_el2;
sys/arm64/vmm/vmm_arm64.c
1182
handled = arm64_handle_world_switch(hypctx, excp_type, vme,
sys/arm64/vmm/vmm_arm64.c
1189
hypctx->tf.tf_elr += vme->inst_length;
sys/arm64/vmm/vmm_arm64.c
1214
struct hypctx *hypctx = vcpui;
sys/arm64/vmm/vmm_arm64.c
1216
vtimer_cpucleanup(hypctx);
sys/arm64/vmm/vmm_arm64.c
1217
vgic_cpucleanup(hypctx);
sys/arm64/vmm/vmm_arm64.c
1220
vmmpmap_remove(hypctx->el2_addr, el2_hypctx_size(), true);
sys/arm64/vmm/vmm_arm64.c
1222
free(hypctx, M_HYP);
sys/arm64/vmm/vmm_arm64.c
1246
hypctx_regptr(struct hypctx *hypctx, int reg)
sys/arm64/vmm/vmm_arm64.c
1250
return (&hypctx->tf.tf_x[reg]);
sys/arm64/vmm/vmm_arm64.c
1252
return (&hypctx->tf.tf_lr);
sys/arm64/vmm/vmm_arm64.c
1254
return (&hypctx->tf.tf_sp);
sys/arm64/vmm/vmm_arm64.c
1256
return (&hypctx->tf.tf_spsr);
sys/arm64/vmm/vmm_arm64.c
1258
return (&hypctx->tf.tf_elr);
sys/arm64/vmm/vmm_arm64.c
1260
return (&hypctx->sctlr_el1);
sys/arm64/vmm/vmm_arm64.c
1262
return (&hypctx->ttbr0_el1);
sys/arm64/vmm/vmm_arm64.c
1264
return (&hypctx->ttbr1_el1);
sys/arm64/vmm/vmm_arm64.c
1266
return (&hypctx->tcr_el1);
sys/arm64/vmm/vmm_arm64.c
1268
return (&hypctx->tcr2_el1);
sys/arm64/vmm/vmm_arm64.c
1270
return (&hypctx->vmpidr_el2);
sys/arm64/vmm/vmm_arm64.c
1282
struct hypctx *hypctx = vcpui;
sys/arm64/vmm/vmm_arm64.c
1284
running = vcpu_is_running(hypctx->vcpu, &hostcpu);
sys/arm64/vmm/vmm_arm64.c
1286
panic("arm_getreg: %s%d is running", vm_name(hypctx->hyp->vm),
sys/arm64/vmm/vmm_arm64.c
1287
vcpu_vcpuid(hypctx->vcpu));
sys/arm64/vmm/vmm_arm64.c
1289
regp = hypctx_regptr(hypctx, reg);
sys/arm64/vmm/vmm_arm64.c
1301
struct hypctx *hypctx = vcpui;
sys/arm64/vmm/vmm_arm64.c
1304
running = vcpu_is_running(hypctx->vcpu, &hostcpu);
sys/arm64/vmm/vmm_arm64.c
1306
panic("arm_setreg: %s%d is running", vm_name(hypctx->hyp->vm),
sys/arm64/vmm/vmm_arm64.c
1307
vcpu_vcpuid(hypctx->vcpu));
sys/arm64/vmm/vmm_arm64.c
1309
regp = hypctx_regptr(hypctx, reg);
sys/arm64/vmm/vmm_arm64.c
1320
struct hypctx *hypctx = vcpui;
sys/arm64/vmm/vmm_arm64.c
1323
running = vcpu_is_running(hypctx->vcpu, &hostcpu);
sys/arm64/vmm/vmm_arm64.c
1325
panic("%s: %s%d is running", __func__, vm_name(hypctx->hyp->vm),
sys/arm64/vmm/vmm_arm64.c
1326
vcpu_vcpuid(hypctx->vcpu));
sys/arm64/vmm/vmm_arm64.c
1328
hypctx->far_el1 = far;
sys/arm64/vmm/vmm_arm64.c
1329
hypctx->esr_el1 = esr;
sys/arm64/vmm/vmm_arm64.c
1330
hypctx->has_exception = true;
sys/arm64/vmm/vmm_arm64.c
1338
struct hypctx *hypctx = vcpui;
sys/arm64/vmm/vmm_arm64.c
1351
*retval = (hypctx->setcaps & (1ul << num)) != 0;
sys/arm64/vmm/vmm_arm64.c
1363
struct hypctx *hypctx = vcpui;
sys/arm64/vmm/vmm_arm64.c
1370
if ((val != 0) == ((hypctx->setcaps & (1ul << num)) != 0))
sys/arm64/vmm/vmm_arm64.c
1373
hypctx->mdcr_el2 |= MDCR_EL2_TDE;
sys/arm64/vmm/vmm_arm64.c
1374
else if ((hypctx->setcaps & (1ul << VM_CAP_SS_EXIT)) == 0)
sys/arm64/vmm/vmm_arm64.c
1375
hypctx->mdcr_el2 &= ~MDCR_EL2_TDE;
sys/arm64/vmm/vmm_arm64.c
1378
if ((val != 0) == ((hypctx->setcaps & (1ul << num)) != 0))
sys/arm64/vmm/vmm_arm64.c
1382
hypctx->debug_spsr |= (hypctx->tf.tf_spsr & PSR_SS);
sys/arm64/vmm/vmm_arm64.c
1383
hypctx->debug_mdscr |= (hypctx->mdscr_el1 & MDSCR_SS);
sys/arm64/vmm/vmm_arm64.c
1385
hypctx->tf.tf_spsr |= PSR_SS;
sys/arm64/vmm/vmm_arm64.c
1386
hypctx->mdscr_el1 |= MDSCR_SS;
sys/arm64/vmm/vmm_arm64.c
1387
hypctx->mdcr_el2 |= MDCR_EL2_TDE;
sys/arm64/vmm/vmm_arm64.c
1389
hypctx->tf.tf_spsr &= ~PSR_SS;
sys/arm64/vmm/vmm_arm64.c
1390
hypctx->tf.tf_spsr |= hypctx->debug_spsr;
sys/arm64/vmm/vmm_arm64.c
1391
hypctx->debug_spsr &= ~PSR_SS;
sys/arm64/vmm/vmm_arm64.c
1392
hypctx->mdscr_el1 &= ~MDSCR_SS;
sys/arm64/vmm/vmm_arm64.c
1393
hypctx->mdscr_el1 |= hypctx->debug_mdscr;
sys/arm64/vmm/vmm_arm64.c
1394
hypctx->debug_mdscr &= ~MDSCR_SS;
sys/arm64/vmm/vmm_arm64.c
1395
if ((hypctx->setcaps & (1ul << VM_CAP_BRK_EXIT)) == 0)
sys/arm64/vmm/vmm_arm64.c
1396
hypctx->mdcr_el2 &= ~MDCR_EL2_TDE;
sys/arm64/vmm/vmm_arm64.c
1400
if ((val != 0) == ((hypctx->setcaps & (1ul << num)) != 0))
sys/arm64/vmm/vmm_arm64.c
1404
hypctx->debug_spsr |= (hypctx->tf.tf_spsr &
sys/arm64/vmm/vmm_arm64.c
1406
hypctx->tf.tf_spsr |= PSR_I | PSR_F;
sys/arm64/vmm/vmm_arm64.c
1408
hypctx->tf.tf_spsr &= ~(PSR_I | PSR_F);
sys/arm64/vmm/vmm_arm64.c
1409
hypctx->tf.tf_spsr |= (hypctx->debug_spsr &
sys/arm64/vmm/vmm_arm64.c
1411
hypctx->debug_spsr &= ~(PSR_I | PSR_F);
sys/arm64/vmm/vmm_arm64.c
1421
hypctx->setcaps &= ~(1ul << num);
sys/arm64/vmm/vmm_arm64.c
1423
hypctx->setcaps |= (1ul << num);
sys/arm64/vmm/vmm_arm64.c
485
sizeof(struct hypctx *) * vm_get_maxcpus(vm)));
sys/arm64/vmm/vmm_arm64.c
491
return (round_page(sizeof(struct hypctx)));
sys/arm64/vmm/vmm_arm64.c
556
struct hypctx *hypctx;
sys/arm64/vmm/vmm_arm64.c
560
hypctx = malloc_aligned(size, PAGE_SIZE, M_HYP, M_WAITOK | M_ZERO);
sys/arm64/vmm/vmm_arm64.c
564
hyp->ctx[vcpuid] = hypctx;
sys/arm64/vmm/vmm_arm64.c
566
hypctx->hyp = hyp;
sys/arm64/vmm/vmm_arm64.c
567
hypctx->vcpu = vcpu1;
sys/arm64/vmm/vmm_arm64.c
569
reset_vm_el01_regs(hypctx);
sys/arm64/vmm/vmm_arm64.c
570
reset_vm_el2_regs(hypctx);
sys/arm64/vmm/vmm_arm64.c
572
vtimer_cpuinit(hypctx);
sys/arm64/vmm/vmm_arm64.c
573
vgic_cpuinit(hypctx);
sys/arm64/vmm/vmm_arm64.c
576
hypctx->el2_addr = el2_map_enter((vm_offset_t)hypctx, size,
sys/arm64/vmm/vmm_arm64.c
579
return (hypctx);
sys/arm64/vmm/vmm_arm64.c
614
arm64_gen_inst_emul_data(struct hypctx *hypctx, uint32_t esr_iss,
sys/arm64/vmm/vmm_arm64.c
625
HPFAR_EL2_FIPA_ADDR(hypctx->exit_info.hpfar_el2);
sys/arm64/vmm/vmm_arm64.c
627
vme_ret->u.inst_emul.gpa += hypctx->exit_info.far_el2 &
sys/arm64/vmm/vmm_arm64.c
640
paging->ttbr0_addr = hypctx->ttbr0_el1 & ~(TTBR_ASID_MASK | TTBR_CnP);
sys/arm64/vmm/vmm_arm64.c
641
paging->ttbr1_addr = hypctx->ttbr1_el1 & ~(TTBR_ASID_MASK | TTBR_CnP);
sys/arm64/vmm/vmm_arm64.c
642
paging->tcr_el1 = hypctx->tcr_el1;
sys/arm64/vmm/vmm_arm64.c
643
paging->tcr2_el1 = hypctx->tcr2_el1;
sys/arm64/vmm/vmm_arm64.c
644
paging->flags = hypctx->tf.tf_spsr & (PSR_M_MASK | PSR_M_32);
sys/arm64/vmm/vmm_arm64.c
645
if ((hypctx->sctlr_el1 & SCTLR_M) != 0)
sys/arm64/vmm/vmm_arm64.c
666
raise_data_insn_abort(struct hypctx *hypctx, uint64_t far, bool dabort, int fsc)
sys/arm64/vmm/vmm_arm64.c
670
if ((hypctx->tf.tf_spsr & PSR_M_MASK) == PSR_M_EL0t)
sys/arm64/vmm/vmm_arm64.c
678
esr |= hypctx->tf.tf_esr & ESR_ELx_IL;
sys/arm64/vmm/vmm_arm64.c
680
vmmops_exception(hypctx, esr | fsc, far);
sys/arm64/vmm/vmm_arm64.c
684
handle_el1_sync_excp(struct hypctx *hypctx, struct vm_exit *vme_ret,
sys/arm64/vmm/vmm_arm64.c
690
esr_ec = ESR_ELx_EXCEPTION(hypctx->tf.tf_esr);
sys/arm64/vmm/vmm_arm64.c
691
esr_iss = hypctx->tf.tf_esr & ESR_ELx_ISS_MASK;
sys/arm64/vmm/vmm_arm64.c
695
vmm_stat_incr(hypctx->vcpu, VMEXIT_UNKNOWN, 1);
sys/arm64/vmm/vmm_arm64.c
700
if ((hypctx->tf.tf_esr & 0x3) == 0) { /* WFI */
sys/arm64/vmm/vmm_arm64.c
701
vmm_stat_incr(hypctx->vcpu, VMEXIT_WFI, 1);
sys/arm64/vmm/vmm_arm64.c
704
vmm_stat_incr(hypctx->vcpu, VMEXIT_WFE, 1);
sys/arm64/vmm/vmm_arm64.c
709
vmm_stat_incr(hypctx->vcpu, VMEXIT_HVC, 1);
sys/arm64/vmm/vmm_arm64.c
713
vmm_stat_incr(hypctx->vcpu, VMEXIT_MSR, 1);
sys/arm64/vmm/vmm_arm64.c
718
vmm_stat_incr(hypctx->vcpu, VMEXIT_BRK, 1);
sys/arm64/vmm/vmm_arm64.c
722
vmm_stat_incr(hypctx->vcpu, VMEXIT_SS, 1);
sys/arm64/vmm/vmm_arm64.c
727
vmm_stat_incr(hypctx->vcpu, esr_ec == EXCP_DATA_ABORT_L ?
sys/arm64/vmm/vmm_arm64.c
729
switch (hypctx->tf.tf_esr & ISS_DATA_DFSC_MASK) {
sys/arm64/vmm/vmm_arm64.c
740
gpa = HPFAR_EL2_FIPA_ADDR(hypctx->exit_info.hpfar_el2);
sys/arm64/vmm/vmm_arm64.c
743
raise_data_insn_abort(hypctx,
sys/arm64/vmm/vmm_arm64.c
744
hypctx->exit_info.far_el2,
sys/arm64/vmm/vmm_arm64.c
751
if (vm_mem_allocated(hypctx->vcpu, gpa)) {
sys/arm64/vmm/vmm_arm64.c
754
vme_ret->u.paging.esr = hypctx->tf.tf_esr;
sys/arm64/vmm/vmm_arm64.c
761
raise_data_insn_abort(hypctx,
sys/arm64/vmm/vmm_arm64.c
762
hypctx->exit_info.far_el2, false,
sys/arm64/vmm/vmm_arm64.c
767
arm64_gen_inst_emul_data(hypctx, esr_iss,
sys/arm64/vmm/vmm_arm64.c
781
vmm_stat_incr(hypctx->vcpu, VMEXIT_UNHANDLED_SYNC, 1);
sys/arm64/vmm/vmm_arm64.c
792
arm64_handle_world_switch(struct hypctx *hypctx, int excp_type,
sys/arm64/vmm/vmm_arm64.c
800
handled = handle_el1_sync_excp(hypctx, vme, pmap);
sys/arm64/vmm/vmm_arm64.c
806
vmm_stat_incr(hypctx->vcpu,
sys/arm64/vmm/vmm_arm64.c
817
vmm_stat_incr(hypctx->vcpu, VMEXIT_UNHANDLED_EL2, 1);
sys/arm64/vmm/vmm_arm64.c
823
vmm_stat_incr(hypctx->vcpu, VMEXIT_UNHANDLED, 1);
sys/arm64/vmm/vmm_arm64.c
857
struct hypctx *hypctx;
sys/arm64/vmm/vmm_arm64.c
985
hypctx = (struct hypctx *)vcpui;
sys/arm64/vmm/vmm_handlers.c
52
vmm_nvhe_enter_guest(struct hyp *hyp, struct hypctx *hypctx)
sys/arm64/vmm/vmm_handlers.c
54
return (vmm_call_hyp(HYP_ENTER_GUEST, hyp->el2_addr, hypctx->el2_addr));
sys/arm64/vmm/vmm_handlers.c
58
(struct hyp *hyp, struct hypctx *hypctx))
sys/arm64/vmm/vmm_handlers.h
34
struct hypctx;
sys/arm64/vmm/vmm_handlers.h
37
uint64_t vmm_enter_guest(struct hyp *, struct hypctx *);
sys/arm64/vmm/vmm_handlers.h
43
uint64_t vmm_vhe_enter_guest(struct hyp *, struct hypctx *);
sys/arm64/vmm/vmm_hyp.c
107
switch (hypctx->vgic_v3_regs.ich_apr_num - 1) {
sys/arm64/vmm/vmm_hyp.c
110
hypctx->vgic_v3_regs.ich_ap0r_el2[x] = \
sys/arm64/vmm/vmm_hyp.c
112
hypctx->vgic_v3_regs.ich_ap1r_el2[x] = \
sys/arm64/vmm/vmm_hyp.c
123
hypctx->dbgclaimset_el1 = READ_SPECIALREG(dbgclaimset_el1);
sys/arm64/vmm/vmm_hyp.c
129
hypctx->dbgbcr_el1[x] = \
sys/arm64/vmm/vmm_hyp.c
131
hypctx->dbgbvr_el1[x] = \
sys/arm64/vmm/vmm_hyp.c
156
hypctx->dbgwcr_el1[x] = \
sys/arm64/vmm/vmm_hyp.c
158
hypctx->dbgwvr_el1[x] = \
sys/arm64/vmm/vmm_hyp.c
181
hypctx->pmcr_el0 = READ_SPECIALREG(pmcr_el0);
sys/arm64/vmm/vmm_hyp.c
182
hypctx->pmccntr_el0 = READ_SPECIALREG(pmccntr_el0);
sys/arm64/vmm/vmm_hyp.c
183
hypctx->pmccfiltr_el0 = READ_SPECIALREG(pmccfiltr_el0);
sys/arm64/vmm/vmm_hyp.c
184
hypctx->pmuserenr_el0 = READ_SPECIALREG(pmuserenr_el0);
sys/arm64/vmm/vmm_hyp.c
185
hypctx->pmselr_el0 = READ_SPECIALREG(pmselr_el0);
sys/arm64/vmm/vmm_hyp.c
186
hypctx->pmxevcntr_el0 = READ_SPECIALREG(pmxevcntr_el0);
sys/arm64/vmm/vmm_hyp.c
187
hypctx->pmcntenset_el0 = READ_SPECIALREG(pmcntenset_el0);
sys/arm64/vmm/vmm_hyp.c
188
hypctx->pmintenset_el1 = READ_SPECIALREG(pmintenset_el1);
sys/arm64/vmm/vmm_hyp.c
189
hypctx->pmovsset_el0 = READ_SPECIALREG(pmovsset_el0);
sys/arm64/vmm/vmm_hyp.c
191
switch ((hypctx->pmcr_el0 & PMCR_N_MASK) >> PMCR_N_SHIFT) {
sys/arm64/vmm/vmm_hyp.c
194
hypctx->pmevcntr_el0[x] = \
sys/arm64/vmm/vmm_hyp.c
196
hypctx->pmevtyper_el0[x] = \
sys/arm64/vmm/vmm_hyp.c
235
hypctx->tf.tf_sp = READ_SPECIALREG(sp_el1);
sys/arm64/vmm/vmm_hyp.c
236
hypctx->tf.tf_elr = READ_SPECIALREG(elr_el2);
sys/arm64/vmm/vmm_hyp.c
237
hypctx->tf.tf_spsr = READ_SPECIALREG(spsr_el2);
sys/arm64/vmm/vmm_hyp.c
239
hypctx->tf.tf_esr = READ_SPECIALREG(esr_el2);
sys/arm64/vmm/vmm_hyp.c
240
hypctx->par_el1 = READ_SPECIALREG(par_el1);
sys/arm64/vmm/vmm_hyp.c
244
hypctx->sp_el0 = READ_SPECIALREG(sp_el0);
sys/arm64/vmm/vmm_hyp.c
245
hypctx->tpidr_el0 = READ_SPECIALREG(tpidr_el0);
sys/arm64/vmm/vmm_hyp.c
246
hypctx->tpidrro_el0 = READ_SPECIALREG(tpidrro_el0);
sys/arm64/vmm/vmm_hyp.c
247
hypctx->tpidr_el1 = READ_SPECIALREG(tpidr_el1);
sys/arm64/vmm/vmm_hyp.c
249
hypctx->actlr_el1 = READ_SPECIALREG(actlr_el1);
sys/arm64/vmm/vmm_hyp.c
250
hypctx->csselr_el1 = READ_SPECIALREG(csselr_el1);
sys/arm64/vmm/vmm_hyp.c
251
hypctx->mdccint_el1 = READ_SPECIALREG(mdccint_el1);
sys/arm64/vmm/vmm_hyp.c
252
hypctx->mdscr_el1 = READ_SPECIALREG(mdscr_el1);
sys/arm64/vmm/vmm_hyp.c
255
hypctx->elr_el1 = READ_SPECIALREG(EL1_REG(ELR));
sys/arm64/vmm/vmm_hyp.c
256
hypctx->vbar_el1 = READ_SPECIALREG(EL1_REG(VBAR));
sys/arm64/vmm/vmm_hyp.c
258
hypctx->afsr0_el1 = READ_SPECIALREG(EL1_REG(AFSR0));
sys/arm64/vmm/vmm_hyp.c
259
hypctx->afsr1_el1 = READ_SPECIALREG(EL1_REG(AFSR1));
sys/arm64/vmm/vmm_hyp.c
260
hypctx->amair_el1 = READ_SPECIALREG(EL1_REG(AMAIR));
sys/arm64/vmm/vmm_hyp.c
261
hypctx->contextidr_el1 = READ_SPECIALREG(EL1_REG(CONTEXTIDR));
sys/arm64/vmm/vmm_hyp.c
262
hypctx->cpacr_el1 = READ_SPECIALREG(EL1_REG(CPACR));
sys/arm64/vmm/vmm_hyp.c
263
hypctx->esr_el1 = READ_SPECIALREG(EL1_REG(ESR));
sys/arm64/vmm/vmm_hyp.c
264
hypctx->far_el1 = READ_SPECIALREG(EL1_REG(FAR));
sys/arm64/vmm/vmm_hyp.c
265
hypctx->mair_el1 = READ_SPECIALREG(EL1_REG(MAIR));
sys/arm64/vmm/vmm_hyp.c
266
hypctx->sctlr_el1 = READ_SPECIALREG(EL1_REG(SCTLR));
sys/arm64/vmm/vmm_hyp.c
267
hypctx->spsr_el1 = READ_SPECIALREG(EL1_REG(SPSR));
sys/arm64/vmm/vmm_hyp.c
268
hypctx->tcr_el1 = READ_SPECIALREG(EL1_REG(TCR));
sys/arm64/vmm/vmm_hyp.c
270
hypctx->tcr2_el1 = 0;
sys/arm64/vmm/vmm_hyp.c
271
hypctx->ttbr0_el1 = READ_SPECIALREG(EL1_REG(TTBR0));
sys/arm64/vmm/vmm_hyp.c
272
hypctx->ttbr1_el1 = READ_SPECIALREG(EL1_REG(TTBR1));
sys/arm64/vmm/vmm_hyp.c
275
hypctx->cptr_el2 = READ_SPECIALREG(cptr_el2);
sys/arm64/vmm/vmm_hyp.c
276
hypctx->hcr_el2 = READ_SPECIALREG(hcr_el2);
sys/arm64/vmm/vmm_hyp.c
277
hypctx->vpidr_el2 = READ_SPECIALREG(vpidr_el2);
sys/arm64/vmm/vmm_hyp.c
278
hypctx->vmpidr_el2 = READ_SPECIALREG(vmpidr_el2);
sys/arm64/vmm/vmm_hyp.c
282
vmm_hyp_reg_restore(struct hypctx *hypctx, struct hyp *hyp, bool guest,
sys/arm64/vmm/vmm_hyp.c
288
WRITE_SPECIALREG(hcr_el2, hypctx->hcr_el2);
sys/arm64/vmm/vmm_hyp.c
292
WRITE_SPECIALREG(HCRX_EL2_REG, hypctx->hcrx_el2);
sys/arm64/vmm/vmm_hyp.c
300
WRITE_SPECIALREG(HDFGWTR_EL2_REG, hypctx->hdfgwtr_el2);
sys/arm64/vmm/vmm_hyp.c
301
WRITE_SPECIALREG(HFGITR_EL2_REG, hypctx->hfgitr_el2);
sys/arm64/vmm/vmm_hyp.c
302
WRITE_SPECIALREG(HFGRTR_EL2_REG, hypctx->hfgrtr_el2);
sys/arm64/vmm/vmm_hyp.c
303
WRITE_SPECIALREG(HFGWTR_EL2_REG, hypctx->hfgwtr_el2);
sys/arm64/vmm/vmm_hyp.c
308
hypctx->hdfgrtr2_el2);
sys/arm64/vmm/vmm_hyp.c
310
hypctx->hdfgwtr2_el2);
sys/arm64/vmm/vmm_hyp.c
311
WRITE_SPECIALREG(HFGITR2_EL2_REG, hypctx->hfgitr2_el2);
sys/arm64/vmm/vmm_hyp.c
312
WRITE_SPECIALREG(HFGRTR2_EL2_REG, hypctx->hfgrtr2_el2);
sys/arm64/vmm/vmm_hyp.c
313
WRITE_SPECIALREG(HFGWTR2_EL2_REG, hypctx->hfgwtr2_el2);
sys/arm64/vmm/vmm_hyp.c
318
WRITE_SPECIALREG(sp_el0, hypctx->sp_el0);
sys/arm64/vmm/vmm_hyp.c
319
WRITE_SPECIALREG(tpidr_el0, hypctx->tpidr_el0);
sys/arm64/vmm/vmm_hyp.c
320
WRITE_SPECIALREG(tpidrro_el0, hypctx->tpidrro_el0);
sys/arm64/vmm/vmm_hyp.c
321
WRITE_SPECIALREG(tpidr_el1, hypctx->tpidr_el1);
sys/arm64/vmm/vmm_hyp.c
323
WRITE_SPECIALREG(actlr_el1, hypctx->actlr_el1);
sys/arm64/vmm/vmm_hyp.c
324
WRITE_SPECIALREG(csselr_el1, hypctx->csselr_el1);
sys/arm64/vmm/vmm_hyp.c
325
WRITE_SPECIALREG(mdccint_el1, hypctx->mdccint_el1);
sys/arm64/vmm/vmm_hyp.c
326
WRITE_SPECIALREG(mdscr_el1, hypctx->mdscr_el1);
sys/arm64/vmm/vmm_hyp.c
329
WRITE_SPECIALREG(EL1_REG(ELR), hypctx->elr_el1);
sys/arm64/vmm/vmm_hyp.c
330
WRITE_SPECIALREG(EL1_REG(VBAR), hypctx->vbar_el1);
sys/arm64/vmm/vmm_hyp.c
332
WRITE_SPECIALREG(EL1_REG(AFSR0), hypctx->afsr0_el1);
sys/arm64/vmm/vmm_hyp.c
333
WRITE_SPECIALREG(EL1_REG(AFSR1), hypctx->afsr1_el1);
sys/arm64/vmm/vmm_hyp.c
334
WRITE_SPECIALREG(EL1_REG(AMAIR), hypctx->amair_el1);
sys/arm64/vmm/vmm_hyp.c
335
WRITE_SPECIALREG(EL1_REG(CONTEXTIDR), hypctx->contextidr_el1);
sys/arm64/vmm/vmm_hyp.c
336
WRITE_SPECIALREG(EL1_REG(CPACR), hypctx->cpacr_el1);
sys/arm64/vmm/vmm_hyp.c
337
WRITE_SPECIALREG(EL1_REG(ESR), hypctx->esr_el1);
sys/arm64/vmm/vmm_hyp.c
338
WRITE_SPECIALREG(EL1_REG(FAR), hypctx->far_el1);
sys/arm64/vmm/vmm_hyp.c
339
WRITE_SPECIALREG(EL1_REG(MAIR), hypctx->mair_el1); //
sys/arm64/vmm/vmm_hyp.c
341
WRITE_SPECIALREG(EL1_REG(SCTLR), hypctx->sctlr_el1);
sys/arm64/vmm/vmm_hyp.c
342
WRITE_SPECIALREG(EL1_REG(SPSR), hypctx->spsr_el1);
sys/arm64/vmm/vmm_hyp.c
343
WRITE_SPECIALREG(EL1_REG(TCR), hypctx->tcr_el1);
sys/arm64/vmm/vmm_hyp.c
345
WRITE_SPECIALREG(EL1_REG(TTBR0), hypctx->ttbr0_el1);
sys/arm64/vmm/vmm_hyp.c
346
WRITE_SPECIALREG(EL1_REG(TTBR1), hypctx->ttbr1_el1);
sys/arm64/vmm/vmm_hyp.c
350
WRITE_SPECIALREG(par_el1, hypctx->par_el1);
sys/arm64/vmm/vmm_hyp.c
353
WRITE_SPECIALREG(cptr_el2, hypctx->cptr_el2);
sys/arm64/vmm/vmm_hyp.c
354
WRITE_SPECIALREG(vpidr_el2, hypctx->vpidr_el2);
sys/arm64/vmm/vmm_hyp.c
355
WRITE_SPECIALREG(vmpidr_el2, hypctx->vmpidr_el2);
sys/arm64/vmm/vmm_hyp.c
358
WRITE_SPECIALREG(sp_el1, hypctx->tf.tf_sp);
sys/arm64/vmm/vmm_hyp.c
359
WRITE_SPECIALREG(elr_el2, hypctx->tf.tf_elr);
sys/arm64/vmm/vmm_hyp.c
360
WRITE_SPECIALREG(spsr_el2, hypctx->tf.tf_spsr);
sys/arm64/vmm/vmm_hyp.c
363
WRITE_SPECIALREG(pmcr_el0, hypctx->pmcr_el0);
sys/arm64/vmm/vmm_hyp.c
364
WRITE_SPECIALREG(pmccntr_el0, hypctx->pmccntr_el0);
sys/arm64/vmm/vmm_hyp.c
365
WRITE_SPECIALREG(pmccfiltr_el0, hypctx->pmccfiltr_el0);
sys/arm64/vmm/vmm_hyp.c
366
WRITE_SPECIALREG(pmuserenr_el0, hypctx->pmuserenr_el0);
sys/arm64/vmm/vmm_hyp.c
367
WRITE_SPECIALREG(pmselr_el0, hypctx->pmselr_el0);
sys/arm64/vmm/vmm_hyp.c
368
WRITE_SPECIALREG(pmxevcntr_el0, hypctx->pmxevcntr_el0);
sys/arm64/vmm/vmm_hyp.c
371
WRITE_SPECIALREG(pmcntenset_el0, hypctx->pmcntenset_el0);
sys/arm64/vmm/vmm_hyp.c
373
WRITE_SPECIALREG(pmintenset_el1, hypctx->pmintenset_el1);
sys/arm64/vmm/vmm_hyp.c
375
WRITE_SPECIALREG(pmovsset_el0, hypctx->pmovsset_el0);
sys/arm64/vmm/vmm_hyp.c
377
switch ((hypctx->pmcr_el0 & PMCR_N_MASK) >> PMCR_N_SHIFT) {
sys/arm64/vmm/vmm_hyp.c
381
hypctx->pmevcntr_el0[x]); \
sys/arm64/vmm/vmm_hyp.c
383
hypctx->pmevtyper_el0[x])
sys/arm64/vmm/vmm_hyp.c
39
struct hypctx;
sys/arm64/vmm/vmm_hyp.c
41
uint64_t VMM_HYP_FUNC(do_call_guest)(struct hypctx *);
sys/arm64/vmm/vmm_hyp.c
421
WRITE_SPECIALREG(dbgclaimclr_el1, hypctx->dbgclaimset_el1);
sys/arm64/vmm/vmm_hyp.c
428
hypctx->dbgbcr_el1[x]); \
sys/arm64/vmm/vmm_hyp.c
430
hypctx->dbgbvr_el1[x])
sys/arm64/vmm/vmm_hyp.c
44
vmm_hyp_reg_store(struct hypctx *hypctx, struct hyp *hyp, bool guest,
sys/arm64/vmm/vmm_hyp.c
455
hypctx->dbgwcr_el1[x]); \
sys/arm64/vmm/vmm_hyp.c
457
hypctx->dbgwvr_el1[x])
sys/arm64/vmm/vmm_hyp.c
481
hypctx->vtimer_cpu.cntkctl_el1);
sys/arm64/vmm/vmm_hyp.c
483
hypctx->vtimer_cpu.virt_timer.cntx_cval_el0);
sys/arm64/vmm/vmm_hyp.c
485
hypctx->vtimer_cpu.virt_timer.cntx_ctl_el0);
sys/arm64/vmm/vmm_hyp.c
506
hypctx->vtimer_cpu.phys_timer.cntx_cval_el0);
sys/arm64/vmm/vmm_hyp.c
508
hypctx->vtimer_cpu.phys_timer.cntx_ctl_el0);
sys/arm64/vmm/vmm_hyp.c
51
hypctx->vtimer_cpu.cntkctl_el1 =
sys/arm64/vmm/vmm_hyp.c
513
WRITE_SPECIALREG(ich_hcr_el2, hypctx->vgic_v3_regs.ich_hcr_el2);
sys/arm64/vmm/vmm_hyp.c
515
hypctx->vgic_v3_regs.ich_vmcr_el2);
sys/arm64/vmm/vmm_hyp.c
516
switch (hypctx->vgic_v3_regs.ich_lr_num - 1) {
sys/arm64/vmm/vmm_hyp.c
520
hypctx->vgic_v3_regs.ich_lr_el2[x])
sys/arm64/vmm/vmm_hyp.c
53
hypctx->vtimer_cpu.virt_timer.cntx_cval_el0 =
sys/arm64/vmm/vmm_hyp.c
541
switch (hypctx->vgic_v3_regs.ich_apr_num - 1) {
sys/arm64/vmm/vmm_hyp.c
545
hypctx->vgic_v3_regs.ich_ap0r_el2[x]); \
sys/arm64/vmm/vmm_hyp.c
547
hypctx->vgic_v3_regs.ich_ap1r_el2[x])
sys/arm64/vmm/vmm_hyp.c
55
hypctx->vtimer_cpu.virt_timer.cntx_ctl_el0 =
sys/arm64/vmm/vmm_hyp.c
559
vmm_hyp_call_guest(struct hyp *hyp, struct hypctx *hypctx)
sys/arm64/vmm/vmm_hyp.c
561
struct hypctx host_hypctx;
sys/arm64/vmm/vmm_hyp.c
586
vmm_hyp_reg_restore(hypctx, hyp, true, ecv_poff);
sys/arm64/vmm/vmm_hyp.c
592
WRITE_SPECIALREG(mdcr_el2, hypctx->mdcr_el2);
sys/arm64/vmm/vmm_hyp.c
595
ret = VMM_HYP_FUNC(do_call_guest)(hypctx);
sys/arm64/vmm/vmm_hyp.c
601
hypctx->exit_info.far_el2 = READ_SPECIALREG(far_el2);
sys/arm64/vmm/vmm_hyp.c
602
vmm_hyp_reg_store(hypctx, hyp, true, ecv_poff);
sys/arm64/vmm/vmm_hyp.c
606
switch (ESR_ELx_EXCEPTION(hypctx->tf.tf_esr)) {
sys/arm64/vmm/vmm_hyp.c
622
if ((hypctx->tf.tf_esr & ISS_DATA_S1PTW) != 0)
sys/arm64/vmm/vmm_hyp.c
624
switch (hypctx->tf.tf_esr & ISS_DATA_DFSC_MASK) {
sys/arm64/vmm/vmm_hyp.c
635
hypctx->exit_info.hpfar_el2 = READ_SPECIALREG(hpfar_el2);
sys/arm64/vmm/vmm_hyp.c
64
hypctx->vtimer_cpu.phys_timer.cntx_cval_el0 =
sys/arm64/vmm/vmm_hyp.c
642
arm64_address_translate_s1e1r(hypctx->exit_info.far_el2);
sys/arm64/vmm/vmm_hyp.c
646
hypctx->exit_info.hpfar_el2 = hpfar_el2;
sys/arm64/vmm/vmm_hyp.c
66
hypctx->vtimer_cpu.phys_timer.cntx_ctl_el0 =
sys/arm64/vmm/vmm_hyp.c
671
VMM_HYP_FUNC(enter_guest)(struct hyp *hyp, struct hypctx *hypctx)
sys/arm64/vmm/vmm_hyp.c
676
ret = vmm_hyp_call_guest(hyp, hypctx);
sys/arm64/vmm/vmm_hyp.c
72
hypctx->vgic_v3_regs.ich_eisr_el2 =
sys/arm64/vmm/vmm_hyp.c
74
hypctx->vgic_v3_regs.ich_elrsr_el2 =
sys/arm64/vmm/vmm_hyp.c
76
hypctx->vgic_v3_regs.ich_hcr_el2 =
sys/arm64/vmm/vmm_hyp.c
78
hypctx->vgic_v3_regs.ich_misr_el2 =
sys/arm64/vmm/vmm_hyp.c
80
hypctx->vgic_v3_regs.ich_vmcr_el2 =
sys/arm64/vmm/vmm_hyp.c
82
switch (hypctx->vgic_v3_regs.ich_lr_num - 1) {
sys/arm64/vmm/vmm_hyp.c
85
hypctx->vgic_v3_regs.ich_lr_el2[x] = \
sys/arm64/vmm/vmm_nvhe.c
96
(struct hypctx *)x2));
sys/arm64/vmm/vmm_reset.c
117
struct hypctx *el2ctx;
sys/arm64/vmm/vmm_reset.c
52
struct hypctx *el2ctx;
sys/riscv/riscv/genassym.c
103
ASSYM(HYP_H_RA, offsetof(struct hypctx, host_regs.hyp_ra));
sys/riscv/riscv/genassym.c
104
ASSYM(HYP_H_SP, offsetof(struct hypctx, host_regs.hyp_sp));
sys/riscv/riscv/genassym.c
105
ASSYM(HYP_H_GP, offsetof(struct hypctx, host_regs.hyp_gp));
sys/riscv/riscv/genassym.c
106
ASSYM(HYP_H_TP, offsetof(struct hypctx, host_regs.hyp_tp));
sys/riscv/riscv/genassym.c
107
ASSYM(HYP_H_T, offsetof(struct hypctx, host_regs.hyp_t));
sys/riscv/riscv/genassym.c
108
ASSYM(HYP_H_S, offsetof(struct hypctx, host_regs.hyp_s));
sys/riscv/riscv/genassym.c
109
ASSYM(HYP_H_A, offsetof(struct hypctx, host_regs.hyp_a));
sys/riscv/riscv/genassym.c
110
ASSYM(HYP_H_SEPC, offsetof(struct hypctx, host_regs.hyp_sepc));
sys/riscv/riscv/genassym.c
111
ASSYM(HYP_H_SSTATUS, offsetof(struct hypctx, host_regs.hyp_sstatus));
sys/riscv/riscv/genassym.c
112
ASSYM(HYP_H_HSTATUS, offsetof(struct hypctx, host_regs.hyp_hstatus));
sys/riscv/riscv/genassym.c
113
ASSYM(HYP_H_SSCRATCH, offsetof(struct hypctx, host_sscratch));
sys/riscv/riscv/genassym.c
114
ASSYM(HYP_H_STVEC, offsetof(struct hypctx, host_stvec));
sys/riscv/riscv/genassym.c
115
ASSYM(HYP_H_SCOUNTEREN, offsetof(struct hypctx, host_scounteren));
sys/riscv/riscv/genassym.c
117
ASSYM(HYP_G_RA, offsetof(struct hypctx, guest_regs.hyp_ra));
sys/riscv/riscv/genassym.c
118
ASSYM(HYP_G_SP, offsetof(struct hypctx, guest_regs.hyp_sp));
sys/riscv/riscv/genassym.c
119
ASSYM(HYP_G_GP, offsetof(struct hypctx, guest_regs.hyp_gp));
sys/riscv/riscv/genassym.c
120
ASSYM(HYP_G_TP, offsetof(struct hypctx, guest_regs.hyp_tp));
sys/riscv/riscv/genassym.c
121
ASSYM(HYP_G_T, offsetof(struct hypctx, guest_regs.hyp_t));
sys/riscv/riscv/genassym.c
122
ASSYM(HYP_G_S, offsetof(struct hypctx, guest_regs.hyp_s));
sys/riscv/riscv/genassym.c
123
ASSYM(HYP_G_A, offsetof(struct hypctx, guest_regs.hyp_a));
sys/riscv/riscv/genassym.c
124
ASSYM(HYP_G_SEPC, offsetof(struct hypctx, guest_regs.hyp_sepc));
sys/riscv/riscv/genassym.c
125
ASSYM(HYP_G_SSTATUS, offsetof(struct hypctx, guest_regs.hyp_sstatus));
sys/riscv/riscv/genassym.c
126
ASSYM(HYP_G_HSTATUS, offsetof(struct hypctx, guest_regs.hyp_hstatus));
sys/riscv/riscv/genassym.c
127
ASSYM(HYP_G_SCOUNTEREN, offsetof(struct hypctx, guest_scounteren));
sys/riscv/vmm/riscv.h
114
struct hypctx *ctx[];
sys/riscv/vmm/riscv.h
127
struct hypctx *riscv_get_active_vcpu(void);
sys/riscv/vmm/riscv.h
128
void vmm_switch(struct hypctx *);
sys/riscv/vmm/riscv.h
133
int riscv_check_ipi(struct hypctx *hypctx, bool clear);
sys/riscv/vmm/riscv.h
134
bool riscv_check_interrupts_pending(struct hypctx *hypctx);
sys/riscv/vmm/vmm_aplic.c
330
struct hypctx *hypctx;
sys/riscv/vmm/vmm_aplic.c
337
hypctx = vcpu_get_cookie(vcpu);
sys/riscv/vmm/vmm_aplic.c
338
hyp = hypctx->hyp;
sys/riscv/vmm/vmm_aplic.c
359
struct hypctx *hypctx;
sys/riscv/vmm/vmm_aplic.c
366
hypctx = vcpu_get_cookie(vcpu);
sys/riscv/vmm/vmm_aplic.c
367
hyp = hypctx->hyp;
sys/riscv/vmm/vmm_aplic.c
450
aplic_check_pending(struct hypctx *hypctx)
sys/riscv/vmm/vmm_aplic.c
457
hyp = hypctx->hyp;
sys/riscv/vmm/vmm_aplic.c
468
if (irq->target_hart != hypctx->cpu_id)
sys/riscv/vmm/vmm_aplic.c
560
aplic_cpuinit(struct hypctx *hypctx)
sys/riscv/vmm/vmm_aplic.c
566
aplic_cpucleanup(struct hypctx *hypctx)
sys/riscv/vmm/vmm_aplic.c
572
aplic_flush_hwstate(struct hypctx *hypctx)
sys/riscv/vmm/vmm_aplic.c
578
aplic_sync_hwstate(struct hypctx *hypctx)
sys/riscv/vmm/vmm_aplic.h
37
struct hypctx;
sys/riscv/vmm/vmm_aplic.h
46
int aplic_check_pending(struct hypctx *hypctx);
sys/riscv/vmm/vmm_aplic.h
48
void aplic_cpuinit(struct hypctx *hypctx);
sys/riscv/vmm/vmm_aplic.h
49
void aplic_cpucleanup(struct hypctx *hypctx);
sys/riscv/vmm/vmm_aplic.h
50
void aplic_flush_hwstate(struct hypctx *hypctx);
sys/riscv/vmm/vmm_aplic.h
51
void aplic_sync_hwstate(struct hypctx *hypctx);
sys/riscv/vmm/vmm_fence.c
124
vmm_fence_process(struct hypctx *hypctx)
sys/riscv/vmm/vmm_fence.c
129
pending = atomic_readandclear_32(&hypctx->fence_req);
sys/riscv/vmm/vmm_fence.c
140
while (vmm_fence_dequeue(hypctx, &fence) == true)
sys/riscv/vmm/vmm_fence.c
147
struct hypctx *hypctx;
sys/riscv/vmm/vmm_fence.c
162
hypctx = vcpu_get_cookie(vcpu);
sys/riscv/vmm/vmm_fence.c
169
atomic_set_32(&hypctx->fence_req, FENCE_REQ_I);
sys/riscv/vmm/vmm_fence.c
174
atomic_set_32(&hypctx->fence_req,
sys/riscv/vmm/vmm_fence.c
193
if (vmm_fence_enqueue(hypctx, fence) == false)
sys/riscv/vmm/vmm_fence.c
194
atomic_set_32(&hypctx->fence_req,
sys/riscv/vmm/vmm_fence.c
50
vmm_fence_dequeue(struct hypctx *hypctx, struct vmm_fence *new_fence)
sys/riscv/vmm/vmm_fence.c
55
mtx_lock_spin(&hypctx->fence_queue_mtx);
sys/riscv/vmm/vmm_fence.c
56
queue = hypctx->fence_queue;
sys/riscv/vmm/vmm_fence.c
57
fence = &queue[hypctx->fence_queue_head];
sys/riscv/vmm/vmm_fence.c
61
hypctx->fence_queue_head =
sys/riscv/vmm/vmm_fence.c
62
(hypctx->fence_queue_head + 1) % VMM_FENCE_QUEUE_SIZE;
sys/riscv/vmm/vmm_fence.c
64
mtx_unlock_spin(&hypctx->fence_queue_mtx);
sys/riscv/vmm/vmm_fence.c
67
mtx_unlock_spin(&hypctx->fence_queue_mtx);
sys/riscv/vmm/vmm_fence.c
73
vmm_fence_enqueue(struct hypctx *hypctx, struct vmm_fence *new_fence)
sys/riscv/vmm/vmm_fence.c
78
mtx_lock_spin(&hypctx->fence_queue_mtx);
sys/riscv/vmm/vmm_fence.c
79
queue = hypctx->fence_queue;
sys/riscv/vmm/vmm_fence.c
80
fence = &queue[hypctx->fence_queue_tail];
sys/riscv/vmm/vmm_fence.c
83
hypctx->fence_queue_tail =
sys/riscv/vmm/vmm_fence.c
84
(hypctx->fence_queue_tail + 1) % VMM_FENCE_QUEUE_SIZE;
sys/riscv/vmm/vmm_fence.c
86
mtx_unlock_spin(&hypctx->fence_queue_mtx);
sys/riscv/vmm/vmm_fence.c
89
mtx_unlock_spin(&hypctx->fence_queue_mtx);
sys/riscv/vmm/vmm_fence.h
36
struct hypctx;
sys/riscv/vmm/vmm_fence.h
40
void vmm_fence_process(struct hypctx *hypctx);
sys/riscv/vmm/vmm_riscv.c
130
sizeof(struct hypctx *) * vm_get_maxcpus(vm));
sys/riscv/vmm/vmm_riscv.c
162
vmmops_vcpu_restore_csrs(struct hypctx *hypctx)
sys/riscv/vmm/vmm_riscv.c
166
csrs = &hypctx->guest_csrs;
sys/riscv/vmm/vmm_riscv.c
180
vmmops_vcpu_save_csrs(struct hypctx *hypctx)
sys/riscv/vmm/vmm_riscv.c
184
csrs = &hypctx->guest_csrs;
sys/riscv/vmm/vmm_riscv.c
200
struct hypctx *hypctx;
sys/riscv/vmm/vmm_riscv.c
211
size = round_page(sizeof(struct hypctx));
sys/riscv/vmm/vmm_riscv.c
213
hypctx = malloc_aligned(size, PAGE_SIZE, M_HYP, M_WAITOK | M_ZERO);
sys/riscv/vmm/vmm_riscv.c
214
hypctx->hyp = hyp;
sys/riscv/vmm/vmm_riscv.c
215
hypctx->vcpu = vcpu1;
sys/riscv/vmm/vmm_riscv.c
216
hypctx->guest_scounteren = HCOUNTEREN_CY | HCOUNTEREN_TM;
sys/riscv/vmm/vmm_riscv.c
219
hypctx->fence_queue = mallocarray(VMM_FENCE_QUEUE_SIZE,
sys/riscv/vmm/vmm_riscv.c
221
mtx_init(&hypctx->fence_queue_mtx, "fence queue", NULL, MTX_SPIN);
sys/riscv/vmm/vmm_riscv.c
224
hypctx->guest_regs.hyp_sstatus = SSTATUS_SPP | SSTATUS_SPIE;
sys/riscv/vmm/vmm_riscv.c
225
hypctx->guest_regs.hyp_sstatus |= SSTATUS_FS_INITIAL;
sys/riscv/vmm/vmm_riscv.c
228
hypctx->guest_regs.hyp_hstatus = HSTATUS_SPV | HSTATUS_VTW;
sys/riscv/vmm/vmm_riscv.c
229
hypctx->guest_regs.hyp_hstatus |= HSTATUS_SPVP;
sys/riscv/vmm/vmm_riscv.c
231
hypctx->cpu_id = vcpuid;
sys/riscv/vmm/vmm_riscv.c
232
hyp->ctx[vcpuid] = hypctx;
sys/riscv/vmm/vmm_riscv.c
234
aplic_cpuinit(hypctx);
sys/riscv/vmm/vmm_riscv.c
235
vtimer_cpuinit(hypctx);
sys/riscv/vmm/vmm_riscv.c
237
return (hypctx);
sys/riscv/vmm/vmm_riscv.c
267
riscv_unpriv_read(struct hypctx *hypctx, uintptr_t guest_addr, uint64_t *data,
sys/riscv/vmm/vmm_riscv.c
283
old_hstatus = csr_swap(hstatus, hypctx->guest_regs.hyp_hstatus);
sys/riscv/vmm/vmm_riscv.c
327
riscv_gen_inst_emul_data(struct hypctx *hypctx, struct vm_exit *vme_ret,
sys/riscv/vmm/vmm_riscv.c
353
riscv_unpriv_read(hypctx, guest_addr, &insn, trap);
sys/riscv/vmm/vmm_riscv.c
448
riscv_handle_world_switch(struct hypctx *hypctx, struct vm_exit *vme,
sys/riscv/vmm/vmm_riscv.c
464
vmm_stat_incr(hypctx->vcpu, VMEXIT_IRQ, 1);
sys/riscv/vmm/vmm_riscv.c
475
if (vm_mem_allocated(hypctx->vcpu, gpa)) {
sys/riscv/vmm/vmm_riscv.c
480
ret = riscv_gen_inst_emul_data(hypctx, vme, &trap);
sys/riscv/vmm/vmm_riscv.c
495
vmm_stat_incr(hypctx->vcpu, VMEXIT_UNHANDLED, 1);
sys/riscv/vmm/vmm_riscv.c
500
handled = vmm_sbi_ecall(hypctx->vcpu);
sys/riscv/vmm/vmm_riscv.c
504
vme->u.ecall.args[i] = hypctx->guest_regs.hyp_a[i];
sys/riscv/vmm/vmm_riscv.c
517
vmm_stat_incr(hypctx->vcpu, VMEXIT_UNHANDLED, 1);
sys/riscv/vmm/vmm_riscv.c
539
struct hypctx *hypctx;
sys/riscv/vmm/vmm_riscv.c
550
hypctx = hyp->ctx[i];
sys/riscv/vmm/vmm_riscv.c
551
atomic_set_32(&hypctx->ipi_pending, 1);
sys/riscv/vmm/vmm_riscv.c
557
riscv_check_ipi(struct hypctx *hypctx, bool clear)
sys/riscv/vmm/vmm_riscv.c
562
val = atomic_swap_32(&hypctx->ipi_pending, 0);
sys/riscv/vmm/vmm_riscv.c
564
val = hypctx->ipi_pending;
sys/riscv/vmm/vmm_riscv.c
570
riscv_check_interrupts_pending(struct hypctx *hypctx)
sys/riscv/vmm/vmm_riscv.c
573
if (hypctx->interrupts_pending)
sys/riscv/vmm/vmm_riscv.c
580
riscv_sync_interrupts(struct hypctx *hypctx)
sys/riscv/vmm/vmm_riscv.c
584
pending = aplic_check_pending(hypctx);
sys/riscv/vmm/vmm_riscv.c
586
hypctx->guest_csrs.hvip |= HVIP_VSEIP;
sys/riscv/vmm/vmm_riscv.c
588
hypctx->guest_csrs.hvip &= ~HVIP_VSEIP;
sys/riscv/vmm/vmm_riscv.c
591
if (riscv_check_ipi(hypctx, true))
sys/riscv/vmm/vmm_riscv.c
592
hypctx->guest_csrs.hvip |= HVIP_VSSIP;
sys/riscv/vmm/vmm_riscv.c
594
if (riscv_check_interrupts_pending(hypctx))
sys/riscv/vmm/vmm_riscv.c
595
hypctx->guest_csrs.hvip |= HVIP_VSTIP;
sys/riscv/vmm/vmm_riscv.c
597
hypctx->guest_csrs.hvip &= ~HVIP_VSTIP;
sys/riscv/vmm/vmm_riscv.c
599
csr_write(hvip, hypctx->guest_csrs.hvip);
sys/riscv/vmm/vmm_riscv.c
605
struct hypctx *hypctx;
sys/riscv/vmm/vmm_riscv.c
612
hypctx = (struct hypctx *)vcpui;
sys/riscv/vmm/vmm_riscv.c
613
vcpu = hypctx->vcpu;
sys/riscv/vmm/vmm_riscv.c
616
hypctx->guest_regs.hyp_sepc = (uint64_t)pc;
sys/riscv/vmm/vmm_riscv.c
637
vmmops_vcpu_restore_csrs(hypctx);
sys/riscv/vmm/vmm_riscv.c
642
if (hypctx->has_exception) {
sys/riscv/vmm/vmm_riscv.c
643
hypctx->has_exception = false;
sys/riscv/vmm/vmm_riscv.c
668
riscv_set_active_vcpu(hypctx);
sys/riscv/vmm/vmm_riscv.c
669
aplic_flush_hwstate(hypctx);
sys/riscv/vmm/vmm_riscv.c
670
riscv_sync_interrupts(hypctx);
sys/riscv/vmm/vmm_riscv.c
671
vmm_fence_process(hypctx);
sys/riscv/vmm/vmm_riscv.c
674
__func__, csr_read(vsatp), hypctx->guest_regs.hyp_sstatus,
sys/riscv/vmm/vmm_riscv.c
675
hypctx->guest_regs.hyp_hstatus);
sys/riscv/vmm/vmm_riscv.c
677
vmm_switch(hypctx);
sys/riscv/vmm/vmm_riscv.c
680
hypctx->guest_regs.hyp_hstatus);
sys/riscv/vmm/vmm_riscv.c
684
if ((hypctx->guest_csrs.hvip ^ hvip) & HVIP_VSSIP) {
sys/riscv/vmm/vmm_riscv.c
689
hypctx->guest_csrs.hvip &= ~HVIP_VSSIP;
sys/riscv/vmm/vmm_riscv.c
693
aplic_sync_hwstate(hypctx);
sys/riscv/vmm/vmm_riscv.c
708
vme->pc = hypctx->guest_regs.hyp_sepc;
sys/riscv/vmm/vmm_riscv.c
711
handled = riscv_handle_world_switch(hypctx, vme, pmap);
sys/riscv/vmm/vmm_riscv.c
717
hypctx->guest_regs.hyp_sepc += vme->inst_length;
sys/riscv/vmm/vmm_riscv.c
721
vmmops_vcpu_save_csrs(hypctx);
sys/riscv/vmm/vmm_riscv.c
745
struct hypctx *hypctx;
sys/riscv/vmm/vmm_riscv.c
747
hypctx = vcpui;
sys/riscv/vmm/vmm_riscv.c
751
aplic_cpucleanup(hypctx);
sys/riscv/vmm/vmm_riscv.c
753
mtx_destroy(&hypctx->fence_queue_mtx);
sys/riscv/vmm/vmm_riscv.c
754
free(hypctx->fence_queue, M_HYP);
sys/riscv/vmm/vmm_riscv.c
755
free(hypctx, M_HYP);
sys/riscv/vmm/vmm_riscv.c
779
hypctx_regptr(struct hypctx *hypctx, int reg)
sys/riscv/vmm/vmm_riscv.c
78
DPCPU_DEFINE_STATIC(struct hypctx *, vcpu);
sys/riscv/vmm/vmm_riscv.c
784
return (&hypctx->guest_regs.hyp_ra);
sys/riscv/vmm/vmm_riscv.c
786
return (&hypctx->guest_regs.hyp_sp);
sys/riscv/vmm/vmm_riscv.c
788
return (&hypctx->guest_regs.hyp_gp);
sys/riscv/vmm/vmm_riscv.c
790
return (&hypctx->guest_regs.hyp_tp);
sys/riscv/vmm/vmm_riscv.c
792
return (&hypctx->guest_regs.hyp_t[0]);
sys/riscv/vmm/vmm_riscv.c
794
return (&hypctx->guest_regs.hyp_t[1]);
sys/riscv/vmm/vmm_riscv.c
796
return (&hypctx->guest_regs.hyp_t[2]);
sys/riscv/vmm/vmm_riscv.c
798
return (&hypctx->guest_regs.hyp_s[0]);
sys/riscv/vmm/vmm_riscv.c
800
return (&hypctx->guest_regs.hyp_s[1]);
sys/riscv/vmm/vmm_riscv.c
802
return (&hypctx->guest_regs.hyp_a[0]);
sys/riscv/vmm/vmm_riscv.c
804
return (&hypctx->guest_regs.hyp_a[1]);
sys/riscv/vmm/vmm_riscv.c
806
return (&hypctx->guest_regs.hyp_a[2]);
sys/riscv/vmm/vmm_riscv.c
808
return (&hypctx->guest_regs.hyp_a[3]);
sys/riscv/vmm/vmm_riscv.c
810
return (&hypctx->guest_regs.hyp_a[4]);
sys/riscv/vmm/vmm_riscv.c
812
return (&hypctx->guest_regs.hyp_a[5]);
sys/riscv/vmm/vmm_riscv.c
814
return (&hypctx->guest_regs.hyp_a[6]);
sys/riscv/vmm/vmm_riscv.c
816
return (&hypctx->guest_regs.hyp_a[7]);
sys/riscv/vmm/vmm_riscv.c
818
return (&hypctx->guest_regs.hyp_s[2]);
sys/riscv/vmm/vmm_riscv.c
820
return (&hypctx->guest_regs.hyp_s[3]);
sys/riscv/vmm/vmm_riscv.c
822
return (&hypctx->guest_regs.hyp_s[4]);
sys/riscv/vmm/vmm_riscv.c
824
return (&hypctx->guest_regs.hyp_s[5]);
sys/riscv/vmm/vmm_riscv.c
826
return (&hypctx->guest_regs.hyp_s[6]);
sys/riscv/vmm/vmm_riscv.c
828
return (&hypctx->guest_regs.hyp_s[7]);
sys/riscv/vmm/vmm_riscv.c
830
return (&hypctx->guest_regs.hyp_s[8]);
sys/riscv/vmm/vmm_riscv.c
832
return (&hypctx->guest_regs.hyp_s[9]);
sys/riscv/vmm/vmm_riscv.c
834
return (&hypctx->guest_regs.hyp_s[10]);
sys/riscv/vmm/vmm_riscv.c
836
return (&hypctx->guest_regs.hyp_s[11]);
sys/riscv/vmm/vmm_riscv.c
838
return (&hypctx->guest_regs.hyp_t[3]);
sys/riscv/vmm/vmm_riscv.c
840
return (&hypctx->guest_regs.hyp_t[4]);
sys/riscv/vmm/vmm_riscv.c
842
return (&hypctx->guest_regs.hyp_t[5]);
sys/riscv/vmm/vmm_riscv.c
844
return (&hypctx->guest_regs.hyp_t[6]);
sys/riscv/vmm/vmm_riscv.c
846
return (&hypctx->guest_regs.hyp_sepc);
sys/riscv/vmm/vmm_riscv.c
859
struct hypctx *hypctx;
sys/riscv/vmm/vmm_riscv.c
861
hypctx = vcpui;
sys/riscv/vmm/vmm_riscv.c
863
running = vcpu_is_running(hypctx->vcpu, &hostcpu);
sys/riscv/vmm/vmm_riscv.c
865
panic("%s: %s%d is running", __func__, vm_name(hypctx->hyp->vm),
sys/riscv/vmm/vmm_riscv.c
866
vcpu_vcpuid(hypctx->vcpu));
sys/riscv/vmm/vmm_riscv.c
873
regp = hypctx_regptr(hypctx, reg);
sys/riscv/vmm/vmm_riscv.c
885
struct hypctx *hypctx;
sys/riscv/vmm/vmm_riscv.c
889
hypctx = vcpui;
sys/riscv/vmm/vmm_riscv.c
891
running = vcpu_is_running(hypctx->vcpu, &hostcpu);
sys/riscv/vmm/vmm_riscv.c
893
panic("%s: %s%d is running", __func__, vm_name(hypctx->hyp->vm),
sys/riscv/vmm/vmm_riscv.c
894
vcpu_vcpuid(hypctx->vcpu));
sys/riscv/vmm/vmm_riscv.c
896
regp = hypctx_regptr(hypctx, reg);
sys/riscv/vmm/vmm_riscv.c
908
struct hypctx *hypctx;
sys/riscv/vmm/vmm_riscv.c
91
riscv_set_active_vcpu(struct hypctx *hypctx)
sys/riscv/vmm/vmm_riscv.c
911
hypctx = vcpui;
sys/riscv/vmm/vmm_riscv.c
913
running = vcpu_is_running(hypctx->vcpu, &hostcpu);
sys/riscv/vmm/vmm_riscv.c
915
panic("%s: %s%d is running", __func__, vm_name(hypctx->hyp->vm),
sys/riscv/vmm/vmm_riscv.c
916
vcpu_vcpuid(hypctx->vcpu));
sys/riscv/vmm/vmm_riscv.c
94
DPCPU_SET(vcpu, hypctx);
sys/riscv/vmm/vmm_riscv.c
97
struct hypctx *
sys/riscv/vmm/vmm_sbi.c
114
vmm_sbi_handle_time(struct vcpu *vcpu, struct hypctx *hypctx)
sys/riscv/vmm/vmm_sbi.c
119
func_id = hypctx->guest_regs.hyp_a[6];
sys/riscv/vmm/vmm_sbi.c
120
next_val = hypctx->guest_regs.hyp_a[0];
sys/riscv/vmm/vmm_sbi.c
124
vtimer_set_timer(hypctx, next_val);
sys/riscv/vmm/vmm_sbi.c
134
vmm_sbi_handle_ipi(struct vcpu *vcpu, struct hypctx *hypctx)
sys/riscv/vmm/vmm_sbi.c
145
func_id = hypctx->guest_regs.hyp_a[6];
sys/riscv/vmm/vmm_sbi.c
146
hart_mask = hypctx->guest_regs.hyp_a[0];
sys/riscv/vmm/vmm_sbi.c
147
hart_mask_base = hypctx->guest_regs.hyp_a[1];
sys/riscv/vmm/vmm_sbi.c
151
hyp = hypctx->hyp;
sys/riscv/vmm/vmm_sbi.c
185
struct hypctx *hypctx;
sys/riscv/vmm/vmm_sbi.c
188
hypctx = riscv_get_active_vcpu();
sys/riscv/vmm/vmm_sbi.c
189
sbi_extension_id = hypctx->guest_regs.hyp_a[7];
sys/riscv/vmm/vmm_sbi.c
192
hypctx->guest_regs.hyp_a[0],
sys/riscv/vmm/vmm_sbi.c
193
hypctx->guest_regs.hyp_a[1],
sys/riscv/vmm/vmm_sbi.c
194
hypctx->guest_regs.hyp_a[2],
sys/riscv/vmm/vmm_sbi.c
195
hypctx->guest_regs.hyp_a[3],
sys/riscv/vmm/vmm_sbi.c
196
hypctx->guest_regs.hyp_a[4],
sys/riscv/vmm/vmm_sbi.c
197
hypctx->guest_regs.hyp_a[5],
sys/riscv/vmm/vmm_sbi.c
198
hypctx->guest_regs.hyp_a[6],
sys/riscv/vmm/vmm_sbi.c
199
hypctx->guest_regs.hyp_a[7]);
sys/riscv/vmm/vmm_sbi.c
203
error = vmm_sbi_handle_rfnc(vcpu, hypctx);
sys/riscv/vmm/vmm_sbi.c
206
error = vmm_sbi_handle_time(vcpu, hypctx);
sys/riscv/vmm/vmm_sbi.c
209
error = vmm_sbi_handle_ipi(vcpu, hypctx);
sys/riscv/vmm/vmm_sbi.c
216
hypctx->guest_regs.hyp_a[0] = error;
sys/riscv/vmm/vmm_sbi.c
45
vmm_sbi_handle_rfnc(struct vcpu *vcpu, struct hypctx *hypctx)
sys/riscv/vmm/vmm_sbi.c
57
func_id = hypctx->guest_regs.hyp_a[6];
sys/riscv/vmm/vmm_sbi.c
58
hart_mask = hypctx->guest_regs.hyp_a[0];
sys/riscv/vmm/vmm_sbi.c
59
hart_mask_base = hypctx->guest_regs.hyp_a[1];
sys/riscv/vmm/vmm_sbi.c
63
fence.start = hypctx->guest_regs.hyp_a[2];
sys/riscv/vmm/vmm_sbi.c
64
fence.size = hypctx->guest_regs.hyp_a[3];
sys/riscv/vmm/vmm_sbi.c
65
fence.asid = hypctx->guest_regs.hyp_a[4];
sys/riscv/vmm/vmm_sbi.c
83
hyp = hypctx->hyp;
sys/riscv/vmm/vmm_vtimer.c
106
vtimer = &hypctx->vtimer;
sys/riscv/vmm/vmm_vtimer.c
112
atomic_clear_32(&hypctx->interrupts_pending, HVIP_VSTIP);
sys/riscv/vmm/vmm_vtimer.c
114
vtimer_inject_irq_callout, hypctx, 0);
sys/riscv/vmm/vmm_vtimer.c
116
atomic_set_32(&hypctx->interrupts_pending, HVIP_VSTIP);
sys/riscv/vmm/vmm_vtimer.c
68
vtimer_cpuinit(struct hypctx *hypctx)
sys/riscv/vmm/vmm_vtimer.c
74
vtimer = &hypctx->vtimer;
sys/riscv/vmm/vmm_vtimer.c
88
struct hypctx *hypctx;
sys/riscv/vmm/vmm_vtimer.c
91
hypctx = arg;
sys/riscv/vmm/vmm_vtimer.c
92
hyp = hypctx->hyp;
sys/riscv/vmm/vmm_vtimer.c
94
atomic_set_32(&hypctx->interrupts_pending, HVIP_VSTIP);
sys/riscv/vmm/vmm_vtimer.c
95
vcpu_notify_event(vm_vcpu(hyp->vm, hypctx->cpu_id));
sys/riscv/vmm/vmm_vtimer.c
99
vtimer_set_timer(struct hypctx *hypctx, uint64_t next_val)
sys/riscv/vmm/vmm_vtimer.h
36
struct hypctx;
sys/riscv/vmm/vmm_vtimer.h
44
void vtimer_cpuinit(struct hypctx *hypctx);
sys/riscv/vmm/vmm_vtimer.h
45
int vtimer_set_timer(struct hypctx *hypctx, uint64_t next_val);