sys/arm64/arm64/gic_v3.c

1046

gic_icc_write(EOIR1, gi->gi_irq);

sys/arm64/arm64/gic_v3.c

1064

gic_icc_write(EOIR1, gi->gi_irq);

sys/arm64/arm64/gic_v3.c

1171

gic_icc_write(SGI1R, val);

sys/arm64/arm64/gic_v3.c

1194

gic_icc_write(SGI1R, val);

sys/arm64/arm64/gic_v3.c

1258

gic_icc_write(PMR, mask & ICC_PMR_EL1_PRIO_MASK);

sys/arm64/arm64/gic_v3.c

639

gic_icc_write(EOIR1, (uint64_t)active_irq);

sys/arm64/arm64/gic_v3.c

649

gic_icc_write(EOIR1, gi->gi_irq);

sys/arm64/arm64/gic_v3.c

653

gic_icc_write(EOIR1, gi->gi_irq);

sys/arm64/arm64/gic_v3_reg.h

522

gic_icc_write(reg, val); \

sys/arm64/arm64/gic_v3_reg.h

530

gic_icc_write(reg, val); \

sys/arm64/arm64/gicv3_its.c

1329

gic_icc_write(EOIR1, girq->gi_lpi + GIC_FIRST_LPI);

sys/arm64/arm64/gicv3_its.c

1344

gic_icc_write(EOIR1, girq->gi_lpi + GIC_FIRST_LPI);