fw_state
u32 fw_state;
swstate->fw_state = t4_read_reg(padap, A_PCIE_FW);
switch (sc->fw_state) {
sc->fw_state);
if (sc->fw_state == IWI_FW_SCANNING)
if (sc->fw_state == IWI_FW_SCANNING) {
if (sc->fw_state == IWI_FW_LOADING) {
sc->fw_state = IWI_FW_IDLE;
if (sc->fw_state == IWI_FW_IDLE)
if (sc->fw_state == IWI_FW_SCANNING)
uint32_t fw_state;
KASSERT(_sc->fw_state == IWI_FW_IDLE, \
("iwi firmware not idle, state %s", iwi_fw_states[_sc->fw_state]));\
_sc->fw_state = _state; \
if (_sc->fw_state == _state) \
iwi_fw_states[_state], iwi_fw_states[_sc->fw_state])); \
_sc->fw_state = IWI_FW_IDLE; \
if (pd_info->fw_state != MFI_PD_STATE_SYSTEM) {
uint32_t fw_state, cur_state;
fw_state = cur_abs_reg_val & MFI_FWSTATE_MASK;
while (fw_state != MFI_FWSTATE_READY) {
cur_state = fw_state;
switch (fw_state) {
fw_state);
fw_state = cur_abs_reg_val & MFI_FWSTATE_MASK;
if (fw_state == cur_state)
if (fw_state == MFI_FWSTATE_DEVICE_SCAN) {
if (fw_state == cur_state) {
"%#x\n", fw_state);
uint32_t fw_state;
fw_state = sc->mfi_read_fw_status(sc);
if ((fw_state & MFI_FWSTATE_FAULT) == MFI_FWSTATE_FAULT ||
uint16_t fw_state; /* MFI_PD_STATE_* */
uint16_t fw_state; /* MFI_PD_STATE_* */
u_int32_t val, fw_state;
fw_state = val & MFI_STATE_MASK;
if (fw_state != MFI_STATE_READY)
while (fw_state != MFI_STATE_READY) {
switch (fw_state) {
device_printf(sc->mrsas_dev, "Unknown state 0x%x\n", fw_state);
fw_state = (mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
"in %d secs\n", fw_state, max_wait);
u_int32_t fw_status, fw_state;
fw_state = fw_status & MFI_STATE_MASK;
if (fw_state == MFI_STATE_FAULT || sc->do_timedout_reset ||
if (fw_state == MFI_STATE_FAULT || tm_target_reset_failed ||
u_int32_t fw_state, count, MSIxIndex;
fw_state = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
if (fw_state == MFI_STATE_FAULT) {
freework->fw_state &= ~DEPCOMPLETE;
freework->fw_state |= DEPCOMPLETE;
if ((freework->fw_state & ALLCOMPLETE) == ALLCOMPLETE)
freework->fw_state = ATTACHED;
freework->fw_state |= DEPCOMPLETE;
if ((fwn->fw_state & ONWORKLIST) == 0)
freework->fw_state |= DEPCOMPLETE;
freework->fw_state |= DELAYEDFREE;
if ((freework->fw_state & INPROGRESS) == 0)
if (freework->fw_state & DEPCOMPLETE) {
freework->fw_state |= INPROGRESS;
if (freework->fw_state & DELAYEDFREE)
freework->fw_state |= COMPLETE;
if ((freework->fw_state & ALLCOMPLETE) == ALLCOMPLETE)
freework->fw_state &= ~INPROGRESS;
freework->fw_state |= ALLCOMPLETE;
unsigned char fw_state;
ret = ath3k_get_state(hdl, &fw_state);
if (fw_state & ATH3K_PATCH_UPDATE) {
unsigned char fw_state;
ret = ath3k_get_state(hdl, &fw_state);
unsigned char fw_state;
ret = ath3k_get_state(hdl, &fw_state);
if ((fw_state & ATH3K_MODE_MASK) == ATH3K_NORMAL_MODE) {
if (info.fw_state != MFI_PD_STATE_HOT_SPARE) {
mfi_pdstate(ar->pd[j].fw_state));
if (pinfo->fw_state != MFI_PD_STATE_UNCONFIGURED_GOOD) {
ar->pd[i].fw_state = MFI_PD_STATE_ONLINE;
if (info.fw_state != MFI_PD_STATE_UNCONFIGURED_GOOD) {
if (info.fw_state == new_state) {
if (info.fw_state != MFI_PD_STATE_REBUILD) {
if (info.fw_state != MFI_PD_STATE_REBUILD) {
mfi_pdstate(ar->pd[k].fw_state));
sprintf(buf, "%s%s", mfi_pdstate(info->fw_state), foreign_state);
s = mfi_pdstate(info->fw_state);
mfi_pdstate(ar->pd[j].fw_state));
len = strlen(mfi_pdstate(info.fw_state));