for_each_set_bit
for_each_set_bit(bit, &vqs->rx_queues, 32) {
for_each_set_bit(bit, &vvm->txq_map, ICE_VIRTCHNL_QUEUE_MAP_SIZE) {
for_each_set_bit(bit, &vvm->rxq_map, ICE_VIRTCHNL_QUEUE_MAP_SIZE) {
for_each_set_bit(bit, &phy_high, 64)
for_each_set_bit(bit, &phy_low, 64)
for_each_set_bit(bit, &phy_low, 64) {
for_each_set_bit(bit, &phy_high, 64) {
for_each_set_bit(bit, &phy_type_low, 64)
for_each_set_bit(bit, &phy_type_high, 64) {
for_each_set_bit(bit, &cluster_mask,
for_each_set_bit(arp_index, rf->allocated_arps, rf->arp_table_size) {
for_each_set_bit(vlan, priv->vlan.active_vlans, VLAN_N_VID)
for_each_set_bit(vlan, priv->vlan.active_vlans, VLAN_N_VID) {
for_each_set_bit(i, priv->vlan.active_vlans, VLAN_N_VID) {
for_each_set_bit(i, priv->vlan.active_vlans, VLAN_N_VID)
for_each_set_bit(i, &sym_ae_msk, sym_ae_msk_size)
for_each_set_bit(idx, &bundle->tx_mask, tx_rx_offset)
for_each_set_bit(i, &ae_mask, GET_MAX_ACCELENGINES(accel_dev))
for_each_set_bit(ae, &ae_mask, max_aes)
for_each_set_bit(ae, &ae_mask, ICP_QAT_UCLO_MAX_AE)
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(ctx, &ctx_mask, ICP_QAT_UCLO_MAX_CTX)
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(i, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(a, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num)
for_each_set_bit(ae, &ae_mask, max_ae)
for_each_set_bit(thread, &thd_srv_mask, 8)
for_each_set_bit(i, &accel_mask, ADF_C4XXX_MAX_ACCELERATORS)
for_each_set_bit(srv, &service_mask, ADF_C4XXX_MAX_OBJ)
for_each_set_bit(accel, &accel_mask, ADF_C4XXX_MAX_ACCELERATORS)
for_each_set_bit(accel_num, &accel_mask, ADF_C4XXX_MAX_ACCELERATORS)
for_each_set_bit(accel, &accel_mask, ADF_C4XXX_MAX_ACCELERATORS)
for_each_set_bit(accel, &accel_mask, ADF_C4XXX_MAX_ACCELERATORS)
for_each_set_bit(accel, &accel_mask, ADF_C4XXX_MAX_ACCELERATORS)
for_each_set_bit(accel, &accel_mask, ADF_C4XXX_MAX_ACCELERATORS)
for_each_set_bit(i, &ae_mask, ADF_C4XXX_MAX_ACCELENGINES)
for_each_set_bit(i, &accel_mask, ADF_C4XXX_MAX_ACCELERATORS)
for_each_set_bit(i, &intr_status, ADF_C4XXX_RF_PAR_ERR_BITS)
for_each_set_bit(i,
for_each_set_bit(i,
for_each_set_bit(i, &tmp_iastatssm, ADF_C4XXX_IASTATSSM_BITS)
for_each_set_bit(accel, &tmp_errsou, num_accels)
for_each_set_bit(i, &ae_mask, ADF_C4XXX_MAX_ACCELENGINES)
for_each_set_bit(i, mad_reg_req->method_mask, IB_MGMT_MAX_METHODS) {
for_each_set_bit(i, mad_reg_req->method_mask, IB_MGMT_MAX_METHODS)
for_each_set_bit(i, mad_reg_req->method_mask, IB_MGMT_MAX_METHODS)