CLK_SYSTEM_RATE
GATE_INV(TEGRA124_CLK_HCLK, "hclk", "hclk_div", CLK_SYSTEM_RATE, 7),
GATE_INV(TEGRA124_CLK_PCLK, "pclk", "pclk_div", CLK_SYSTEM_RATE, 3),
DIV(0, "hclk_div", "sclk", CLK_SYSTEM_RATE, 4, 2, 0),
DIV(0, "pclk_div", "hclk", CLK_SYSTEM_RATE, 0, 2, 0),
GATE_INV(TEGRA210_CLK_HCLK, "hclk", "hclk_div", CLK_SYSTEM_RATE, 7),
GATE_INV(TEGRA210_CLK_PCLK, "pclk", "pclk_div", CLK_SYSTEM_RATE, 3),
DIV(0, "hclk_div", "sclk", CLK_SYSTEM_RATE, 4, 2, 0),
DIV(0, "pclk_div", "hclk", CLK_SYSTEM_RATE, 0, 2, 0),