dpaa2_swp_write_reg
dpaa2_swp_write_reg(sc->swp, DPAA2_SWP_CINH_DCAP, idx);
dpaa2_swp_write_reg(sc->swp, DPAA2_SWP_CINH_IIR, 0);
dpaa2_swp_write_reg(swp, DPAA2_SWP_CINH_VDQCR_RT,
dpaa2_swp_write_reg(swp, DPAA2_SWP_CINH_CR_RT,
dpaa2_swp_write_reg(p, DPAA2_SWP_CINH_CFG, reg);
dpaa2_swp_write_reg(p, DPAA2_SWP_CINH_SDQCR, 0);
dpaa2_swp_write_reg(swp, DPAA2_SWP_CINH_IER, mask);
dpaa2_swp_write_reg(swp, DPAA2_SWP_CINH_ISR, mask);
dpaa2_swp_write_reg(swp, DPAA2_SWP_CINH_SDQCR, dqsrc != 0
dpaa2_swp_write_reg(swp, DPAA2_SWP_CINH_DQRR_ITR, threshold);
dpaa2_swp_write_reg(swp, DPAA2_SWP_CINH_ITPR, itp);
dpaa2_swp_write_reg(swp, DPAA2_SWP_CINH_RCR_AM_RT +
void dpaa2_swp_write_reg(struct dpaa2_swp *swp, uint32_t o, uint32_t v);