cpsw_write_4
cpsw_write_4(sc->swsc, sc->physel,
cpsw_write_4(sc->swsc, CPSW_SL_RX_PRI_MAP(sc->unit), 0x76543210);
cpsw_write_4(sc->swsc, CPSW_PORT_P_TX_PRI_MAP(sc->unit + 1),
cpsw_write_4(sc->swsc, CPSW_SL_RX_MAXLEN(sc->unit), 0x5f2);
cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg);
cpsw_write_4(sc->swsc, CPSW_ALE_PORTCTL(sc->unit + 1),
cpsw_write_4(sc->swsc, CPSW_PORT_P_VLAN(sc->unit + 1),
cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0);
cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0);
cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg);
cpsw_write_4(sc->swsc, CPSW_ALE_CONTROL, reg);
cpsw_write_4(sc->swsc, sc->phyaccess, cmd);
cpsw_write_4(sc->swsc, sc->phyaccess, cmd);
cpsw_write_4(sc->swsc, reg, mac_control);
cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 1);
cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), added);
cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 2);
cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 0);
cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, intstat);
cpsw_write_4(sc, MDIOLINKINTMASKED,
cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 3);
cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023);
cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]);
cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]);
cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]);
cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023));
cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_HI(sc->unit + 1),
cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_LO(sc->unit + 1),
cpsw_write_4(sc, CPSW_STATS_OFFSET + cpsw_stat_sysctls[i].reg,
cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl);
cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), 0);
cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), 0);
cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), intr_per_ms);
cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), intr_per_ms);
cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl);
cpsw_write_4(sc, CPSW_PORT_P_VLAN(p->es_port),
cpsw_write_4(sc, CPSW_ALE_PORTCTL(p->es_port), reg);
cpsw_write_4(sc, slot->bd_offset, cpsw_cpdma_bd_paddr(sc, next_slot))
cpsw_write_4(sc, (queue)->hdp_offset, cpsw_cpdma_bd_paddr(sc, slot))
cpsw_write_4(sc, (queue)->hdp_offset + CP_OFFSET, (val))
cpsw_write_4(sc, reg, v);
cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(i), 0x00);
cpsw_write_4(sc, CPSW_WR_C_TX_EN(i), 0x00);
cpsw_write_4(sc, CPSW_WR_C_RX_EN(i), 0x00);
cpsw_write_4(sc, CPSW_WR_C_MISC_EN(i), 0x00);
cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 0);
cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 0);
cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0);
cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0);
cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0);
cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0);
cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF);
cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF);
cpsw_write_4(sc, CPSW_WR_INT_CONTROL, reg);
cpsw_write_4(sc, CPSW_ALE_CONTROL, CPSW_ALE_CTL_CLEAR_TBL);
cpsw_write_4(sc, CPSW_ALE_CONTROL, reg);
cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210);
cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0);
cpsw_write_4(sc, CPSW_ALE_PORTCTL(0),
cpsw_write_4(sc, CPSW_SS_PTYPE, 0);
cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7);
cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0);
cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, 2);
cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), 0);
cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0);
cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1);
cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1);
cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(0), 0xFF);
cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0xFF);
cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0xFF);
cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F);
cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 3);
cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET,
cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1);
cpsw_write_4(sc, MDIOCONTROL, MDIOCTL_ENABLE | MDIOCTL_FAULTENB | 0xff);
cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), sc->rx.active_queue_len);
cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), CPSW_TXFRAGS);