cpsw_read_4
reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit));
reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit));
reg = cpsw_read_4(sc->swsc, CPSW_ALE_CONTROL);
r = cpsw_read_4(sc, reg);
r = cpsw_read_4(sc->swsc, sc->phyaccess);
mac_control = cpsw_read_4(sc->swsc, reg);
if (cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)) == 0xfffffffc)
intstat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED);
dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS);
txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(txchan)));
txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_CP(txchan)));
rxchan, cpsw_read_4(sc,CPSW_CPDMA_RX_HDP(rxchan)));
rxchan, cpsw_read_4(sc, CPSW_CPDMA_RX_CP(rxchan)));
uint32_t stat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0));
cpsw_read_4(sc, MDIOLINKINTMASKED));
cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)));
cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)));
ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0);
ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1);
ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2);
r = cpsw_read_4(sc, CPSW_STATS_OFFSET +
r = cpsw_read_4(sc, CPSW_STATS_OFFSET +
result += cpsw_read_4(sc, CPSW_STATS_OFFSET + stat->reg);
ctrl = cpsw_read_4(sc, CPSW_WR_INT_CONTROL);
reg = cpsw_read_4(sc, CPSW_PORT_P_VLAN(p->es_port));
reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port));
reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port));
cpsw_read_4(sc, (queue)->hdp_offset + CP_OFFSET)
CPSW_DEBUGF(("HDP <=== 0x%08x (was 0x%08x)", v, cpsw_read_4(sc, reg)));
while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1)
while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1)
while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1)
while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1)
reg = cpsw_read_4(sc, CPSW_WR_INT_CONTROL);
reg = cpsw_read_4(sc, CPSW_SS_IDVER);