sys/dev/arcmsr/arcmsr.c

1086

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);

sys/dev/arcmsr/arcmsr.c

1088

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);

sys/dev/arcmsr/arcmsr.c

1118

CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);

sys/dev/arcmsr/arcmsr.c

1119

CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);

sys/dev/arcmsr/arcmsr.c

1123

CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);

sys/dev/arcmsr/arcmsr.c

1151

CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index);

sys/dev/arcmsr/arcmsr.c

1160

CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0);

sys/dev/arcmsr/arcmsr.c

1161

CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);

sys/dev/arcmsr/arcmsr.c

1176

CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0);

sys/dev/arcmsr/arcmsr.c

1177

CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);

sys/dev/arcmsr/arcmsr.c

1281

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);

sys/dev/arcmsr/arcmsr.c

1292

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);

sys/dev/arcmsr/arcmsr.c

1297

CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);

sys/dev/arcmsr/arcmsr.c

1304

CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);

sys/dev/arcmsr/arcmsr.c

1321

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);

sys/dev/arcmsr/arcmsr.c

1338

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);

sys/dev/arcmsr/arcmsr.c

1346

CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);

sys/dev/arcmsr/arcmsr.c

1356

CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);

sys/dev/arcmsr/arcmsr.c

1368

CHIP_REG_WRITE32(HBA_MessageUnit,

sys/dev/arcmsr/arcmsr.c

1396

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);

sys/dev/arcmsr/arcmsr.c

1397

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);

sys/dev/arcmsr/arcmsr.c

1409

CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);

sys/dev/arcmsr/arcmsr.c

1421

CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);

sys/dev/arcmsr/arcmsr.c

1423

CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);

sys/dev/arcmsr/arcmsr.c

1845

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);

sys/dev/arcmsr/arcmsr.c

1871

CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);

sys/dev/arcmsr/arcmsr.c

1883

CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);

sys/dev/arcmsr/arcmsr.c

1895

CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);

sys/dev/arcmsr/arcmsr.c

1919

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */

sys/dev/arcmsr/arcmsr.c

1943

CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */

sys/dev/arcmsr/arcmsr.c

1971

CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */

sys/dev/arcmsr/arcmsr.c

1984

CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */

sys/dev/arcmsr/arcmsr.c

2003

CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */

sys/dev/arcmsr/arcmsr.c

2036

CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */

sys/dev/arcmsr/arcmsr.c

2125

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);

sys/dev/arcmsr/arcmsr.c

2183

CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);

sys/dev/arcmsr/arcmsr.c

2186

CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR);

sys/dev/arcmsr/arcmsr.c

2215

CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index);

sys/dev/arcmsr/arcmsr.c

2243

CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index);

sys/dev/arcmsr/arcmsr.c

2263

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/

sys/dev/arcmsr/arcmsr.c

2363

CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);

sys/dev/arcmsr/arcmsr.c

2373

CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE);

sys/dev/arcmsr/arcmsr.c

2487

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);

sys/dev/arcmsr/arcmsr.c

2497

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);

sys/dev/arcmsr/arcmsr.c

2498

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);

sys/dev/arcmsr/arcmsr.c

2502

CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);

sys/dev/arcmsr/arcmsr.c

2506

CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);

sys/dev/arcmsr/arcmsr.c

2508

CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);

sys/dev/arcmsr/arcmsr.c

2516

CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);

sys/dev/arcmsr/arcmsr.c

2518

CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);

sys/dev/arcmsr/arcmsr.c

275

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);

sys/dev/arcmsr/arcmsr.c

289

CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);

sys/dev/arcmsr/arcmsr.c

295

CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);

sys/dev/arcmsr/arcmsr.c

302

CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE);

sys/dev/arcmsr/arcmsr.c

320

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);

sys/dev/arcmsr/arcmsr.c

335

CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);

sys/dev/arcmsr/arcmsr.c

3375

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);

sys/dev/arcmsr/arcmsr.c

3400

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);

sys/dev/arcmsr/arcmsr.c

3401

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);

sys/dev/arcmsr/arcmsr.c

3413

CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);

sys/dev/arcmsr/arcmsr.c

342

CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);

sys/dev/arcmsr/arcmsr.c

3425

CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);

sys/dev/arcmsr/arcmsr.c

3427

CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);

sys/dev/arcmsr/arcmsr.c

3471

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/

sys/dev/arcmsr/arcmsr.c

351

CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask);

sys/dev/arcmsr/arcmsr.c

3658

CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);

sys/dev/arcmsr/arcmsr.c

369

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/

sys/dev/arcmsr/arcmsr.c

3729

CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index);

sys/dev/arcmsr/arcmsr.c

3770

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);

sys/dev/arcmsr/arcmsr.c

3869

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);

sys/dev/arcmsr/arcmsr.c

3870

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);

sys/dev/arcmsr/arcmsr.c

3920

CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);

sys/dev/arcmsr/arcmsr.c

3921

CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);

sys/dev/arcmsr/arcmsr.c

3970

CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);

sys/dev/arcmsr/arcmsr.c

3972

CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);

sys/dev/arcmsr/arcmsr.c

4022

CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);

sys/dev/arcmsr/arcmsr.c

4024

CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);

sys/dev/arcmsr/arcmsr.c

411

CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/

sys/dev/arcmsr/arcmsr.c

4176

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */

sys/dev/arcmsr/arcmsr.c

4177

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);

sys/dev/arcmsr/arcmsr.c

4190

CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */

sys/dev/arcmsr/arcmsr.c

4191

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);

sys/dev/arcmsr/arcmsr.c

4199

CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */

sys/dev/arcmsr/arcmsr.c

4200

CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);

sys/dev/arcmsr/arcmsr.c

4207

CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */

sys/dev/arcmsr/arcmsr.c

4209

CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);

sys/dev/arcmsr/arcmsr.c

4236

CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);

sys/dev/arcmsr/arcmsr.c

4237

CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);

sys/dev/arcmsr/arcmsr.c

4238

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);

sys/dev/arcmsr/arcmsr.c

4265

CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */

sys/dev/arcmsr/arcmsr.c

4266

CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */

sys/dev/arcmsr/arcmsr.c

4267

CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */

sys/dev/arcmsr/arcmsr.c

4268

CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */

sys/dev/arcmsr/arcmsr.c

4269

CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */

sys/dev/arcmsr/arcmsr.c

4284

CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);

sys/dev/arcmsr/arcmsr.c

4285

CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);

sys/dev/arcmsr/arcmsr.c

4286

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);

sys/dev/arcmsr/arcmsr.c

4287

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);

sys/dev/arcmsr/arcmsr.c

4306

CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */

sys/dev/arcmsr/arcmsr.c

4307

CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);

sys/dev/arcmsr/arcmsr.c

4308

CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */

sys/dev/arcmsr/arcmsr.c

4309

CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */

sys/dev/arcmsr/arcmsr.c

431

CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/

sys/dev/arcmsr/arcmsr.c

4310

CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100);

sys/dev/arcmsr/arcmsr.c

4311

CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);

sys/dev/arcmsr/arcmsr.c

4321

CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);

sys/dev/arcmsr/arcmsr.c

4322

CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884);

sys/dev/arcmsr/arcmsr.c

4323

CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32);

sys/dev/arcmsr/arcmsr.c

4324

CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32);

sys/dev/arcmsr/arcmsr.c

4325

CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE);

sys/dev/arcmsr/arcmsr.c

4327

CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32);

sys/dev/arcmsr/arcmsr.c

4328

CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32);

sys/dev/arcmsr/arcmsr.c

4329

CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE);

sys/dev/arcmsr/arcmsr.c

4330

CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);

sys/dev/arcmsr/arcmsr.c

4332

CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);

sys/dev/arcmsr/arcmsr.c

4357

CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);

sys/dev/arcmsr/arcmsr.c

4359

CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);

sys/dev/arcmsr/arcmsr.c

4482

CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1)); /* host buffer low addr, bit0:1 all buffer active */

sys/dev/arcmsr/arcmsr.c

4483

CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */

sys/dev/arcmsr/arcmsr.c

4484

CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1); /* set host buffer physical address */

sys/dev/arcmsr/arcmsr.c

452

CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/

sys/dev/arcmsr/arcmsr.c

469

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);

sys/dev/arcmsr/arcmsr.c

4853

CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/

sys/dev/arcmsr/arcmsr.c

4854

CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */

sys/dev/arcmsr/arcmsr.c

4885

CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/

sys/dev/arcmsr/arcmsr.c

4886

CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */

sys/dev/arcmsr/arcmsr.c

504

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);

sys/dev/arcmsr/arcmsr.c

505

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);

sys/dev/arcmsr/arcmsr.c

522

CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);

sys/dev/arcmsr/arcmsr.c

539

CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);

sys/dev/arcmsr/arcmsr.c

541

CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);

sys/dev/arcmsr/arcmsr.c

649

CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);

sys/dev/arcmsr/arcmsr.c

672

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);

sys/dev/arcmsr/arcmsr.c

673

CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);

sys/dev/arcmsr/arcmsr.c

684

CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);

sys/dev/arcmsr/arcmsr.c

695

CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);

sys/dev/arcmsr/arcmsr.c

697

CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);

sys/dev/arcmsr/arcmsr.c

903

CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/