cmd_status
sc->cmd_status = m_status;
slave, len, cmd, sc->cmd_status \
if (sc->cmd_status & (1<<10)) {
uint32_t cmd_status;
__le32 cmd_status;
u32 cmd_status;
&cmd_status, tx_counter, rx_counter, NULL);
if (!retval && cmd_status != I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
u32 cmd_status;
&cmd_status, &tx_time_dur, &rx_time_dur, NULL);
if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
&cmd_status,
if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
u32 *cmd_status, u32 *data0, u32 *data1,
if (!cmd_status || !data0 || !data1) {
*cmd_status = LE32_TO_CPU(cmd->params.resp.cmd_status);
u32 *cmd_status, u32 *data0, u32 *data1,
enum i40e_status_code cmd_status;
cmd_status = i40e_enable_eee(&pf->hw, (bool)(!!new_state));
if (!cmd_status) {
} else if (cmd_status == I40E_ERR_CONFIG)
cm->cm_frame->header.cmd_status = MFI_STAT_OK;
if (hdr->cmd_status != MFI_STAT_OK) {
"MFI_DCMD_PD_LIST_QUERY failed %x\n", hdr->cmd_status);
if (hdr->cmd_status != MFI_STAT_OK) {
hdr->cmd_status);
hdr->cmd_status == MFI_STAT_INVALID_STATUS) {
if (dcmd->header.cmd_status == MFI_STAT_NOT_FOUND) {
if (dcmd->header.cmd_status != MFI_STAT_OK) {
dcmd->header.cmd_status);
if (sc->cm_map_abort || hdr->cmd_status != MFI_STAT_OK) {
if (hdr->cmd_status != MFI_STAT_OK) {
if ((hdr->cmd_status != MFI_STAT_OK) || (hdr->scsi_status != 0)) {
"scsi_status=%#x\n", cm, hdr->cmd_status, hdr->scsi_status);
hdr->cmd_status = MFI_STAT_INVALID_STATUS;
while (hdr->cmd_status == MFI_STAT_INVALID_STATUS) {
if (hdr->cmd_status == MFI_STAT_INVALID_STATUS) {
if (cm->cm_frame->header.cmd_status == MFI_STAT_OK) {
if (cm->cm_frame->header.cmd_status == MFI_STAT_OK) {
if (syspd && cm->cm_frame->header.cmd_status != MFI_STAT_OK)
if (ld_cm->cm_frame->header.cmd_status != MFI_STAT_OK) {
ioc->mfi_frame.hdr.cmd_status = cm->cm_frame->header.cmd_status;
error = copyout(&cm->cm_frame->header.cmd_status,
->lioc_frame.hdr.cmd_status,
pt->header.cmd_status = 0;
switch (pt->header.cmd_status) {
hdr->cmd_status = MFI_STAT_INVALID_STATUS;
while (hdr->cmd_status == MFI_STAT_INVALID_STATUS) {
if (hdr->cmd_status == MFI_STAT_INVALID_STATUS) {
if (hdr->cmd_status != MFI_STAT_OK) {
hdr->cmd_status);
hdr->cmd_status == MFI_STAT_INVALID_STATUS) {
mfi_init->header.cmd_status = MFI_STAT_INVALID_STATUS;
if (mfi_init->header.cmd_status == MFI_STAT_OK) {
mfi_init->header.cmd_status);
error = mfi_init->header.cmd_status;
mfi_cmd->cm_frame->header.cmd_status = MFI_STAT_OK;
mfi_cmd->cm_frame->dcmd.header.cmd_status = MFI_STAT_OK;
mfi_cmd->cm_frame->header.cmd_status = status;
mfi_cmd->cm_frame->dcmd.header.cmd_status = status;
mfi_cmd->cm_frame->header.cmd_status = ext_status;
mfi_cmd->cm_frame->dcmd.header.cmd_status = ext_status;
mfi_cmd->cm_frame->header.cmd_status = status;
mfi_cmd->cm_frame->dcmd.header.cmd_status = status;
mfi_cmd->cm_frame->header.cmd_status = status;
mfi_cmd->cm_frame->dcmd.header.cmd_status = status;
status = cmd_mfi->cm_frame->dcmd.header.cmd_status;
cmd_mfi->cm_frame->header.cmd_status = MFI_STAT_OK;
uint8_t cmd_status;
dw->mge_desc->cmd_status = MGE_RX_ENABLE_INT | MGE_DMA_OWNED;
status = dw->mge_desc->cmd_status;
dw->mge_desc->cmd_status = MGE_RX_ENABLE_INT | MGE_DMA_OWNED;
status = desc->cmd_status;
dw->mge_desc->cmd_status = 0;
dw->mge_desc->cmd_status |= MGE_TX_LAST | MGE_TX_FIRST |
status = desc->cmd_status;
int cmd_status = 0;
cmd_status |= MGE_TX_IP_HDR_SIZE(ip->ip_hl);
cmd_status |= MGE_TX_NOT_FRAGMENT;
cmd_status |= MGE_TX_GEN_IP_CSUM;
cmd_status |= MGE_TX_GEN_L4_CSUM;
cmd_status |= MGE_TX_GEN_L4_CSUM | MGE_TX_UDP;
dw->mge_desc->cmd_status |= cmd_status;
uint32_t cmd_status;
init_frame->cmd_status = 0xFF;
if (init_frame->cmd_status == 0xFF) {
if (init_frame->cmd_status == 0xFF)
if (init_frame->cmd_status == 0)
if (init_frame->cmd_status == 0xFF)
device_printf(sc->mrsas_dev, "IOC Init failed, status = 0x%x\n", init_frame->cmd_status);
dcmd->cmd_status = 0xFF;
frame_hdr->cmd_status = 0xFF;
if (frame_hdr->cmd_status == 0xFF) {
if (frame_hdr->cmd_status == 0xFF)
if (frame_hdr->cmd_status == 0xFF) {
cmd->cmd_status = 0xFF;
if (cmd->cmd_status == 0xFF) {
if (cmd->cmd_status == 0xFF) {
u_int8_t cmd_status = cmd->frame->hdr.cmd_status;
if (cmd_status != 0) {
if (cmd_status != MFI_STAT_NOT_FOUND)
device_printf(sc->mrsas_dev, "map sync failed, status=%x\n", cmd_status);
if (cmd_status == MFI_STAT_OK) {
"Jbod map sync failed, status=%x\n", cmd_status);
cmd->cmd_status = cmd->frame->io.cmd_status;
if (cmd->cmd_status == 0xFF)
cmd->cmd_status = 0;
dcmd->cmd_status = 0x0;
dcmd->cmd_status = 0x0;
dcmd->cmd_status = 0xFF;
dcmd->cmd_status = 0xFF;
dcmd->cmd_status = 0xFF;
dcmd->cmd_status = 0xFF;
dcmd->cmd_status = 0xFF;
dcmd->cmd_status = 0xFF;
abort_fr->cmd_status = 0xFF;
cmd->cmd_status = 0xFF;
if (cmd->cmd_status == 0xFF) {
cmd->cmd_status = 0;
dcmd->cmd_status = 0x0;
dcmd->cmd_status = 0x0;
u_int8_t cmd_status;
u_int8_t cmd_status; /* 02h */
u_int8_t cmd_status; /* 02h */
u_int8_t cmd_status; /* 02h */
u_int8_t cmd_status; /* 02h */
u_int8_t cmd_status; /* 02h */
u_int8_t cmd_status; /* 02h */
u_int8_t cmd_status; /* 02h */
u_int8_t cmd_status; /* 02h */
user_ioc->frame.hdr.cmd_status = MFI_STAT_OK;
memcpy(&user_ioc->frame.hdr.cmd_status, &cmd->frame->hdr.cmd_status,
memcpy(&ioc->ioc_frame.cmd_status, &cmd->frame->hdr.cmd_status,
*statusp = dcmd->header.cmd_status;
else if (dcmd->header.cmd_status != MFI_STAT_OK) {
mfi_status(dcmd->header.cmd_status));
static int cmd_status(int argc, char *argv[]);
{"status", cmd_status,