sys/arm64/arm64/cmn600.c

54

#define WR8(sc, r, v) bus_write_8((sc)->sc_res[0], (r), (v))

sys/arm64/arm64/gic_v3.c

264

bus_write_8(rdist, offset, val);

sys/arm64/arm64/gicv3_its.c

344

bus_write_8((sc)->sc_its_res, (reg), (val))

sys/arm64/coresight/coresight_etm4x.c

129

bus_write_8(sc->res, TRCACVR(i), event->addr[i]);

sys/arm64/iommu/smmu.c

1120

bus_write_8(sc->res[0], SMMU_GERROR_IRQ_CFG0, 0);

sys/arm64/iommu/smmu.c

1124

bus_write_8(sc->res[0], SMMU_EVENTQ_IRQ_CFG0, 0);

sys/arm64/iommu/smmu.c

1129

bus_write_8(sc->res[0], SMMU_PRIQ_IRQ_CFG0, 0);

sys/arm64/iommu/smmu.c

1246

bus_write_8(sc->res[0], SMMU_STRTAB_BASE, strtab->base);

sys/arm64/iommu/smmu.c

1250

bus_write_8(sc->res[0], SMMU_CMDQ_BASE, sc->cmdq.base);

sys/arm64/iommu/smmu.c

1273

bus_write_8(sc->res[0], SMMU_EVENTQ_BASE, sc->evtq.base);

sys/arm64/iommu/smmu.c

1286

bus_write_8(sc->res[0], SMMU_PRIQ_BASE, sc->priq.base);

sys/dev/acpica/acpi_apei.c

148

#define WRITE8(r, o, v) bus_write_8((r), (o), (v))

sys/dev/cxgbe/adapter.h

1308

bus_write_8(sc->regs_res, reg, val);

sys/dev/dpaa2/dpaa2_rc.c

3234

bus_write_8(mcp->map, sizeof(uint64_t) * i, cmd->params[i-1]);

sys/dev/dpaa2/dpaa2_rc.c

3240

bus_write_8(mcp->map, 0, cmd->header);

sys/dev/dpaa2/dpaa2_swp.c

1022

bus_write_8(map, offset + sizeof(uint64_t) * i, cmd->params[i]);

sys/dev/dpaa2/dpaa2_swp.c

1105

bus_write_8(map, offset + sizeof(uint64_t) * i, cmd->params[i]);

sys/dev/dpaa2/dpaa2_swp.c

872

bus_write_8(map,

sys/dev/dpaa2/dpaa2_swp.c

887

bus_write_8(map,

sys/dev/dpaa2/dpaa2_swp.c

970

bus_write_8(map, offset + sizeof(uint64_t) * i, cmd->params[i]);

sys/dev/pci/pci_user.c

1096

bus_write_8(res, offset, pbi->pbi_value);

sys/dev/proto/proto_core.c

436

bus_write_8(r->r_d.res, ofs, buf.x8[0]);

sys/dev/qat/include/common/adf_accel_devices.h

483

bus_write_8(csr_base, csr_offset, val)

sys/dev/qlnx/qlnxe/qlnx_os.c

5243

bus_write_8(((qlnx_host_t *)cdev)->pci_reg, offset, value);

sys/dev/qlnx/qlnxr/qlnxr_verbs.c

5185

bus_write_8(ha->pci_dbells, reg_addr, cq->db.raw);

sys/dev/vnic/nic_main.c

373

bus_write_8(nic->reg_base, offset, val);

sys/dev/vnic/nicvf_main.c

798

bus_write_8(nic->reg_base, offset, val);

sys/dev/vnic/nicvf_main.c

813

bus_write_8(nic->reg_base, offset + (qidx << NIC_Q_NUM_SHIFT), val);

sys/dev/vnic/thunder_bgx.c

230

bus_write_8(bgx->reg_base, addr, val);

sys/dev/vnic/thunder_bgx.c

240

bus_write_8(bgx->reg_base, addr, val | bus_read_8(bgx->reg_base, addr));

sys/dev/vnic/thunder_mdio.c

145

bus_write_8((sc)->reg_base, (reg), (val))

sys/dev/xilinx/if_xae.c

75

#define XAE_WR8(_sc, _reg, _val) bus_write_8((_sc)->res[0], _reg, _val)

sys/dev/xilinx/if_xae.c

80

#define AXIDMA_WR8(_sc, _reg, _val) bus_write_8((_sc)->dma_res, _reg, _val)

sys/powerpc/powernv/opal_pci.c

198

bus_write_8(sc->r_reg, 0x210, PHB3_TCE_KILL_INVAL_ALL);

sys/riscv/sifive/sifive_ccache.c

58

#define WR8(sc, off, val) (bus_write_8((sc)->res, (off), (val)))

sys/x86/iommu/amd_iommu.h

181

bus_write_8(unit->mmio_res, reg, val);

sys/x86/iommu/intel_dmar.h

316

bus_write_8(unit->regs, reg, val);