bus_timing_normal
cts->ios.timing = is_highspeed == 1 ? bus_timing_hs : bus_timing_normal;
case bus_timing_normal:
for (timing = bus_timing_mmc_ddr52; timing > bus_timing_normal; timing--) {
cts->ios.timing = bus_timing_normal;
case bus_timing_normal:
case bus_timing_normal:
case bus_timing_normal:
for (timing = bus_timing_max; timing > bus_timing_normal; timing--) {
setbit(&ivar->timings, bus_timing_normal);
bus_timing_normal; timing--) {
if ((ivar->timings & ~(1 << bus_timing_normal)) == 0)
mmcbr_set_timing(dev, bus_timing_normal);
mmcbr_set_timing(dev, bus_timing_normal);
timing == bus_timing_normal || bus_width == bus_width_1)
case bus_timing_normal:
case bus_timing_normal:
rtsx_set_sd_timing(sc, bus_timing_normal);
case bus_timing_normal:
if (ios->timing == bus_timing_normal)