bus_read_8
#define RD8(sc, r) bus_read_8((sc)->sc_res[0], (r))
typer = bus_read_8(r_res, offset + GICR_TYPER);
return (bus_read_8(rdist, offset));
bus_read_8((sc)->sc_its_res, (reg))
evtq->lc.val = bus_read_8(sc->res[0], evtq->prod_off);
q->lc.val = bus_read_8(sc->res[0], q->prod_off);
#define READ8(r, o) bus_read_8((r), (o))
return bus_read_8(sc->regs_res, reg);
val = bus_read_8(mcp->map, 0);
bus_read_8(mcp->map, i * sizeof(uint64_t));
rsp->params[i] = bus_read_8(map, offset + i * sizeof(uint64_t));
rsp->params[i] = bus_read_8(map, offset + i * sizeof(uint64_t));
bus_read_8((sc)->regs, ENETC_PORT_BASE + (reg))
pbi->pbi_value = bus_read_8(res, offset);
buf.x8[0] = bus_read_8(r->r_d.res, ofs);
#define ADF_CSR_RD64(csr_base, csr_offset) bus_read_8(csr_base, csr_offset)
#define READ_REG64(ha, reg) bus_read_8((ha->pci_reg), reg)
return (bus_read_8(sc->mem_res, off));
val = bus_read_8(nic->reg_base, offset);
return (bus_read_8(nic->reg_base, offset));
return (bus_read_8(nic->reg_base, offset + (qidx << NIC_Q_NUM_SHIFT)));
return (bus_read_8(bgx->reg_base, addr));
bus_write_8(bgx->reg_base, addr, val | bus_read_8(bgx->reg_base, addr));
bus_read_8((sc)->reg_base, (reg))
#define XAE_RD8(_sc, _reg) bus_read_8((_sc)->res[0], _reg)
#define AXIDMA_RD8(_sc, _reg) bus_read_8((_sc)->dma_res, _reg)
bus_read_8(sc->sc_mem, XIVE_TM_SPC_PULL_POOL_CTX);
#define RD8(sc, off) (bus_read_8((sc)->res, (off)))
return (bus_read_8(unit->mmio_res, reg));
return (bus_read_8(unit->regs, reg));