bhnd_bus_read_4
ioctl = bhnd_bus_read_4(r, BCMA_DMP_IOCTRL);
bhnd_bus_read_4(r, BCMA_DMP_IOCTRL);
*((uint32_t *)value) = bhnd_bus_read_4(r, offset);
dmpcfg = bhnd_bus_read_4(dinfo->res_agent, BCMA_DMP_CONFIG);
oobw = bhnd_bus_read_4(dinfo->res_agent,
selout = bhnd_bus_read_4(dinfo->res_agent, BCMA_DMP_OOBSELOUT(
rst = bhnd_bus_read_4(dinfo->res_agent, BCMA_DMP_RESETSTATUS);
rst = bhnd_bus_read_4(dinfo->res_agent, BCMA_DMP_RESETCTRL);
bhnd_bus_read_4(dinfo->res_agent, BCMA_DMP_RESETCTRL); /* read-back */
DEVMETHOD(bhnd_bus_read_4, bhnd_read_4),
return (bhnd_bus_read_4(iores->mapped, offset));
bhnd_bus_read_4((_clkctl)->cc_res, (_clkctl)->cc_res_offset)
clkst = bhnd_bus_read_4(clkctl->cc_res, clkctl->cc_res_offset);
DEVMETHOD(bhnd_bus_read_4, bhndb_bus_read_4),
pcaps = bhnd_bus_read_4(chipc_sc->core, BHND_PMU_CAP);
cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST));
cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL);
otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST);
cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES);
cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT);
regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG);
regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
value = bhnd_bus_read_4(sc->mem_res, offset);
bhnd_bus_read_4((sc)->mem_res, (off))
n = bhnd_bus_read_4(sc->res, CHIPC_CLKC_N);
m = bhnd_bus_read_4(sc->res, creg);
clkreg = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL);
div = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL);
div = bhnd_bus_read_4(sc->res, CHIPC_SYS_CLK_CTL);
pll_on_delay = bhnd_bus_read_4(sc->res, CHIPC_PLL_ON_DELAY) + 2;
scc = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL);
scc = bhnd_bus_read_4(sc->res, CHIPC_SYS_CLK_CTL);
bhnd_bus_read_4((_sc)->mem_res, (_reg))
bhnd_bus_read_4(BHND_PCI_SOFTC(_sc)->mem_res, (_reg))
sc->caps = bhnd_bus_read_4(sc->res, BHND_PMU_CAP);
return (bhnd_bus_read_4(sc->res, reg));
if (bhnd_bus_read_4(r, SIBA_CFG0_TMSTATEHIGH) & SIBA_TMH_SERR) {
imstate = bhnd_bus_read_4(r, SIBA_CFG0_IMSTATE);
ts_low = bhnd_bus_read_4(r, SIBA_CFG0_TMSTATELOW);
idl = bhnd_bus_read_4(r, SIBA_CFG0_IDLOW);
*((uint32_t *)value) = bhnd_bus_read_4(dinfo->cfg_res[0],
imcfg = bhnd_bus_read_4(dinfo->cfg_res[0], SIBA_CFG0_IMCONFIGLOW);
rval = bhnd_bus_read_4(r, reg);
bhnd_bus_read_4(r, reg); /* read-back */
rval = bhnd_bus_read_4(r, reg);