ata_mode2idx
int ata_mode2idx(int mode);
piotimings[ata_mode2idx(piomode)], 4);
pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(piomode)], 1);
(piotimings[ata_mode2idx(piomode)] << offset), 4);
0x20 + (devno << 3), piotiming[ata_mode2idx(piomode)]);
timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
new40 = timings[ata_mode2idx(piomode)] << 8;
new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) |
(timings[ata_mode2idx(piomode)] & 0x03);
timings[devno] = chtiming[ata_mode2idx(piomode)];
new40 = timings[ata_mode2idx(piomode)] << 8;
new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) |
(timings[ata_mode2idx(piomode)] & 0x03);
piotiming[ata_mode2idx(piomode)], 4);
pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(piomode)], 1);
timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
(piotimings[ata_mode2idx(piomode)] << offset), 4);
pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1);
pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2);
pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4);
pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
pci_write_config(parent, 0xab, pio_timings[ata_mode2idx(piomode)], 1);
pci_write_config(parent, reg - 0x08,timings[ata_mode2idx(piomode)], 1);