bcm_pcib_set_reg
bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val);
bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val);
bcm_pcib_set_reg(sc, REG_PCIE_HARD_DEBUG, 0);
bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val);
bcm_pcib_set_reg(sc, REG_EP_CONFIG_CHOICE, func_index);
bcm_pcib_set_reg(sc, REG_MSI_CLR, 1 << irq);
bcm_pcib_set_reg(sc, REG_MSI_EOI, 1);
bcm_pcib_set_reg(sc, REG_MSI_CLR, 0xffffffff);
bcm_pcib_set_reg(sc, REG_MSI_MASK_CLR, 0xffffffff);
bcm_pcib_set_reg(sc, REG_MSI_ADDR_LOW, (sc->msi_addr & 0xffffffff) | 1);
bcm_pcib_set_reg(sc, REG_MSI_ADDR_HIGH, (sc->msi_addr >> 32));
bcm_pcib_set_reg(sc, REG_MSI_CONFIG, REG_VALUE_MSI_CONFIG);
bcm_pcib_set_reg(sc, REG_DMA_WINDOW_LOW, REG_VALUE_DMA_WINDOW_LOW);
bcm_pcib_set_reg(sc, REG_DMA_WINDOW_HIGH, REG_VALUE_DMA_WINDOW_HIGH);
bcm_pcib_set_reg(sc, REG_DMA_CONFIG, REG_VALUE_DMA_WINDOW_CONFIG);
bcm_pcib_set_reg(sc, REG_BRIDGE_GISB_WINDOW, 0);
bcm_pcib_set_reg(sc, REG_DMA_WINDOW_1, 0);
bcm_pcib_set_reg(sc, REG_BUS_WINDOW_LOW, pci_base & 0xffffffff);
bcm_pcib_set_reg(sc, REG_BUS_WINDOW_HIGH, pci_base >> 32);
bcm_pcib_set_reg(sc, REG_CPU_WINDOW_LOW,
bcm_pcib_set_reg(sc, REG_CPU_WINDOW_START_HIGH,
bcm_pcib_set_reg(sc, REG_CPU_WINDOW_END_HIGH,
bcm_pcib_set_reg(sc, PCI_ID_VAL3,
bcm_pcib_set_reg(sc, REG_PCIE_HARD_DEBUG, tmp);