sys/arm64/iommu/smmureg.h

450

#define CD0_IPS_M (0x7UL << CD0_IPS_S)

sys/arm64/iommu/smmureg.h

451

#define CD0_IPS_32BITS (0x0UL << CD0_IPS_S)

sys/arm64/iommu/smmureg.h

452

#define CD0_IPS_36BITS (0x1UL << CD0_IPS_S)

sys/arm64/iommu/smmureg.h

453

#define CD0_IPS_40BITS (0x2UL << CD0_IPS_S)

sys/arm64/iommu/smmureg.h

454

#define CD0_IPS_42BITS (0x3UL << CD0_IPS_S)

sys/arm64/iommu/smmureg.h

455

#define CD0_IPS_44BITS (0x4UL << CD0_IPS_S)

sys/arm64/iommu/smmureg.h

456

#define CD0_IPS_48BITS (0x5UL << CD0_IPS_S)

sys/arm64/iommu/smmureg.h

457

#define CD0_IPS_52BITS (0x6UL << CD0_IPS_S) /* SMMUv3.1 only */